TW400621B - Metallization structure and the manufacture method thereof - Google Patents

Metallization structure and the manufacture method thereof Download PDF

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Publication number
TW400621B
TW400621B TW087101056A TW87101056A TW400621B TW 400621 B TW400621 B TW 400621B TW 087101056 A TW087101056 A TW 087101056A TW 87101056 A TW87101056 A TW 87101056A TW 400621 B TW400621 B TW 400621B
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Taiwan
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layer
metal layer
scope
manufacturing
patent application
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TW087101056A
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Chinese (zh)
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Kuan-Yang Liau
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United Microelectronics Corp
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Priority to TW087101056A priority Critical patent/TW400621B/en
Priority to US09/082,388 priority patent/US6114238A/en
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Publication of TW400621B publication Critical patent/TW400621B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A metallization structure - which provides a nitride metal layer to cover the surface of the metallization structure. And, the nitride metal layer is used to be the barrier layer with the inter metal dielectrics (IMD) - which is used to prevent the diffusion of the metal entrance into being the oxide of the inter metal dielectrics (IMD). Also, it avoids the condition of short and further influencing the reliability of the device. Meanwhile, the metallization structure is to form dielectrics on the substrate that has device structure. Next, it further includes: a metal layer formed on the dielectrics, a first barrier layer formed on the contact face between the metal layer, the dielectrics, and the second barrier layer formed on the surface of the metal layer which without in contact with the dielectrics.

Description

2476TWF.DOC/005 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（I ) 本發明是有關於一種金屬化結構及其製造法，且特 別是有關於一種預防金屬層間短路的金屬化結構及其製造雜。 第1圖係顯示一種習知技藝金屬i的結搆剖面圖。在一 具有兀件結構的基底_ 100上形成有一介電層102，介電層 1 立2多以氧化物構成。接著在介電層102中定義一開口，而 開口中形成有一塡J|麗旦殷金屬層j、〇4 ,另外，在盟口表面 霁形成有一阻障層1〇6/而在金屬層材料爲銅時，在一般的 CVD沉積溫度控制中’金屬銅即會擴散進入作爲介電層1〇2 的氧化物，因之，在介電層102與金屬銅1〇4接觸面形成 一阻障層(Barreir Layer)106 ’例如爵氮化鉅（TaN)或氮化鎢 CWN)，藉由阻障層的存在而限制金屬銅的擴散作用 (Diffusion)。然而在習知的嵌金法（Damascene)製程中，完 成化學機械硏磨法（CMP)的平坦化（Planarizati〇n)製程後， 會再於介電層102上形成一內金屬介電屬（Inter Metal dielectrics，IMD)108，而巴金屬介電層1处中形成有金屬插 塞110或溝渠(未繪出)等金屬化結構。然在銅形成的金屬層 104上表面，通常未形成有阻障層以預防氧化物沉積時銅擴 散進入內金屬介電層108,故而引起介雷層102逛內金匾> 電麗_1〇8間辑路（Short)的現象，造成元件的可靠度 (Reliability)降低。 有鑑於此，本發明的主要目的，就是在提供一置麗化金 屢層覆蓋在金屬層的表面,氮化金屬層係作爲與_內金屬介 電層間的阻障層，用以防止金屬擴散進入內金屬介電層而 (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 •丨脉_ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 2476TWF.DOC/005 2476TWF.DOC/005 經濟部中央標準局員工消費合作社印製 Μ Β7 五、發明説明（> ) 造成短路的情況。 爲達上述之目的，本發明提供一種金屬化的製造方法， 首先在一具有元件的基底上形成一介雷曆，而定義介電層 形成一開口。開口中形成有阻障層，之後塡入一第一金屬 層，並平坦化H一金屬層。接著再利用氮化法，將氮趨入 介電層與第一金屬層表面，而形成一氮氧化物層與一含氮 金屬層。續再去除含氮金屬層，並對基底表面形成一第二 金屬層，利用高溫製程使第二金屬層和含氮金屬層作用， 形成一氮化金屬層，最後再去除未反應之第二金屬層，故 而完成在金屬層上覆蓋一作爲阻障層之氮化金屬層。 爲達上述之目的，本發明提供一種金屬化的結構，在— 具有兀件結構的基底上形成有一介電層，之後更包括有. 一金屬層形成在介電層中，一第一阻障層形成在金屬層與 介電層之接觸面，以及一第二阻障層形成在金屬層未與^ 電層接觸的表面。 爲讓本發明之上述和其他目的、特徵、和優點能更日月_ 易懂，下文特舉一較佳實施例，並配合所附圖式，作胃糸田 說明如下： ' 圖式之簡單說明： 第1圖係顯示一種習知技藝金屬化的結構剖面W。 第2A圖至第2D圖係顯示根據本發明較佳實施例金_ 化之製造流程剖面圖。 其中，各圖標號之簡單說明如下： 100、200 :基底 本紙張尺度適用中國國家標準（CNS ) Α4規格（2!ΟΧ297公釐1 ^ —‘^—-；-----m}·裝— (請先閱讀背面之注意事項再填寫本頁)2476TWF.DOC / 005 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (I) The present invention relates to a metallized structure and a method for manufacturing the same, and more particularly to a metal for preventing short circuit between metals Chemical structure and its manufacturing. FIG. 1 is a cross-sectional view showing the structure of a conventional metal i. A dielectric layer 102 is formed on a substrate 100 having a component structure, and the dielectric layers 1 and 2 are mostly made of oxide. Next, an opening is defined in the dielectric layer 102, and a 塡 J | 丽丹 尹 metal layer j, 〇4 is formed in the opening. In addition, a barrier layer 106 / is formed on the surface of the alliance port, and a metal layer material is formed. In the case of copper, in general CVD deposition temperature control, 'metal copper will diffuse into the oxide which is the dielectric layer 102, so a barrier is formed at the interface between the dielectric layer 102 and the metal copper 104. Barreir layer 106 ', such as TaN or tungsten nitride (CWN), restricts the diffusion of metallic copper by the presence of a barrier layer. However, in the conventional Damascene process, after completing the Planarization process of the chemical mechanical honing process (CMP), an internal metal dielectric is formed on the dielectric layer 102 ( Inter Metal dielectrics (IMD) 108, and metallized structures such as metal plugs 110 or trenches (not shown) are formed in the P metal dielectric layer 1. However, on the upper surface of the metal layer 104 formed of copper, a barrier layer is usually not formed to prevent copper from diffusing into the inner metal dielectric layer 108 during the deposition of the oxide, thus causing the dielectric layer 102 to walk inside the gold plaque. 〇 The phenomenon of short circuit (Short), which reduces the reliability of the device (Reliability). In view of this, the main object of the present invention is to provide a metallized gold layer to cover the surface of the metal layer. The nitrided metal layer serves as a barrier layer with the inner metal dielectric layer to prevent metal diffusion. Enter the inner metal dielectric layer (please read the precautions on the back before filling in this page) Binding, binding, and pulses_ This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 2476TWF.DOC / 005 2476TWF .DOC / 005 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs Β7. 5. Description of Invention (>) Short circuit. To achieve the above object, the present invention provides a metallization manufacturing method. First, a dielectric calendar is formed on a substrate having a component, and a dielectric layer is defined to form an opening. A barrier layer is formed in the opening, and then a first metal layer is inserted and the H-metal layer is planarized. Then, the nitriding method is used to introduce nitrogen into the surface of the dielectric layer and the first metal layer to form an oxynitride layer and a nitrogen-containing metal layer. The nitrogen-containing metal layer is further removed, and a second metal layer is formed on the substrate surface. The high-temperature process is used to make the second metal layer and the nitrogen-containing metal layer act to form a nitrided metal layer. Finally, the unreacted second metal is removed. Layer, so that the metal layer is covered with a nitrided metal layer as a barrier layer. In order to achieve the above-mentioned object, the present invention provides a metallized structure, a dielectric layer is formed on a substrate having an element structure, and then further includes a metal layer formed in the dielectric layer and a first barrier A layer is formed on a contact surface between the metal layer and the dielectric layer, and a second barrier layer is formed on a surface of the metal layer that is not in contact with the dielectric layer. In order to make the above and other objects, features, and advantages of the present invention more understandable, the following is a description of a preferred embodiment with the accompanying drawings, as follows: '' Brief description of the drawings : Figure 1 shows a cross-section W of a metallized structure according to the prior art. Figures 2A to 2D are cross-sectional views showing the manufacturing process of metallization according to a preferred embodiment of the present invention. Among them, a brief description of each icon number is as follows: 100, 200: The paper size of the base is applicable to the Chinese National Standard (CNS) Α4 specification (2! 〇 × 297 mm 1 ^ — '^ —-; ----- m} · installation — (Please read the notes on the back before filling this page)

、1T 2476TWF.DOC/005 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（今） 102、202 :介電層 104:金屬化結構 106、206 :阻障層 108 :內金屬介電層1T 2476TWF.DOC / 005 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (today) 102, 202: Dielectric layer 104: Metallized structure 106, 206: Barrier layer 108: Internal metal dielectric Electrical layer

no : MSMM 208 :金屬層 208a:含氮金屬層 212 :第二金屬層 212a :氮化金屬層 實施例 第2A圖至第2D圖係顯示根據本發明較佳實施例金屬 化之製造流程剖面僵。 請參照第2A圖。在一具有元件結構(未繪出）的基底200 上形成一介電層〜2〇2，介電層202材料多爲氧化物。而介電 層2〇2在經微影蝕刻技術與嵌金法製程定義後，形成一開 口 204，之後’爲防止金屬對氧化物的擴散作用，在介電層 202與開口 204中形成一第一胆蘑_層_206，第一阻障層206 例如爲氮化f[iJaN)或氮化鎢（WN)，而以濺鍍（Sputtering) 昀方式形成。 請參照第2B圖，接著，在開口 204中形成一第一金屬 層208 ’例如爲銅，再經化學機械硏磨法去除介雷層2〇2 表面的藶一阻障層2〇6與平坦化第—金屬層2〇8,而暴露出 介電層202。之後，在暴露出的第一金屬層2〇8表面形成一 第一阻障層，以作爲隔離第一金屬層208與後續之內介電 ‘本紙張尺度適财( CNS ) ( 21GX297·^•釐) ' --- (請先閲讀背面之注意事項再填寫本頁)no: MSMM 208: Metal layer 208a: Nitrogen-containing metal layer 212: Second metal layer 212a: Nitrided metal layer Embodiments 2A to 2D are diagrams showing the cross-section of the metalized manufacturing process according to the preferred embodiment of the present invention. . Please refer to Figure 2A. A dielectric layer ~ 202 is formed on a substrate 200 having a device structure (not shown), and the material of the dielectric layer 202 is mostly an oxide. After the dielectric layer 202 is defined by the lithographic etching technology and the gold inlay process, an opening 204 is formed. Then, to prevent the metal from diffusing the oxide, a first layer is formed in the dielectric layer 202 and the opening 204. A bivalve layer 206, and the first barrier layer 206 is, for example, nitrided f [iJaN) or tungsten nitride (WN), and is formed in a sputtering method. Please refer to FIG. 2B. Next, a first metal layer 208 ′ is formed in the opening 204, for example, copper, and then the first barrier layer 20 and the flat surface of the dielectric layer 20 are removed by chemical mechanical honing. The first-metal layer 208 is exposed, and the dielectric layer 202 is exposed. After that, a first barrier layer is formed on the exposed surface of the first metal layer 208 to isolate the first metal layer 208 from the subsequent internal dielectrics. 'This paper scale suitable for wealth (CNS) (21GX297 · ^ • Li) '--- (Please read the notes on the back before filling this page)

! 2 476TWF.DOC/005 A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明（+) 層。而第二阻障層之形成，首先進行一氮化(Nitridation)製 程，例如利用電漿氮化或植入（Implant)的步驟，將氮210 趨入ίϋΜ一mUL第二金屬層2〇8暴露出的表面，而在介 電層202表面則形成一第氧化物層202a，暴露出的第一金 屬層2〇8表面則形成一食氮金屬層2〇8a。其中’以電漿法 進行氮_化·座麗釣能量約爲100-500eV，則氮化深度約爲 5〇A，而以植入法形成之氮化深度則可達約數百A ’能量則 約爲5〇KeV。而形成後之氮氧化物層202a與含氮金屬層 2〇8a厚度則視反應作用的程度而決定。 再如第2C圖所示。選擇性餽刻去除介電層202表面之 氮氧化物層202a，以濕蝕刻或乾蝕刻法進行均可。再對基 底2立0„灘鍍形成一第二金屬層繼續再經一高溫製程， 例如回火(Anneal)步驟，使含氮金屬層208a中的氮可與第 二金屬層H2反應，溫度控制在氮可學第二金屬層2〗2反 應即可，例如爲40(TC，則在含氮金屬層2〇8>殫面上形成 一氡化金屬麗4124，而第二金屬層212例_姐羞券墙(Ta)、 鈦層(Ti)或鎢層(W)時，則處i匕金屬層212a爲氣化氮化 鈦或氮化鎢。最後，再利用例如爲濕蝕刻法將介電層202 表面尙未與氮反應之金屬層212去除，則完成此金屬化結 構製程。 本發明係在暴露出的金屬屋產面JFU变二氮北金屬層，作 爲與內金屬介電層之阻障層，因之可限制金屬對內金屬介 電層的擴散作用，故可感少短路的現象，提高元件的可靠 度。 __ ^ ______ ______ ____ (諳先聞讀背面之注意事項再填寫本頁) .裝_ 、βτ 抹 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 2476TWF.DOC/005 A7 B7 五、發明説明（Γ) 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 I^ 裝 訂 ^ _·^ (請先間讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）! 2 476TWF.DOC / 005 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. The (+) layer of the invention description. For the formation of the second barrier layer, a Nitridation process is first performed. For example, plasma nitridation or implantation steps are used to expose the nitrogen 210 into the μM-mUL second metal layer 208. A first oxide layer 202a is formed on the surface of the dielectric layer 202, and a exposed nitrogen metal layer 208a is formed on the exposed surface of the first metal layer 208. Among them, the energy of Nitrogenation and Zirconium fishing by plasma method is about 100-500eV, and the nitriding depth is about 50A, and the nitriding depth formed by implantation method is about several hundred A. Energy It is about 50 KeV. The thickness of the oxynitride layer 202a and the nitrogen-containing metal layer 208a after the formation depends on the degree of reaction. As shown in Figure 2C. The selective feed etch can be used to remove the oxynitride layer 202a on the surface of the dielectric layer 202 by either wet etching or dry etching. Then, a second metal layer is formed on the substrate 2 to form a second metal layer, and then a high temperature process is performed, such as an Anneal step, so that nitrogen in the nitrogen-containing metal layer 208a can react with the second metal layer H2, and the temperature is controlled. The reaction can be performed on the nitrogen-learnable second metal layer 2 and, for example, 40 (TC, a tritium metal 4124 is formed on the nitrogen-containing metal layer 208>, and the second metal layer is 212 cases. When the wall (Ta), titanium layer (Ti) or tungsten layer (W) is used, the metal layer 212a is vaporized titanium nitride or tungsten nitride. Finally, for example, the wet The metal layer 212 on the surface of the electrical layer 202 that has not reacted with nitrogen is completed, and then the metallization structure process is completed. The present invention is a JFU-nitrogen-nitrogen-north metal layer on the exposed metal roof surface, which is used as a dielectric layer with the inner metal The barrier layer can limit the diffusion of metal to the inner metal dielectric layer, so it can reduce the short circuit phenomenon and improve the reliability of the device. __ ^ ______ ______ ____ (谙 Please read the precautions on the back before filling in this Page). Loading _, βτ The size of this paper is applicable to China National Standard (CNS) A4 (210X297 mm) 2476T WF.DOC / 005 A7 B7 V. Description of the Invention (Γ) Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit of the present invention and Within the scope, various modifications and retouching can be made, so the protection scope of the present invention shall be determined by the scope of the attached patent application. I ^ Binding ^ _ · ^ (Please read the notes on the back before filling in (This page) Printed by the Consumers Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This paper is sized for the Chinese National Standard (CNS) A4 (210X297 mm)

Claims (1)

經濟部中央標準局負工消費合作社印装 A8 2476TWF.DOC/005 B8 C8 D8 六、申請專利範圍 1.一種金屬化的製造方法，在一具有元件結構的基底上 形成有一介電層，該製造方法包括： 在該介電層定義一開口； 在該開口表面形成一第一阻障層； 在該第一阻障層上形成一塡滿該開口之第一金屬層，平 坦化該第一金屬層，暴露出該介電層；以及 在該第一金屬層的暴露表面形成一第二阻障層。 2. 如申請專利範圍第1項所述之製造方法，其中，該第 一金屬層包括銅。 3. 如申請專利範圍第1項所述之製造方法，其中，該第 二阻障層包括一氮化金屬層。 4. 如申請專利範圍第1項所述之製造方法，其中，在該 第一金屬層的暴露表面形成一第二阻障層的步驟更包括： 對該基底進行一氮化製程，該介電層表面形成一氮氧化 物層，該第一金屬層表面形成一含氮金屬層； 去除該介電層表面之該氮氧化物層； 在該基底表面形成一第二金屬層；以及 使該第二金屬層與該第一金屬層的暴露表面之該含氮 金屬層作用，形成一第二阻障層。 5. 如申請專利範圍第4項所述之製造方法，其中，在形 成該第二阻障層後更包括去除未反應的該第二金屬層的步 驟。 6. 如申請專利範圍第4項所述之製造方法，其中，該氮 化製程以一電漿法進行。 本紙張尺度逋用中國國家標準（CNS ) A4規格（210父297°公釐） (請先閲讀背面之注$項再填寫本頁) 裝- 訂 2476TWF.DOC/005 A8 B8 C8 D8 六、申請專利範圍 7. 如申請專利範圍第4項所述之製造方法，其中，該氮 化製程以一電漿法進行’則該氮化深度約爲50人。 8. 如申請專利範圍第7項所述之製造方法，其中，該電 漿法之能量約爲l〇〇-5〇〇eV左右。 9. 如申請專利範圍第4項所述之製造方法，其中，該氮 化製程以一離子植入法進行。 10. 如申請專利範圍第4項所述之製造方法，其中，該 氮化製程以一離子植入法進行，則該氮化深度約爲幾百A。 11. 如申請專利範圍第10項所述之製造方法，其中，該 離子植入法之能量約爲5OKeV。 12. 如申請專利範圍第4項所述之製造方法，其中，該 第二金屬層包括鉅，則該氮北金屬層爲氮化钽。 13. 如申請專利範圍第4項所述之製造方法，其中，該 第二金屬層包括鎢，則該氮化金屬層爲氮化鎢。 14. 如申請專利範圍第4項所述之製造方法，其中，該 第二金屬層包括鈦，則該氮化金屬層爲氮化鈦。 15_如申請專利範圍第4項所述之製造方法，其中，去 除該氮氧化物層以乾蝕刻法進行。 16. 如申請專利範圍第4項所述之製造方法，其中，去 除該氮氧化物層以濕蝕刻法進行。 17. 如申請專利範圍第4項所述之製造方法，其中，去 除未反應之該第二金屬層以濕蝕刻法進行。 I8·如申請專利範圍第4項所述之製造方法，其中，使 該第二金屬層與該第一金屬層的暴露表面之該含氮金屬層 豕紙張尺度適用中國國家樣率（CNS ) A4規格（210X297公釐） (請先聞讀背面之注$項再填寫本頁) 一—I------------ 絲. 經濟部中央梯牟局員工消费合作社印製 2476TWF.DOC/005 is8 C8 D8 六、申請專利範圍 作用包括進行一高溫製程的步驟。 19. 如申請專利範菌第18項所述之製造方法，其中，該 高溫製程溫度控制在足以生成該氮化金屬層。 20. —種金屬化的結構，提供一基底，該基底上形成有 一介電層；該金屬化結構包括： 一金屬層，形成在該介電層中； 一第一阻障層，形成在該金屬層與該介電層的接觸面； 以及 一第二阻障層，形成在該金屬層未與該介電層接觸的表 面。 21. 如申請專利範圍第20項所述之結構，其中，該第二 阻障層包括一氮化金屬層。 I I— n ^ —^1 ^― !"I I I —-# (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印裝 私紙張尺度逋用中國國家揉举（CNS ) A4規格（210X297公釐）Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A8 2476TWF.DOC / 005 B8 C8 D8 VI. Application scope 1. A metallized manufacturing method. A dielectric layer is formed on a substrate with a component structure. The method includes: defining an opening in the dielectric layer; forming a first barrier layer on a surface of the opening; forming a first metal layer filled with the opening on the first barrier layer to planarize the first metal Layer, exposing the dielectric layer; and forming a second barrier layer on the exposed surface of the first metal layer. 2. The manufacturing method according to item 1 of the scope of patent application, wherein the first metal layer includes copper. 3. The manufacturing method as described in item 1 of the patent application scope, wherein the second barrier layer comprises a metal nitride layer. 4. The manufacturing method according to item 1 of the scope of patent application, wherein the step of forming a second barrier layer on the exposed surface of the first metal layer further comprises: performing a nitriding process on the substrate, and the dielectric Forming a nitrogen oxide layer on the surface of the layer, forming a nitrogen-containing metal layer on the surface of the first metal layer; removing the nitrogen oxide layer on the surface of the dielectric layer; forming a second metal layer on the surface of the substrate; The two metal layers interact with the nitrogen-containing metal layer on the exposed surface of the first metal layer to form a second barrier layer. 5. The manufacturing method according to item 4 of the scope of patent application, wherein after forming the second barrier layer, a step of removing the unreacted second metal layer is further included. 6. The manufacturing method according to item 4 of the scope of patent application, wherein the nitriding process is performed by a plasma method. This paper uses the Chinese National Standard (CNS) A4 specification (210 ° 297 ° mm) (please read the note on the back before filling this page) Binding-Order 2476TWF.DOC / 005 A8 B8 C8 D8 VI. Application Patent scope 7. The manufacturing method described in item 4 of the scope of patent application, wherein the nitriding process is performed by a plasma method, and the nitriding depth is about 50 people. 8. The manufacturing method according to item 7 of the scope of patent application, wherein the energy of the plasma method is about 100-500 eV. 9. The manufacturing method according to item 4 of the scope of patent application, wherein the nitriding process is performed by an ion implantation method. 10. The manufacturing method described in item 4 of the scope of patent application, wherein the nitriding process is performed by an ion implantation method, and the nitriding depth is about several hundred A. 11. The manufacturing method according to item 10 of the scope of patent application, wherein the energy of the ion implantation method is about 5 OKeV. 12. The manufacturing method according to item 4 of the scope of patent application, wherein the second metal layer includes giant, and the nitrogen north metal layer is tantalum nitride. 13. The manufacturing method according to item 4 of the scope of patent application, wherein the second metal layer includes tungsten, and the metal nitride layer is tungsten nitride. 14. The manufacturing method according to item 4 of the scope of patent application, wherein the second metal layer includes titanium, and the metal nitride layer is titanium nitride. 15_ The manufacturing method as described in item 4 of the scope of patent application, wherein removing the oxynitride layer is performed by a dry etching method. 16. The manufacturing method according to item 4 of the scope of patent application, wherein the removal of the nitrogen oxide layer is performed by a wet etching method. 17. The manufacturing method according to item 4 of the scope of patent application, wherein removing the unreacted second metal layer is performed by a wet etching method. I8. The manufacturing method as described in item 4 of the scope of patent application, wherein the nitrogen-containing metal layer on the exposed surface of the second metal layer and the first metal layer is adapted to the Chinese national sample rate (CNS) A4 Specifications (210X297 mm) (please read the note on the back before filling in this page) I—I ------------ Silk. Printed by the Consumer Consumption Cooperative of the Central Ladder Bureau of the Ministry of Economic Affairs 2476TWF .DOC / 005 is8 C8 D8 6. The scope of patent application includes the steps of carrying out a high temperature process. 19. The manufacturing method according to item 18 of the patent application, wherein the high-temperature process temperature is controlled to be sufficient to form the nitrided metal layer. 20. A metallized structure that provides a substrate on which a dielectric layer is formed; the metallized structure includes: a metal layer formed in the dielectric layer; a first barrier layer formed on the substrate A contact surface between the metal layer and the dielectric layer; and a second barrier layer formed on a surface of the metal layer that is not in contact with the dielectric layer. 21. The structure of claim 20, wherein the second barrier layer comprises a metal nitride layer. II— n ^ — ^ 1 ^ ―! &Quot; III —- # (Please read the notes on the back before filling out this page) Printed paper scales printed by the Consumers ’Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, using the Chinese state ( CNS) A4 size (210X297 mm)
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