CN110676216A

CN110676216A - Interconnection structure and forming method thereof

Info

Publication number: CN110676216A
Application number: CN201911220622.4A
Authority: CN
Inventors: 许健; 胡思平; 王家文
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-12-03
Filing date: 2019-12-03
Publication date: 2020-01-10

Abstract

The embodiment of the application discloses a forming method of an interconnection structure and the interconnection structure, wherein the method comprises the following steps: providing a substrate with an opening, wherein the opening is used for exposing a conductive layer with metal in the substrate; processing the opening by using first plasma gas to obtain a metal compound; forming an interconnect structure over the treated opening, wherein a compound of the metal is reduced to the metal during formation of the interconnect structure.

Description

Interconnection structure and forming method thereof

Technical Field

The embodiments of the present application relate to the field of semiconductor devices and their manufacture, and relate to, but are not limited to, an interconnect structure and a method of forming the same.

Background

In back-end-of-line (BEOL) of a semiconductor device, after a semiconductor device layer is formed, a metal interconnection layer needs to be formed over the semiconductor device layer to lead out an electrode. Forming the metal interconnect layer generally includes: trenches are formed in the layer of insulating material and then metal is deposited within the trenches to form metal interconnect lines.

After forming the trench in the insulating material layer, the metal wire in the conductive layer is usually exposed, and since the metal wire has a grain boundary on its surface and the atomic arrangement on the grain boundary is looser than that in the grain boundary, abnormal cutting or surface dishing of the metal wire surface may be induced during the subsequent semiconductor process, and these defects may affect the filling range when the Physical Vapor Deposition (PVD) fills the metal, thereby causing an Electron Mobility (EM) failure.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a method for forming an interconnect structure and an interconnect structure, in which an opening is processed by using a plasma gas of nitrogen, so as to form a nitride of a metal on a conductive layer, the nitride forms a protective layer on a surface of the conductive layer, the protective layer can protect a metal surface in a BEOL process, thereby avoiding generation of defects, further avoiding an influence of the defects on a filling range when PVD fills metal, and improving an electrical connection performance of the interconnect structure.

The technical scheme of the embodiment of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a method for forming an interconnect structure, where the method includes:

providing a substrate with an opening, wherein the opening is used for exposing a conductive layer with metal in the substrate;

processing the opening by using first plasma gas to obtain a metal compound;

forming an interconnect structure over the treated opening, wherein a compound of the metal is reduced to the metal during formation of the interconnect structure.

In some embodiments, the first plasma gas includes nitrogen, and correspondingly, the processing the opening with the first plasma gas to obtain the metal compound includes:

and processing the opening by using a first plasma gas comprising nitrogen to obtain the nitride of the metal.

In some embodiments, the forming an interconnect structure over the processed opening, wherein, during the forming the interconnect structure, the compound of the metal is reduced to the metal, comprises:

forming a barrier layer on the treated opening, wherein a compound of the metal is reduced to the metal when the barrier layer is formed;

after the barrier layer is formed, a conductive material is filled in the opening through a PVD (physical vapor deposition) deposition process to obtain a metal filling layer so as to form the interconnection structure.

In some embodiments, the providing an open substrate, wherein the opening is used to expose a conductive layer with metal in the substrate, comprises:

sequentially forming a first dielectric layer, the conducting layer, an etching stop layer and a second dielectric layer on a provided semiconductor substrate to obtain the substrate;

and carrying out patterning treatment and etching on the second dielectric layer to obtain the substrate with the opening.

In some embodiments, the processing the opening with a first plasma gas including nitrogen to obtain the nitride of the metal includes:

and removing the opening by using first plasma gas comprising nitrogen to obtain the nitride of the metal, and removing impurities formed when the opening is etched.

In some embodiments, the method further comprises:

removing the opening by using second plasma gas to remove impurities formed when the opening is etched;

after the impurities are removed, the opening is treated with a first plasma gas including nitrogen.

In some embodiments, the conductive layer having metal therein has a metal wire, and the processing the opening with a first plasma gas including nitrogen to obtain a nitride of the metal includes:

and filling the first plasma gas acting on the surface of the metal wire into the process chamber, so that nitrogen in the first plasma gas reacts with the metal on the surface of the metal wire to generate the nitride of the metal.

In some embodiments, the metal wire is a copper wire, and the first plasma gas acting on the surface of the copper wire is correspondingly filled in the process chamber, so that nitrogen in the plasma gas reacts with copper on the surface of the copper wire to generate copper nitride.

In some embodiments, the forming a barrier layer over the processed opening includes:

a barrier layer having tantalum nitride is formed over the treated opening by a PVD deposition process.

In some embodiments, the method comprises:

in the process of forming the barrier layer, when metal ions in the metal nitride are reduced to the metal, nitrogen elements in the metal nitride are used to provide a nitrogen source for the tantalum nitride.

In a second aspect, an embodiment of the present application provides an interconnect structure, including:

a substrate including an opening for exposing a conductive layer within the substrate;

the barrier layer is filled in the opening;

a metal filling layer filled in the opening and located above the barrier layer

According to the forming method of the interconnection structure and the interconnection structure, the opening is processed by using the plasma gas of nitrogen, so that the metal nitride (such as copper nitride) is formed on the conductive layer with metal (such as copper), the nitride forms the protective layer on the surface of the conductive layer, the protective layer can protect the metal surface in a BEOL (beam induced thermal oxidation) process, the generation of defects is avoided, the influence of the defects on the filling range during metal filling of PVD (physical vapor deposition) is further avoided, and the electrical connection performance of the interconnection structure is improved.

Drawings

In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.

FIG. 1A is a schematic flow chart illustrating a method for forming an interconnect structure according to the related art;

FIG. 1B is a schematic diagram illustrating a structure of a substrate after an opening is etched in the related art;

fig. 1C is a schematic structural view of the related art after the opening is processed by plasma gas;

FIG. 1D is a schematic diagram illustrating a defect exposed on a surface of a conductive layer after wet cleaning in a related art process;

FIG. 1E is a schematic diagram illustrating a structure of a related art after a barrier layer is deposited on a defective metal surface;

fig. 2A is a schematic flow chart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure;

FIG. 2B is a schematic view of a substrate after processing the opening with a first plasma gas including nitrogen according to an embodiment of the present disclosure;

fig. 2C is a schematic view of a substrate structure after a wet cleaning process according to an embodiment of the present application;

FIG. 2D is a schematic diagram of a substrate after a metal barrier layer is deposited on the processed opening according to an embodiment of the present disclosure;

fig. 3 is a schematic flow chart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure;

fig. 4 is a schematic flow chart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure;

fig. 5 is a schematic flow chart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure;

fig. 6 is a schematic flowchart of a method for forming an interconnect structure according to an embodiment of the present disclosure;

fig. 7 is a schematic flowchart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure;

fig. 8 is a schematic flow chart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure;

fig. 9 is a schematic flowchart of a method for forming an interconnect structure according to an embodiment of the present disclosure;

fig. 10 is a schematic flow chart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure;

fig. 11 is a flowchart illustrating a method for forming an interconnect structure according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present application clearer, the following will describe specific technical solutions of the present application in further detail with reference to the accompanying drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

Where similar language of "first/second" appears in the specification, the following description is added, and where reference is made to the term "first \ second \ third" merely for distinguishing between similar items and not for indicating a particular ordering of items, it is to be understood that "first \ second \ third" may be interchanged both in particular order or sequence as appropriate, so that embodiments of the application described herein may be practiced in other than the order illustrated or described herein.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present application in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

In order to better understand the formation method of the interconnect structure and the interconnect structure provided in the embodiments of the present application, an analysis of the problems in the related art is first described.

Fig. 1A is a schematic flow chart of a method for forming an interconnect structure in the related art, as shown in fig. 1A, the method includes:

step S101, etching an opening on the substrate, wherein the opening exposes the conducting layer.

Fig. 1B is a schematic structural diagram of a substrate after an opening is etched in the related art, as shown in fig. 1B, the substrate includes a semiconductor substrate 10, a first dielectric layer 20, a conductive layer 30, an etch stop layer 40, and a second dielectric layer 50, which are sequentially disposed, where: the conductive layer 30 is disposed in the first dielectric layer 20, and has a metal wire, such as a copper wire, therein. An opening is formed in the second dielectric layer 50 by etching the second dielectric layer 50, which exposes the conductive layer 30.

During the etching process to form the opening to expose the conductive layer 30, a high molecular polymer (not shown in fig. 1B) is formed on the bottom of the opening and the surface of the sidewall of the opening due to the reaction of the etching gas and the material in the second dielectric layer 50. In general, the etching gas used may be a fluorine-containing gas. For example, if the etching gas is CF4 and the second dielectric layer is fluorosilicate glass, CF4 in the etching gas reacts with the fluorosilicate glass in the second dielectric layer, thereby forming a fluoropolymer on the surface of the opening. If the high molecular polymers cannot be removed, the high molecular polymers become a pollution source inside the product, so that the quality of metal filling in the opening subsequently is influenced, and the electrical connection performance of the semiconductor device is further influenced. Therefore, it is necessary to remove the high molecular polymer in the opening with the plasma gas (see step S102).

And step S102, processing the opening through conventional plasma gas to remove the high molecular polymer in the opening.

Here, the conventional plasma gas generally includes a plasma gas of hydrogen gas or carbon monoxide gas; in the related art, the high molecular polymer may be considered as an impurity. A plasma gas containing hydrogen or carbon monoxide is typically used for the treatment to remove impurities formed in the openings when etching the second dielectric layer 50.

Fig. 1C is a schematic structural diagram of the related art after the opening is processed by the conventional plasma gas, as shown in fig. 1C, when the high molecular polymer in the opening is removed by the conventional plasma gas, the metal in the conductive layer is also bombarded, and the metal (such as copper) may be sputtered to the sidewall, which may cause EM failure.

And step S103, cleaning the substrate processed in the step S102 by a wet process.

After the opening is treated by the conventional plasma gas, the opening needs to be cleaned by a wet process, and in the related art, the opening is usually cleaned by an acidic solution. When the metal is copper, for example, when the copper surface is cleaned with an acidic solution, the grain boundary atomic arrangement on the copper surface is loosened from the inside of the grain due to a certain difference in the particle arrangement orientation of the crystal grains, and the grain boundary atomic arrangement is disordered, so that many defects such as voids, dislocations, and bond deformation exist, and abnormal cutting and defects may be induced when the cleaning is performed with an acidic solution. Fig. 1D is a schematic diagram of a defect exposed on the surface of the conductive layer after being cleaned by a wet process in the related art, as shown in fig. 1D, the defect 60 is located on the surface of the conductive layer 30.

And step S104, depositing metal on the substrate processed in the step S103 to form a barrier layer and a filling layer in sequence.

A barrier layer is formed on the processed substrate, and then a filling layer is formed on the processed substrate. When depositing a metal on a substrate to form a barrier layer, fig. 1E is a schematic structural diagram of a related art after depositing a barrier layer on a defective metal surface, as shown in fig. 1E, the barrier layer cannot be formed at the position of the defect 60 due to the defect 60 on the metal surface. During deposition of the metal to form the fill layer (not shown in fig. 1E), an underfill condition may occur within the defect 60, thereby resulting in a filled void. Due to the presence of the filled voids, the resistance of the semiconductor device is increased and other adverse effects such as EM failure occur.

From the above, it can be seen that: in the related art, during the process of forming the metal interconnection layer, the metal wires in the conductive layer are usually exposed, and since the metal wires have grain boundaries on the surface and the atomic arrangement on the grain boundaries is looser than that in the grain boundaries, abnormal cutting or surface dishing of the metal wire surface may be induced during the subsequent semiconductor process, and these defects may affect the filling range when PVD fills metal, thereby causing EM failure.

Taking the metal wiring as an example of a copper wire, the surface of the copper wire has a grain boundary, and the grain boundary is susceptible to corrosion in the subsequent process because the atomic arrangement on the grain boundary is looser than that in the grain boundary. In the BEOL of semiconductor devices such as semiconductors, these grain boundaries will be weak points when performing etching processes or wet process contacts, which may induce abnormal cutting of the copper wire surface or generate surface dishing when etching processes, wet processes or other physical bombardment, and these defects may affect the filling range when PVD fills metals, resulting in EM failure.

Based on the problems in the related art, an embodiment of the present application provides a method for forming an interconnect structure, and fig. 2A is a schematic flow chart of the method for forming an interconnect structure provided in the embodiment of the present application, as shown in fig. 2A, the method includes:

step S201, providing a substrate with an opening, wherein the opening is used to expose a conductive layer with metal in the substrate.

With continued reference to fig. 1B, as shown in fig. 1B, the substrate includes a semiconductor substrate 10, a first dielectric layer 20, a conductive layer 30, an etch stop layer 40, and a second dielectric layer 50, which are sequentially disposed, wherein: the conductive layer 30 is disposed in the first dielectric layer 20, and has a metal wire, such as a copper wire, therein. An opening is formed in the second dielectric layer 50 by etching the second dielectric layer 50, which exposes the conductive layer 30.

The substrate provided by the embodiment of the present application may be a substrate in which various opening structures such as a through hole and a trench have been formed by etching, and may be, for example, a substrate in which a through hole is formed in the second dielectric layer 50 after etching; correspondingly, the opening can be regarded as a dielectric window formed after the substrate is etched through a through hole and/or a groove. In the embodiment of the present invention, copper (Cu) is generally used as the metal in the conductive layer having a metal, but the metal is not limited to copper, and may be, for example, tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), titanium (Ti), or an alloy of these materials. In some embodiments, the metal in the conductive layer may be in the form of a metal wire, such as a copper wire.

Step S202, processing the opening by using a first plasma gas to obtain a metal compound.

Since the opening is formed by etching, the etching gas reacts with the material of the second dielectric layer 50 to generate impurities (e.g., high molecular polymer). In the embodiment of the present invention, the etching gas is an etching gas containing at least one of fluorine-containing gases such as CF4, CF8, C5F8, C4F6, and CHF 3. The second dielectric layer 50 may include Fluorinated Silicate Glass (FSG), Black Diamond (BD), SiCOH-containing low dielectric constant (k) materials, non-porous low-k materials, and the like.

In an embodiment of the present invention, the first plasma gas includes nitrogen, and the opening is processed by the first plasma gas including nitrogen, so that impurities can be taken away, thereby reducing residual impurities. When the opening is treated by the first plasma including nitrogen gas, the plasma gas of nitrogen gas reacts with the metal in the conductive layer 30 to generate a nitride of the metal. Illustratively, the metal in the conductive layer 30 is copper, and the resulting nitride of the metal is copper nitride. In some embodiments, since the conductive layer 30 with metal in the substrate is exposed at the opening, the metal in the conductive layer 30 is oxidized to generate oxide of the metal, and the nitride of the metal is generated from the oxide of the metal when the opening is processed by the plasma gas of nitrogen.

Fig. 2B is a schematic structural diagram of the substrate after the openings are processed by the first plasma gas including nitrogen according to the embodiment of the present application, and as shown in fig. 2B, a metal or metal oxide on the surface of the conductive layer reacts with the plasma gas including nitrogen, so that a layer of metal nitride is generated on the surface of the metal, and the metal nitride can be considered to form a protective layer 80. The protective layer may prevent plasma from bombarding the metal surface during the processing of the opening with the first plasma gas comprising nitrogen gas to some extent, which may cause metal to sputter onto the second dielectric layer 50.

Fig. 2C is a schematic view of a substrate structure after a wet cleaning process according to an embodiment of the present disclosure, as shown in fig. 2C, during the wet cleaning process, the protection layer 80 may function to prevent the cleaning liquid from corroding the metal in the conductive layer 30, so that no defect is formed on the surface of the conductive layer 30 after the wet cleaning process is completed.

In the embodiment of the present application, regarding the time for performing the first processing on the opening by using the first plasma of nitrogen, the processing time of the plasma gas can be determined by comprehensively considering the factors such as the amount of impurities (high molecular polymers) generated in the opening in the actual process, the magnitude of the plasma bombardment power, the gas flow rate, and the thickness of the formed metal nitride. Illustratively, impurities are generated in the openings much and the thickness of the nitride to be formed is thick, so that the processing time of the plasma gas can be extended.

Step S203, forming an interconnection structure on the processed opening, wherein in the process of forming the interconnection structure, the compound of the metal is reduced to the metal.

In the embodiment of the present application, the formation of the interconnect structure in the opening of the process opening includes the processes of depositing a metal barrier layer 70 in the processed opening, and depositing a metal filling layer on the metal barrier layer 70. Fig. 2D is a schematic structural diagram of the substrate after the metal barrier layer 70 is deposited on the processed opening according to the embodiment of the present application, and as shown in fig. 2D, when the metal barrier layer 70 is deposited on the processed opening, the metal nitride on the surface of the metal in the conductive layer 30 is reduced, so as to avoid the defect 60 shown in fig. 1D, and thus the formed metal barrier layer 70 is continuous. When the nitride of the metal on the surface of the metal in the conductive layer 30 is reduced, the metal of the conductive layer 30 is made simple, thereby avoiding an influence on the resistance of the conductive layer 30. Therefore, according to the technical solution provided by this embodiment, when a metal filling layer (not shown in fig. 2D) is deposited on the metal barrier layer 70, a filling gap caused by a defect in the related art can be avoided, so that the problems of increasing the resistance of the semiconductor device and causing other adverse effects such as EM failure due to the existence of the filling gap are avoided.

By the above method, the opening is processed by plasma gas of nitrogen gas, so that the metal nitride (such as copper nitride) is formed on the conductive layer with metal (such as copper), and the nitride forms a protective layer on the surface of the conductive layer, because the protective layer can avoid defects on the metal surface caused by BEOL (wet cleaning) process, the influence on the filling range is avoided when the interconnection structure is formed, and the reliability of the interconnection structure is improved.

Based on the method for forming the interconnect structure provided in the foregoing embodiment, an embodiment of the present application further provides a method for forming an interconnect structure, and fig. 3 is a schematic flow chart of the method for forming an interconnect structure provided in the embodiment of the present application, as shown in fig. 3, the method includes:

step S301, providing a substrate with an opening, wherein the opening is used to expose a conductive layer with metal in the substrate.

Step S302, the opening is processed by using a first plasma gas including nitrogen gas, so as to obtain a nitride of the metal.

Step S303, forming a barrier layer on the processed opening, wherein, when the barrier layer is formed, the compound of the metal is reduced to the metal.

In the embodiments of the present application, the barrier layer is typically formed of tantalum, tantalum nitride, or an alloy of tantalum and tantalum nitride. A metal barrier layer is formed by a PVD deposition process in an opening in a substrate, illustratively, the opening including a trench and a via, and a metal barrier layer including tantalum nitride is formed by a PVD process on a bottom and sidewalls of the trench and on a bottom and sidewalls of the via.

In the embodiment of the application, when the metal barrier layer is formed, the nitride of the metal is reduced. For example, during PVD deposition, tantalum metal is vaporized, and during deposition on the surface of the opening, tantalum metal reacts with copper nitride to displace copper ions from the copper nitride.

Step S304, after forming the barrier layer, filling a conductive material in the opening by a PVD deposition process to obtain a metal filling layer, so as to form an interconnect structure.

In the embodiment of the present application, the conductive material is generally a metal material. The metal material may be the same as or different from the metal material in the conductive layer. In the embodiment of the present application, the conductive material to be filled is preferably the same as the metal material in the conductive layer. Illustratively, the metal in the conductive layer is copper, and the filled conductive material is also copper. In some embodiments, the conductive material may also be tungsten (W), ruthenium (Ru), cobalt (Co), nickel (Ni), titanium (Ti), or alloys thereof.

According to the method provided by the embodiment of the application, the opening is processed by using the plasma gas of nitrogen, so that the nitride of the metal is formed on the conductive layer with the metal, the nitride forms the protective layer on the surface of the conductive layer, and the protective layer can avoid defects possibly caused on the metal surface by a BEOL (wet cleaning process) process, so that the influence on the filling range is avoided when the interconnection structure is formed, and when the metal barrier layer is formed, the compound of the metal is reduced into the metal, so that the phenomenon that the resistance of the conductive layer is increased and the performance of a semiconductor is influenced due to different materials in the metal conductive layer is avoided.

Based on the foregoing embodiments, an embodiment of the present application further provides a method for forming an interconnect structure, and fig. 4 is a schematic flow chart of the method for forming an interconnect structure provided in the embodiment of the present application, as shown in fig. 4, the method includes:

step S401, sequentially forming a first dielectric layer, the conductive layer, an etching stop layer, and a second dielectric layer on a provided semiconductor substrate to obtain the substrate.

In the embodiment of the present application, the semiconductor substrate may be a single crystal silicon (monocrystalline) substrate. The first and second dielectric layers are low-k dielectric materials, and may include Fluorinated Silicate Glass (FSG), Black Diamond (BD), SiCOH-containing low dielectric constant (k) materials, non-porous low-k materials, and the like. The etch stop layer is typically a silicon nitride material.

In this embodiment of the application, the step S401 may be implemented by the following steps:

step S1, providing a semiconductor substrate;

step S2, forming a first dielectric layer on the semiconductor substrate;

step S3, forming a metal conductive layer in the dielectric layer;

step S4, forming an etching stopper layer on the semiconductor substrate;

step S5, forming a second dielectric layer on the etch stop layer;

step S6, forming a through hole by patterning and first etching the second dielectric layer;

step S7, patterning and etching the second dielectric layer after the first etching process to form a trench, wherein the via and the trench form an opening.

In this embodiment of the application, the sequence of step S6 and step S7 may be exchanged. That is, the trench may be etched first and then the opening may be etched.

Step S402, the second dielectric layer is processed in a graphical mode and etched, and the substrate with the opening is obtained.

In the embodiment of the present application, before etching the second dielectric layer, a patterning process is performed on the mask layer above the second dielectric layer. When the grooves and the through holes are formed by different methods, the graphic processing technology of the mask layer is different. When the hard mask layer comprises a metal hard mask, a photoresist may be formed on the metal hard mask to pattern the metal hard mask to define the location of the holes or trenches. After the holes or the grooves are etched, the residual photoresist is removed, and then the photoresist is formed on the metal hard mask so as to define the positions of the holes or the grooves.

In the embodiment of the present application, the opening may be a through hole formed in the second dielectric layer after etching, or may be a through hole and a trench formed in the second dielectric layer.

Step S403, processing the opening with a first plasma gas including nitrogen gas to obtain a nitride of the metal.

Step S404, forming an interconnect structure on the processed opening, wherein the compound of the metal is reduced to the metal in the process of forming the interconnect structure.

The method provided by the embodiment of the application comprises the steps of forming a first dielectric layer, a conductive layer, an etching stop layer and a second dielectric layer on a semiconductor substrate in sequence to obtain the substrate, etching the substrate, to obtain a substrate having the opening exposing the conductive layer having the metal, so that the openings are treated by a first plasma gas comprising nitrogen to form a nitride of the metal, the nitride forms a protective layer on the surface of the conductive layer, because the protective layer can prevent the metal surface from being damaged by BEOL (wet cleaning) process, therefore, the influence on the filling range is avoided when the interconnection structure is formed, and the metal compound is reduced into metal when the metal barrier layer is formed, so that the influence on the performance of a semiconductor caused by the increase of the resistance of the conductive layer due to the difference of materials in the metal conductive layer is avoided.

Based on the foregoing embodiments, an embodiment of the present application further provides a method for forming an interconnect structure, and fig. 5 is a schematic flow chart of the method for forming an interconnect structure provided in the embodiment of the present application, as shown in fig. 5, the method includes:

step S501, a first dielectric layer, the conductive layer, an etching stop layer and a second dielectric layer are sequentially formed on a provided semiconductor substrate to obtain the substrate.

Step S502, the second dielectric layer is processed in a graphical mode and etched, and the substrate with the opening is obtained.

Step S503, performing a cleaning process on the opening by using a first plasma gas including nitrogen to obtain a nitride of the metal, and removing impurities formed when the opening is etched.

In the embodiment of the present application, the opening is subjected to the cleaning process by replacing the plasma gas including hydrogen or carbon monoxide, which is generally used, with the first plasma gas including nitrogen. And a first plasma gas including nitrogen gas for removing impurities formed when etching the opening.

In an embodiment of the present invention, the impurities may be a high molecular polymer, such as a fluoropolymer, and the high molecular polymer is removed by a first plasma gas including nitrogen. When the high molecular polymer is removed, nitrogen reacts with metal or metal oxide on the surface of the metal to generate metal nitride.

Step S504, forming an interconnect structure on the processed opening, wherein in the process of forming the interconnect structure, the compound of the metal is reduced to the metal.

According to the method provided by the embodiment of the application, the high molecular polymer is removed by using the first plasma gas containing nitrogen, when the high molecular polymer is removed, the metal nitride is generated on the metal surface, and the metal surface can be protected in the wet cleaning process stage and the impurity removal stage by forming the metal nitride. The method avoids defects possibly caused by BEOL process on the metal surface, so that the influence on the filling range is avoided when an interconnection structure is formed, and the metal compound is reduced into metal when a metal barrier layer is formed, so that the influence on the performance of a semiconductor caused by the increase of the resistance of a conductive layer due to the difference of materials in the metal conductive layer is avoided.

An embodiment of the present application further provides a method for forming an interconnect structure, and fig. 6 is a schematic flowchart of the method for forming an interconnect structure provided in the embodiment of the present application, and as shown in fig. 6, the method includes:

step S601, sequentially forming a first dielectric layer, the conductive layer, an etching stop layer, and a second dielectric layer on a provided semiconductor substrate to obtain the substrate.

Step S602, performing patterning and etching on the second dielectric layer to obtain a substrate with the opening.

Step S603, performing a cleaning process on the opening by using a second plasma gas to remove impurities formed when the opening is etched.

In the embodiment of the present application, the second plasma gas may be a plasma gas that does not include nitrogen, for example, a plasma gas that includes hydrogen, or a plasma gas that includes carbon monoxide. In the embodiment of the application, impurities formed when the opening is etched are removed through the second plasma gas, and the impurities comprise high molecular polymers.

Step S604, after removing the impurities, processing the opening with a first plasma gas including nitrogen to obtain a nitride of the metal.

In the embodiment of the present application, after removing the impurities, the opening is processed by using the first plasma gas including nitrogen to obtain the nitride of the metal, at this time, the impurities in the opening are less, and the first plasma gas including nitrogen mainly functions to generate the nitride with the metal surface of the conductive layer.

Step S605, forming an interconnect structure on the processed opening, wherein in the process of forming the interconnect structure, the compound of the metal is reduced to the metal.

According to the method provided by the embodiment of the application, impurities are removed through the second plasma gas, the first plasma gas containing nitrogen is added to be used for processing the opening to generate the metal nitride, the generated metal nitride protects the metal in the wet process stage under the condition of ensuring clean cleaning, defects caused by the wet process stage are avoided, further, the influence of the defects on the filling range when the PVD is used for filling the metal is avoided, and the electric connection performance of the interconnection structure is improved.

An embodiment of the present application further provides a method for forming an interconnect structure, and fig. 7 is a schematic flowchart of the method for forming an interconnect structure provided in the embodiment of the present application, and as shown in fig. 7, the method includes:

step S701, sequentially forming a first dielectric layer, the conductive layer, an etching stop layer, and a second dielectric layer on a provided semiconductor substrate to obtain the substrate.

Step S702, the second dielectric layer is processed by patterning and etched, and a substrate with the opening is obtained.

Step S703 is to perform a cleaning process on the opening by using a second plasma gas to remove impurities formed during etching of the opening.

Step S704, performing a cleaning process on the opening by using a first plasma gas including nitrogen to obtain a nitride of the metal, and removing impurities formed when the opening is etched.

Step S705, forming a barrier layer on the processed opening, wherein, when the barrier layer is formed, the compound of the metal is reduced to the metal.

Step S706, after forming the barrier layer, filling a conductive material in the opening by a PVD deposition process to obtain a metal filling layer, so as to form an interconnect structure.

Based on the foregoing embodiments, an embodiment of the present application further provides a method for forming an interconnect structure, and fig. 8 is a schematic flowchart of the method for forming an interconnect structure provided in the embodiment of the present application, and as shown in fig. 8, the method includes:

step S801, providing a substrate with an opening, wherein the opening is used to expose a conductive layer with metal wires in the substrate.

In the embodiment of the present application, the metal wire is a metal wiring within a semiconductor. Illustratively, the metal wire is a copper wire.

Step S802, filling the first plasma gas acting on the surface of the metal wire into a process chamber, so that nitrogen in the first plasma gas reacts with the metal on the surface of the metal wire to generate the nitride of the metal.

In the embodiment of the application, the first plasma gas containing nitrogen is injected into the process chamber of the plasma equipment, so that the first plasma gas acts on the surface of the metal wire, the nitrogen in the first plasma gas reacts with the metal on the surface of the metal wire, and the metal nitride is generated. In connection with the above example, the first plasma gas acting on the surface of the copper wire is filled in the process chamber, so that the nitrogen in the plasma gas reacts with the copper on the surface of the copper wire to generate copper nitride.

Step S803, forming an interconnect structure on the processed opening, wherein in the process of forming the interconnect structure, the compound of the metal is reduced to the metal.

In an embodiment of the present application, a first plasma gas including nitrogen is introduced into the process chamber to treat the surface of the wire to form a nitride on the wire. The metal surface can be protected during the wet cleaning process and the impurity removal stage by forming a nitride of the metal. The method has the advantages that defects possibly caused by BEOL process on the metal surface are avoided, so that the influence on the filling range is avoided when the interconnection structure is formed, and the metal compound is reduced into metal when the metal barrier layer is formed, so that the influence on the performance of a semiconductor caused by the increase of the resistance of the conductive layer due to the difference of materials in the metal conductive layer is avoided.

An embodiment of the present application further provides a method for forming an interconnect structure, and fig. 9 is a schematic flowchart of the method for forming an interconnect structure provided in the embodiment of the present application, and as shown in fig. 9, the method includes:

step S901, providing a substrate with an opening, wherein the opening is used to expose a conductive layer with metal in the substrate.

Step S902, processing the opening with a first plasma gas including nitrogen gas to obtain a nitride of the metal.

Step S903, forming a barrier layer with tantalum nitride on the processed opening by PVD deposition process, wherein a compound of the metal is reduced to the metal when the barrier layer is formed.

In an embodiment of the present invention, forming a barrier layer having tantalum nitride over an opening by a PVD process includes vaporizing tantalum and applying tantalum and nitrogen together to a surface of the opening to form a barrier layer of tantalum nitride over the surface.

Step S904, after forming the barrier layer, filling a conductive material in the opening by a PVD deposition process to obtain a metal filling layer, so as to form an interconnect structure.

In the embodiment of the application, the barrier layer of tantalum nitride is formed by a PVD (physical vapor deposition) deposition process, so that the deposited barrier layer is more uniform, and the performance of a semiconductor device is improved.

Based on the foregoing embodiments, an embodiment of the present application further provides a method for forming an interconnect structure, and fig. 10 is a schematic flow chart of the method for forming an interconnect structure provided in the embodiment of the present application, and as shown in fig. 10, the method includes:

step S1001, a substrate with an opening is provided, wherein the opening is used for exposing a conductive layer with metal in the substrate.

Step S1002, the opening is processed by using a first plasma gas including nitrogen gas, so as to obtain a nitride of the metal.

Step S1003, forming a barrier layer with tantalum nitride on the processed opening by PVD deposition, wherein when the barrier layer is formed, a compound of the metal is reduced to the metal, and nitrogen in the metal nitride is used to provide a nitrogen source of the tantalum nitride.

In the embodiment, the nitrogen element in the metal nitride can be used to provide a nitrogen source for tantalum nitride, but when a barrier layer of tantalum nitride is PVD deposited, the nitrogen element in tantalum nitride is not all provided by the nitrogen element in the metal nitride, but other nitrogen sources can be reduced during the formation of tantalum nitride.

Step S1004, after forming the barrier layer, filling a conductive material in the opening by a PVD deposition process to obtain a metal filling layer, so as to form an interconnect structure.

In the embodiments of the present application, the nitrogen source in the metal nitride is used to provide tantalum to form tantalum nitride when the formed metal nitride is reduced to metal, that is, in the embodiments of the present application, the metal nitride, such as Cu — N, may react in the PVD step, the nitrogen element may become a source of nitrogen in the tantalum nitride, and the copper returns to the metal layer. Therefore, other nitrogen sources can be reduced, which in turn can reduce the cost of the deposition process.

An embodiment of the present application further provides a method for forming an interconnect structure, where fig. 11 is a schematic flow chart of the method for forming an interconnect structure provided in the embodiment of the present application, and as shown in fig. 11, the method includes:

step S1101, providing a substrate with an opening, wherein the opening is used for exposing a conductive layer with metal in the substrate.

Step S1102, performing a cleaning process on the opening by using a first plasma gas including nitrogen to obtain a nitride of the metal, and removing impurities formed when the opening is etched.

Step S1103, forming an interconnect structure on the processed opening, wherein in the process of forming the interconnect structure, the compound of the metal is reduced to the metal.

According to the method provided by the embodiment of the application, the opening is removed through the first plasma gas containing nitrogen to obtain the metal nitride, and impurities formed when the opening is etched are removed. The method has the advantages that impurities are removed, metal nitride is formed on the surface of the metal, the metal nitride forms a protective layer, the metal surface is prevented from being possibly defected by BEOL (back-end-of-line) technology, so that the influence on the filling range is avoided when the interconnection structure is formed, and the metal compound is reduced into metal when the metal barrier layer is formed, so that the influence on the performance of a semiconductor caused by the increase of the resistance of the conductive layer due to the difference of materials in the metal conductive layer is avoided.

Based on the foregoing methods, embodiments of the present application provide an interconnect structure, which is manufactured by the method for forming an interconnect structure provided in the foregoing embodiments, and the interconnect structure includes:

the barrier layer is filled in the opening;

and the metal filling layer is filled in the opening and is positioned above the barrier layer.

For technical details not disclosed in the embodiments of the interconnect structure of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.

It should be noted that the description of the interconnect structure in this embodiment is similar to the description of the method embodiment, and has similar beneficial effects to the method embodiment, and therefore, the description is not repeated. For technical details not disclosed in the embodiments of the interconnect structure of the present application, reference is made to the description of the above-mentioned method embodiments of the present application for understanding.

In the description herein, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example" or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The equivalent structure or equivalent flow conversion made by the content of the specification and the attached drawings, or directly or indirectly applied to other related technical fields, are all included in the protection scope of the patent of the application.

Claims

1. A method of forming an interconnect structure, the method comprising:

processing the opening by using a first plasma gas comprising nitrogen to obtain a nitride of the metal;

forming an interconnect structure over the processed opening, wherein the nitride of the metal is reduced to the metal during the formation of the interconnect structure.

2. The method of claim 1, wherein forming an interconnect structure over the processed opening, wherein the metal nitride is reduced to the metal during the forming the interconnect structure, comprises:

forming a barrier layer on the treated opening, wherein a nitride of the metal is reduced to the metal when the barrier layer is formed;

3. The method of claim 1, wherein providing an open substrate, wherein the opening is used to expose a conductive layer having a metal in the substrate, comprises:

4. The method of claim 3, wherein said treating the opening with a first plasma gas comprising nitrogen to obtain the nitride of the metal comprises:

5. The method of claim 3, further comprising:

6. The method of any one of claims 1 to 5, wherein the conductive layer having the metal therein has a metal wire therein, and the processing of the opening with the first plasma gas including nitrogen to obtain the nitride of the metal comprises:

7. The method according to claim 6, wherein the metal wire is a copper wire, and the first plasma gas acting on the surface of the copper wire is correspondingly filled in the process chamber, so that nitrogen in the plasma gas reacts with copper on the surface of the copper wire to generate copper nitride.

8. The method of any of claims 1 to 5, wherein forming a barrier layer over the treated opening comprises:

9. The method of claim 8, further comprising:

10. An interconnect structure made by the forming method of claims 1 to 10, comprising:

the barrier layer is filled in the opening;