CN105185787A - Method for manufacturing array substrate, array substrate and liquid crystal display panel - Google Patents
Method for manufacturing array substrate, array substrate and liquid crystal display panel Download PDFInfo
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- CN105185787A CN105185787A CN201510532057.0A CN201510532057A CN105185787A CN 105185787 A CN105185787 A CN 105185787A CN 201510532057 A CN201510532057 A CN 201510532057A CN 105185787 A CN105185787 A CN 105185787A
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- drain electrode
- protective layer
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- electrode cabling
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Abstract
The invention discloses a method for manufacturing an array substrate, the array substrate and a liquid crystal display panel. The method comprises the steps of forming a gate insulation layer on a substrate; forming a drain wire in the gate insulation layer; forming an insulation protective layer on the gate insulation layer and the drain wire; etching the insulation protective layer to etch off the part of the insulation protective layer that is positioned corresponding to the drain wire so as to form a pixel through hole at the location of the drain wire in the insulation protective layer; conducting the reduction treatment on the drain wire naked out of the pixel through hole by means of a preset reduction material; forming a pixel electrode layer on the insulation protective layer and electrically connecting the pixel electrode layer with the drain wire via the pixel through hole. According to the technical scheme of the invention, during the formation period of the pixel through hole, a high-impedance material generated due to the reaction between the drain wire and etching gases is reduced to a material for forming the drain wire. Therefore, the contact impedance between the pixel electrode layer of the array substrate and the drain wire of a TFT switch is effectively reduced.
Description
Technical field
The present invention relates to technical field of liquid crystal display, specifically, relate to the method, array base palte and the display panels that make array base palte.
Background technology
TFT-LCD is a kind of low-carbon green environment-friendly type display, and it is formed primarily of display panels and backlight.Wherein, display panels comprises: driving chip, polaroid, array base palte, color membrane substrates and the liquid crystal be positioned between array base palte and color membrane substrates.The core technology of TFT-LCD is the production technology of array base palte, and the production technology of array base palte then comprises the technical processs such as thin-film technique, exposure technology, etching technics and stripping technology.Wherein thin-film technique is divided into the pecvd process of metal sputtering and Inorganic Non-metallic Materials, and for these two kinds of thin-film techniques, etch process is respectively acid solution wet etching and chemical vapor dry etching.But, traditional SiN
xinsulating layer of thin-film can produce the problem that between pixel electrode and drain metal, contact impedance is excessive after carrying out via etch.
Summary of the invention
Technical problem to be solved by this invention is to solve the problem that in existing array base palte, between pixel electrode and drain metal, contact impedance is excessive.For solving the problem, one embodiment of the present of invention provide firstly a kind of method of manufacturing array substrate, and described method comprises:
Substrate forms gate insulator;
Described gate insulator is formed drain electrode cabling;
Described gate insulator and drain electrode cabling form insulating protective layer;
Described insulating protective layer is etched, to be etched away by the insulating protective layer corresponding to described drain electrode cabling position, thus in described insulating protective layer, corresponds to described drain electrode cabling position formation pixel via hole;
Default reducing substances is utilized to carry out reduction treatment to the drain electrode cabling exposed in described pixel via hole;
Described insulating protective layer forms pixel electrode layer, and described pixel electrode layer is electrically connected with described drain electrode cabling by described pixel via hole.
According to one embodiment of present invention, the step that described insulating protective layer etches is comprised:
Described insulating protective layer applies photoresist layer;
The light shield being provided with predetermined pattern is utilized to carry out exposure imaging to described photoresist layer, to be removed by the photoresist layer corresponding to described drain electrode cabling position;
Described insulating protective layer is etched, will do not etched away by the insulating protective layer that described photoresist layer covers, thus form described pixel via hole;
Described photoresist layer is peeled off.
According to one embodiment of present invention, dry quarter, will do not etched away by the insulating protective layer that described photoresist layer covers is carried out to described insulating protective layer.
According to one embodiment of present invention, the etching gas used when carrying out dry quarter to described insulating barrier comprises SiF
6, H
2and N
2.
According to one embodiment of present invention, described default reducing substances is H
2.
According to one embodiment of present invention, before the described drain electrode cabling of formation, first on described gate insulator, form barrier layer, on described barrier layer, form described drain electrode cabling subsequently.
Present invention also offers a kind of array base palte, described array base palte adopts method manufacture as above described in any one.
According to one embodiment of present invention, described array base palte comprises:
Substrate;
Gate insulator, it is formed on the substrate;
Drain electrode cabling, it is formed on described gate insulator;
Insulating protective layer, it is formed on described gate insulator and drain electrode cabling, and wherein, the position corresponding to described drain electrode cabling in described insulating protective layer is formed with pixel via hole;
Pixel electrode layer, it is formed on described insulating protective layer, and described pixel electrode layer is electrically connected with described drain electrode cabling by described pixel via hole.
According to one embodiment of present invention, described array base palte also comprises:
Barrier layer, it is formed between described gate insulator and drain electrode cabling, for stopping that the material forming described drain electrode cabling spreads to described gate insulator.
Present invention also offers a kind of display panels, described display panels comprises the array base palte described in described any one.
As can be seen from foregoing description, utilize the present embodiment the array base palte that obtains of the manufacturing method of array base plate that provides after forming pixel via hole, also add the process of drain electrode cabling being carried out to reduction treatment, this processing procedure can by pixel via hole formation stages because drain electrode cabling and the etching gas high impedance material that reacts and generate be reduced to the material forming the cabling that drains, thus the contact impedance between the drain electrode cabling effectively reducing pixel electrode layer and TFT switch in array base palte.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from specification, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in specification, claims and accompanying drawing and obtain.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, do simple introduction by accompanying drawing required in embodiment or description of the prior art below:
Fig. 1 is the structural representation of existing array base palte;
Fig. 2 is the cutaway view of pixel via structure in existing array base palte;
Fig. 3 is the cutaway view of pixel via structure in array base palte according to an embodiment of the invention.
Fig. 4 is the flow chart of manufacturing array substrate according to an embodiment of the invention;
Fig. 5 is according to an embodiment of the invention to the flow chart that insulating protective layer etches.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical problem whereby, and the implementation procedure reaching technique effect can fully understand and implement according to this.It should be noted that, only otherwise form conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other, and the technical scheme formed is all within protection scope of the present invention.
Meanwhile, in the following description, many details have been set forth for illustrative purposes, to provide thorough understanding of embodiments of the invention.But, it will be apparent to those skilled in the art that the present invention can detail here or described ad hoc fashion implement.
Fig. 1 shows the structural representation of the array base palte of existing TFT-LCD.
As shown in Figure 1, existing array base palte comprises: TFT switch 101, pixel electrode 102, public electrode cabling 103 and data wire 104 interlaced with each other and grid cabling 105.Wherein, pixel electrode 102 and public electrode cabling 103 together form storage capacitance 106.The source electrode of TFT switch 101 is connected with data wire 104, and grid is connected with grid cabling 105, and pixel electrode 102 is connected with the drain electrode of TFT switch 101 by pixel via hole 107.
Fig. 2 shows the cross-sectional view of pixel via hole 107 in existing array base palte.
As shown in Figure 2, in the pixel via structure of existing array base palte, gate insulator 202 is formed on substrate 201, and drain electrode cabling 203 is formed on gate insulator 202, and insulating protective layer 204 covers on gate insulator 202 and drain electrode cabling 203.Be formed with pixel via hole 205 in insulating protective layer 204, and pixel via hole 205 is formed in directly over drain electrode cabling 203.Like this, pixel electrode layer 206 just can realize being electrically connected with drain electrode cabling 203 by pixel via hole 205.In addition, in the pixel via structure of existing array base palte, being also provided with molybdenum between gate insulator 202 and drain electrode cabling 203 is material barrier layer 208.
In traditional array base palte, the material of insulating protective layer 204 is silicon nitride, and etching adopted etching gas to insulating protective layer 204 is then SiF
6/ He/O
2.In order to improve the wedge angle of pixel via hole 205, the O in etching gas
2n can be replaced with again
2.But, find, due to N by analyzing
2can react with the Cu forming the cabling 203 that drains under high-temperature plasma environment and generate CuN
x, namely generate the high impedance layer 207 be between drain electrode cabling 203 and pixel electrode layer 206 shown in Fig. 2.And CuN
ximpedance obviously large than Cu, this also causes pixel electrode layer 206 in existing array base palte and main cause that between drain electrode cabling 203, contact impedance is excessive just.
Based on above-mentioned analysis, present embodiments provide a kind of new array base palte, the difference of this array base palte and existing array base palte is mainly the structure at its pixel via hole place, and Fig. 3 shows the cutaway view of pixel via structure in this substrate.
As shown in Figure 3, in the array base palte that provides of the present embodiment, pixel via structure comprises: substrate 201, gate insulator 202, drain electrode cabling 203, insulating protective layer 204 and pixel electrode layer 206.Wherein, in this pixel via structure, gate insulator 202 is formed on substrate 201.In the present embodiment, substrate 201 preferably adopts glass substrate.It should be noted that, in other embodiments of the invention, substrate 201 can also adopt other rational materials (such as resin etc.) to realize, and the present invention is not limited thereto.
Drain electrode cabling 203 is formed on gate insulator 202, and insulating protective layer 204 to be formed on gate insulator 202 and drain electrode cabling 203 and cover gate insulating barrier 202 and drain electrode cabling 203.Be formed with pixel via hole 205 in insulating protective layer 204, pixel via hole 205 is formed in directly over drain electrode cabling 203.Like this, the subregion of drain electrode cabling 203 is just out exposed by pixel via hole 205.Therefore, the pixel electrode layer 206 be formed on insulating protective layer 204 just can realize being electrically connected with drain electrode cabling 203 by pixel via hole 205.Because the source electrode of TFT switch is connected with data wire, therefore when TFT switch closes, the signal that data line transfer comes just can conduct to pixel electrode layer 206 by TFT switch, drain electrode cabling 203 and pixel via hole 205, thus applies corresponding voltage to pixel electrode layer 206.
Comparison diagram 2 and Fig. 3 can find out, in the array base palte that the present embodiment provides, pixel via structure is no longer containing high impedance layer 207, so also just efficiently solves the problem that the drain electrode cabling Contact impedance of pixel electrode and TFT switch in existing array base palte is excessive.
Known by above-mentioned analysis, in existing array base palte, pixel electrode layer 206 is excessive with the drain electrode cabling 203 Contact impedance of TFT switch is due to drain electrode cabling 203 copper in the process forming pixel via hole 205 and the N in etching gas
2react and produce the CuN of high impedance
xcause.Therefore, in order to reduce pixel electrode layer 206 and TFT switch drain electrode cabling 203 between contact impedance, the present embodiment just manages the formation reducing high impedance layer in pixel via hole 205 forming process.
Particularly, in the present embodiment, after etching obtains pixel via hole 205, default reduzate material is also utilized to carry out reduction treatment to forming in etching the high impedance material generated in the process of pixel via hole 205, this high impedance material to be reduced to the material being formed drain electrode cabling 203, the contact impedance between the drain electrode cabling 203 so also just effectively reducing pixel electrode layer 206 and TFT switch.
Because the cabling 203 that drains in the array base palte that the present embodiment provides is for copper cabling, and the etching gas used when forming pixel via hole 205 comprises SiF
6, H
2and N
2, the high impedance material therefore formed is Cu and N
2the CuN that reaction generates
x.In order to by CuN
xbe reduced to Cu, in the present embodiment, preferably adopt H
2come CuN
xcarry out reduction treatment.
It should be noted that, in other embodiments of the invention, drain electrode cabling 203 and etching gas can also be other reasonable materials, therefore the high impedance material that etching obtains being formed in the process of pixel via hole 205 can also be other respective substance, and for this high impedance material, different reducing substances can be selected to carry out reduction treatment to it, the present invention is not limited thereto.
Simultaneously, also it is to be noted, in different embodiments of the invention, also can barrier layer be set between gate insulator 202 and drain electrode cabling 203, to stop that the material (such as Cu) being formed drain electrode cabling 203 spreads in amorphous silicon, thus avoid due to the diffusion of above-mentioned substance the impact that the active layer of thin-film transistor produces.In the present embodiment, the material on barrier layer preferably adopts molybdenum, and certainly, in other embodiments of the invention, barrier layer can also adopt other reasonable materials, the present invention is not limited thereto.
The present embodiment additionally provides a kind of method manufacturing above-mentioned array base palte, and Fig. 4 shows the flow chart of the method.
As shown in Figure 4, in the manufacturing method of array base plate that the present embodiment provides, first in step S401, on substrate 201, gate insulator 202 is formed.In the present embodiment, substrate 201 is preferably glass substrate.Certainly, in other embodiments of the invention, substrate 201 can also adopt other rational materials (such as resin etc.) to be formed, and the present invention is not limited thereto.Such as in one embodiment of the invention, substrate 201 can also adopt resin to be formed.
In step S402, gate insulator 202 forms drain electrode cabling 203.Wherein, in the present embodiment, the material of drain electrode cabling 203 is Cu.Certainly, in other embodiments of the invention, drain electrode cabling 203 can also adopt other rational electric conducting materials (such as Au or Ag etc.) to realize, and the present invention is not limited thereto equally.
After formation drain electrode cabling 203; the method that the present embodiment provides forms insulating protective layer 204 in step S403 on gate insulator 202 and drain electrode cabling 203; and in step s 404 insulating protective layer 204 is etched; to be fallen by insulating protective layer 204 partial etching corresponding to drain electrode cabling 203 position, thus in insulating protective layer 204, form required pixel via hole 205.
Particularly; as shown in Figure 5; when etching insulating protective layer 204; first on insulating protective layer 204, one deck photoresist layer 501 is applied; the light shield 502 being provided with predetermined pattern is utilized to carry out exposure imaging to this photoresist layer subsequently; thus the photoresist layer 501 of the position corresponding to drain electrode cabling 203 is removed, remove by the photoresist layer 501 directly over the pixel via hole 205 of wishing to obtain.Then etch insulating protective layer 204, in the present embodiment, preferably adopt dry mode of carving to etch insulating protective layer 204, the dry etching gas used of carving comprises SiF
6, H
2and N
2.The etching gas passed through under plasma environment can with the SiN forming insulating protective layer 204
xreact generation gaseous product, so also just etched away by the insulating protective layer 204 do not covered by photoresist layer 501, thus form pixel via hole 205, so also just exposes corresponding drain electrode cabling 203.
Finally the photoresist layer 501 of remnants is peeled off, just complete the etching to insulating protective layer 204 thus.
Due to the N in etching gas
2under high-temperature plasma environment, meeting and Cu reaction generate CuN
x, therefore in the process forming pixel via hole 205, the N in etching gas
2cuN is generated by inevitably reacting with the Cu forming the cabling 203 that drains
x.And CuN
xit is the main cause causing the drain electrode cabling Contact impedance of pixel electrode and TFT switch excessive.
In order to reduce pixel electrode and TFT switch drain electrode cabling between contact impedance, just need to reduce or eliminate the CuN that reaction produces
x.For this reason, again as shown in Figure 4, the method for the manufacturing array substrate that the present embodiment provides utilizes default reducing substances to carry out reduction treatment to the drain electrode cabling 203 exposed in step S405, reacting the CuN produced
xagain Cu is reduced to, thus the contact impedance between the drain electrode cabling effectively reducing pixel electrode and TFT switch.
The present embodiment needs the material carrying out reduction treatment to be CuN
x, therefore preset reducing substances and be preferably H
2.It should be noted that, in other embodiments of the invention, default reducing substances can also select other reasonable materials to come CuN
xreduce, the present invention is not limited thereto.Simultaneously, in other embodiments of the invention, drain electrode cabling and/or etching gas also can be other reasonable materials, and the material with high-impedance behavior that corresponding reaction produces also can utilize other rational reducing substances to carry out reduction treatment, and the present invention is not limited thereto equally.
Carrying out drain electrode cabling after reduction treatment completes, in step S406, on insulating protective layer 204, forming pixel electrode layer 206, and pixel electrode layer 206 being connected with the cabling 203 that drains by pixel via hole 205.
It should be noted that, in other embodiments of the invention, before formation drain electrode cabling 203, first can also form a barrier layer on gate insulator 202, form drain electrode cabling 203 over the barrier layer more subsequently.Wherein, barrier layer can stop material (such as Cu) diffusion in amorphous silicon (such as gate insulator 202) forming drain electrode cabling 203 effectively, thus avoids due to the diffusion of above-mentioned substance the impact that the active layer of thin-film transistor produces.In the present embodiment, the material on barrier layer preferably adopts molybdenum, and certainly, in other embodiments of the invention, barrier layer can also adopt other reasonable materials, the present invention is not limited thereto.
The present embodiment additionally provides a kind of display panels using above-mentioned array base palte.
As can be seen from foregoing description, utilize the present embodiment the array base palte that obtains of the manufacturing method of array base plate that provides after forming pixel via hole, also add the process of drain electrode cabling being carried out to reduction treatment, this processing procedure can by pixel via hole formation stages because drain electrode cabling and the etching gas high impedance material that reacts and generate be reduced to the material forming the cabling that drains, thus the contact impedance between the drain electrode cabling effectively reducing pixel electrode layer and TFT switch in array base palte.
It should be understood that disclosed embodiment of this invention is not limited to ad hoc structure disclosed herein, treatment step or material, and the equivalent of these features that those of ordinary skill in the related art understand should be extended to substitute.It is to be further understood that term is only for describing the object of specific embodiment as used herein, and and do not mean that restriction.
Special characteristic, structure or characteristic that " embodiment " mentioned in specification or " embodiment " mean to describe in conjunction with the embodiments comprise at least one embodiment of the present invention.Therefore, specification various places throughout occur phrase " embodiment " or " embodiment " might not all refer to same embodiment.
Conveniently, multiple project, construction unit and/or component units can appear in common list as used herein.But each element that these lists should be interpreted as in this list is identified as member unique separately respectively.Therefore, when not having reverse side to illustrate, in this list, neither one member only can appear in common list the actual equivalent of other member any being just interpreted as same list based on them.In addition, can also come together with reference to various embodiment of the present invention and example together with for the alternative of each element at this.Should be understood that, these embodiments, example and substitute and be not interpreted as equivalent each other, and be considered to representative autonomous separately of the present invention.
Although above-mentioned example is for illustration of the principle of the present invention in one or more application, but for a person skilled in the art, when not deviating from principle of the present invention and thought, obviously can in form, the details of usage and enforcement does various amendment and need not creative work be paid.Therefore, the present invention is limited by appending claims.
Claims (10)
1. a method for manufacturing array substrate, is characterized in that, described method comprises:
Substrate forms gate insulator;
Described gate insulator is formed drain electrode cabling;
Described gate insulator and drain electrode cabling form insulating protective layer;
Described insulating protective layer is etched, to be etched away by the insulating protective layer corresponding to described drain electrode cabling position, thus in described insulating protective layer, corresponds to described drain electrode cabling position formation pixel via hole;
Default reducing substances is utilized to carry out reduction treatment to the drain electrode cabling exposed in described pixel via hole;
Described insulating protective layer forms pixel electrode layer, and described pixel electrode layer is electrically connected with described drain electrode cabling by described pixel via hole.
2. the method for claim 1, is characterized in that, comprises the step that described insulating protective layer etches:
Described insulating protective layer applies photoresist layer;
The light shield being provided with predetermined pattern is utilized to carry out exposure imaging to described photoresist layer, to be removed by the photoresist layer corresponding to described drain electrode cabling position;
Described insulating protective layer is etched, will do not etched away by the insulating protective layer that described photoresist layer covers, thus form described pixel via hole;
Described photoresist layer is peeled off.
3. method as claimed in claim 2, is characterized in that, carries out dry quarter, will do not etched away by the insulating protective layer that described photoresist layer covers to described insulating protective layer.
4. method as claimed in claim 3, is characterized in that, the etching gas used when carrying out dry quarter to described insulating barrier comprises SiF
6, H
2and N
2.
5. the method according to any one of Claims 1 to 4, is characterized in that, described default reducing substances is H
2.
6. the method for claim 1, is characterized in that, before the described drain electrode cabling of formation, first on described gate insulator, forms barrier layer, forms described drain electrode cabling subsequently on described barrier layer.
7. an array base palte, is characterized in that, described array base palte adopts method manufacture according to any one of claim 1 ~ 6.
8. array base palte as claimed in claim 7, it is characterized in that, described array base palte comprises:
Substrate;
Gate insulator, it is formed on the substrate;
Drain electrode cabling, it is formed on described gate insulator;
Insulating protective layer, it is formed on described gate insulator and drain electrode cabling, and wherein, the position corresponding to described drain electrode cabling in described insulating protective layer is formed with pixel via hole;
Pixel electrode layer, it is formed on described insulating protective layer, and described pixel electrode layer is electrically connected with described drain electrode cabling by described pixel via hole.
9. array base palte as claimed in claim 8, it is characterized in that, described array base palte also comprises:
Barrier layer, it is formed between described gate insulator and drain electrode cabling, for stopping that the material forming described drain electrode cabling spreads to described gate insulator.
10. a display panels, is characterized in that, described display panels comprises the array base palte according to any one of claim 7 ~ 9.
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|---|---|---|---|
| CN201510532057.0A CN105185787B (en) | 2015-08-26 | 2015-08-26 | Make method, array substrate and the liquid crystal display panel of array substrate |
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| CN105185787B CN105185787B (en) | 2018-08-14 |
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