CN101022080A - Metal conducting wire and producing method thereof - Google Patents
Metal conducting wire and producing method thereof Download PDFInfo
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- CN101022080A CN101022080A CN 200710087532 CN200710087532A CN101022080A CN 101022080 A CN101022080 A CN 101022080A CN 200710087532 CN200710087532 CN 200710087532 CN 200710087532 A CN200710087532 A CN 200710087532A CN 101022080 A CN101022080 A CN 101022080A
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Abstract
This invention discloses a metal lead and its manufacturing method including the following steps: forming a first film on a base plate, a second film on the first film, forming a lead opening on the first and second films and exposing part of the top surface of the base plate, etching the opening side wall of the first film inward to let it shrink inward to form a side-directed notch between the second film and the base plate, forming a seed crystal layer on the top surfaces of the base plate exposed by the opening and the second film, carrying out plating to form a metal material on the surface of the seed crystal layer to be filled in the lead opening and the side-directed notch to form a metal layer, removing the second film and stripping the seed crystal layer and the metal material overlapped on the second film.
Description
Technical field
The present invention is about a kind of plain conductor and manufacture method thereof, particularly about a kind of plain conductor and manufacture method thereof that is applied to the display panels manufacturing process.
Background technology
Along with the progress that shows science and technology, compare with traditional CRT monitor, (thin film transistor liquid crystal display TFT-LCD) has the little and advantage that do not take up space of light, thin, low radiation and volume to Thin Film Transistor-LCD.Therefore, Thin Film Transistor-LCD has become main force's product of monitor market at present, is the fast development in response to liquid crystal display product, and the inter-industry competition of liquid crystal panel manufacturer increases day by day.
In the manufacture process of display panels, grid lead belongs to the first road patterned metal layer on substrate, so the architectural feature of grid lead is very big for the influence of operations such as subsequent deposition insulating barrier.In present technology, the above-mentioned first road patterned metal layer can utilize multilayer film to peel off the method that (lift-off) add deposition and make, and technological means is as described below.
Please refer to Figure 1A to Fig. 1 E, it is the method schematic diagram of known manufacturing patterned metal layer.At first the upper surface at a substrate 10 forms one first rete 12, a first metal layer 13 and one second rete 14 in regular turn.Then, on second rete 14, carry out photo-mask process, and form an opening 15 on second rete 14, and expose the first metal layer 13 of part, shown in Figure 1B.
Please refer to Fig. 1 C, 15 pairs of the first metal layers of opening 13 via second rete 14 carry out etching work procedure, up to first rete, 12 upper surfaces that expose part, and make the sidewall of the first metal layer 13 further be subjected to lateral etch, and between second rete 14 and first rete, form the side direction breach 15a of an indent.Wherein, the employed etching solution of this etching work procedure only can be to the first metal layer 13 generation effects, and perhaps in this etching work procedure, the etching selectivity of the first metal layer 13 is greater than other rete.
Please refer to Fig. 1 D, then deposition second metal level 16 that is to say second metal level 16 except being deposited on second rete, 14 upper surfaces above substrate 10 comprehensively, more is deposited on part first rete 12 upper surfaces by opening 15.
At last, mode such as useful etch is removed second rete 14.When second rete 14 is removed, can peels off second metal level 16 that (lift-off) is covered in second rete, 14 tops jointly, and only stay the first metal layer 13 and second metal level 16 at first rete, 12 upper surfaces.Shown in Fig. 1 E, second metal level 16 of staying first rete, 12 upper surfaces promptly becomes required plain conductor 161, and the first metal layer 13 and the plain conductor 161 formations first road patterned metal layer.
Please continue the E with reference to Fig. 1, because plain conductor 161 forms in the mode that deposits, therefore the gradient at the lead edge of plain conductor 161 both sides 161a can seem steeper.Yet when then carrying out subsequent handling such as depositing insulating layer, the situation that the steeper lead edge 161a of the gradient causes insulating barrier to adhere to bad or insulating barrier broken hole easily takes place, and then influence electrically, even causes the problem of short circuit or circuit malfunction.
Therefore, in view of in the above-mentioned known technology the weak point that still exists, provide one to be the effective solution of the necessary reality of current techniques to this.
Summary of the invention
A purpose of the present invention is to improve by method of manufacturing technology the too steep problem of edge's gradient of plain conductor.
Another object of the present invention is to by improving the too steep problem of edge's gradient of plain conductor, adhere to bad when reducing follow-up insulating layer deposition or the situation of broken hole takes place, and produce preferable electrical effect.
Another object of the present invention is to relax the gradient of plain conductor edge,, promote the yield of subsequent handling to increase the enough and to spare of follow-up insulating barrier operation.
The invention provides a kind of plain conductor, it comprises a crystal seed layer and a metal level.Wherein, crystal seed layer is formed on the substrate.Metal level is formed on the crystal seed layer, and the metal level two ends are step structure.
The invention provides a kind of manufacture method of plain conductor, comprise the following steps: to form a crystal seed layer on a substrate.Form one first rete on crystal seed layer.Form one second rete on first rete.Form a wire openings in first and second rete, and expose part crystal seed layer upper surface.Opening sidewalls to first rete carries out etching, and its sidewall is inwardly bounced back, and forms a side direction breach between second rete and crystal seed layer.Carry out an electroplating work procedure, fill a metal material in wire openings and side direction breach, and form a metal level.Remove first rete and second rete, and peel off the metal level on second rete.Remove the crystal seed layer that is not covered by metal level.
The invention provides a kind of manufacture method of plain conductor, comprise the following steps: to form one first rete on a substrate.Form one second rete on first rete.Form a wire openings in first and second rete, and expose the part upper surface of base plate.Opening sidewalls to first rete carries out etching, and its sidewall is inwardly bounced back, and forms a side direction breach between second rete and substrate.Form the upper surface of base plate and the second rete upper surface that a crystal seed layer exposes to the open air in wire openings.Carry out an electroplating work procedure, form a metal material, and be filled in wire openings and the side direction breach, and form a metal level in the crystal seed layer surface.Remove second rete, and peel off be laminated in second rete on crystal seed layer and metal material.
About the advantages and spirit of the present invention, and more detailed execution mode can be further understood by following execution mode and institute's accompanying drawing.
Description of drawings
In conjunction with appended diagram, can understand the plurality of advantages of foregoing and the present invention by following detailed description easily, wherein:
Figure 1A to Fig. 1 E is the manufacture method schematic diagram of known patterned metal layer;
Fig. 2 A to Fig. 2 H is the manufacture method schematic diagram of first embodiment of plain conductor of the present invention; And
Fig. 3 A to Fig. 3 J is the manufacture method schematic diagram of second embodiment of plain conductor of the present invention.
Wherein, Reference numeral:
10: 12: the first retes of substrate
13: 14: the second retes of the first metal layer
15: opening 15a: the side direction breach
161a: lead edge 20: substrate
21: 22: the first retes of crystal seed layer
Rete 24 in 23: the second: wire openings
24a: side direction lacks 25: metal material
251: metal level 26: metal barrier
27: gate insulator 30: substrate
31: the first rete 31a: gap
Rete 33 in 32: the second: wire openings
33a: side direction lacks 34: crystal seed layer
35: metal material 351: metal level
36: metal barrier 37: gate insulator
Embodiment
The manufacture method of plain conductor provided by the present invention is utilized multilayer film to peel off (lift-off) and is added electric plating method manufacturing, and comprises different embodiment types, is described in detail as follows.
First embodiment
Please refer to Fig. 2 A to Fig. 2 H, it is the manufacture method schematic diagram of first embodiment of plain conductor of the present invention.Please refer to Fig. 2 A, a substrate 20 at first is provided, and form a crystal seed layer 21 at substrate 20 upper surfaces.Wherein, substrate 20 comprises a glass substrate, and the material of crystal seed layer 21 can be copper (Cu), tantalum (Ta), titanium (Ti), chromium (Cr) or aluminium conducting metals such as (Al), in order to as the electrode in the follow-up electroplating work procedure.
Please refer to Fig. 2 B, after crystal seed layer 21 forms, form one first rete 22 in regular turn on crystal seed layer 21, and form one second rete 23 on first rete 22.Then, be masked in the position that defines a wire openings 24 on first rete 22 and second rete 23 with one, then above-mentioned two retes are carried out a dry ecthing operation, and form wire openings 24 on first rete 22 and second rete 23, and expose the upper surface of part crystal seed layer 21 by this wire openings 24, shown in Fig. 2 C.
Please refer to Fig. 2 D, after wire openings 24 forms, the opening sidewalls of first rete 22 is carried out etching, its sidewall is inwardly bounced back, and in 21 formation of second rete 23 and crystal seed layer, one side direction breach 24a.
Above-mentioned side direction breach 24a utilizes the operation of selective etch to reach.When the material of two retes not simultaneously, both etching selectivities also can be followed difference, in case when simultaneously first rete 22 and second rete 23 being carried out lateral etch (being generally wet etching), the amount of recovery of the sidewall of two retes will be different.In the present embodiment, the amount of recovery of the opening sidewalls of first rete 22 is greater than the amount of recovery of the opening sidewalls of second rete 23, and the amount of recovery of the opening sidewalls of first rete 22 comprises about 0.1 micron.
Yet, for the amount of recovery of the opening sidewalls that obtains first rete 22 result greater than the amount of recovery of the opening sidewalls of second rete 23.The material of above-mentioned first rete 22 and second rete 23 can comprise silicon nitride compound (SiN respectively
x) and silicon dioxide (SiO
2), and to carry out etching solution for etching be phosphoric acid (H
3PO
4).Perhaps, the material of above-mentioned first rete 22 and second rete 23 can comprise indium zinc oxide (IZO) and aluminium (Al) respectively, and to carry out etching solution for etching be oxalic acid.
Please refer to Fig. 2 E, form after the above-mentioned side direction breach 24a, then carry out an electroplating work procedure, to fill a metal material 25 in wire openings 24 and side direction breach 24a.In the present embodiment, be electrode with crystal seed layer 21, copper sulphate (CuSO
4) add sulfuric acid (H
2SO
4) solution is that electroplate liquid carries out above-mentioned electroplating work procedure, therefore, the material of formed metal material 25 comprises copper (Cu).
Above-mentioned metal material 25, in being formed at wire openings 24 and side direction breach 24a, also can be formed at more than second rete, 23 surfaces, but metal material 25 in wire openings 24 and the side direction breach 24a in fact only be arranged for necessary.Therefore, carry out electroplating work procedure after, can then carry out a cmp (CMP) operation, be formed at the above part metals materials 25 in second rete 23 surface with removal, as Fig. 2 F.At this moment, the metal material 25 that is formed in wire openings 24 and the side direction breach 24a is required metal level 251.
Please refer to Fig. 2 G, form after the metal level 251, can utilize the mode of dry ecthing to remove first rete 22 and second rete 23, and then remove the crystal seed layer 21 that is not covered by metal level 251.Wherein, the removal of above-mentioned crystal seed layer 21 is handled in the mode of wet etching, for example: when the material of crystal seed layer 21 is copper, can hydrochloric acid (HCl) be wet etching solution.
After removing the crystal seed layer 21 of above-mentioned two retes and part, the structure on the substrate 20 comprises metal level 251 and the crystal seed layer 21 between substrate 20 and metal level 251, and the two ends of metal level 251 are step structure.
Please continue the H with reference to Fig. 2, then the mode with sputter forms a metal barrier 26 in substrate 20 and metal level 251 surfaces, forms a gate insulator (GI layer) 27 at last again in metal barrier 26 surfaces.
Wherein, the material of metal barrier 26 is titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride compound (WN
x), tungsten silicon nitride compound (WSiN
x) or titanium silicon nitride (TiSiN).The material of gate insulator 27 is nitrogen silicon compound (SiN
x).
Therefore, in the present embodiment, metallic conducting wire structure of the present invention has comprised the crystal seed layer 21 that is formed on the substrate 20 and has been formed at metal level 251 on the crystal seed layer 21.Wherein, metal level 251 has big and little two blocks, and block of cells is positioned at big block top.In preferred embodiment, the two ends of metal level 251 are stair-stepping structure, and symmetrical each other.
In addition, plain conductor more comprises metal barrier 26 and gate insulator 27, and wherein metal barrier 26, is formed at the surface of metal level 251 and substrate 20.Gate insulator 27 is formed at the upper surface of metal barrier 26.
Second embodiment
Please refer to Fig. 3 A to Fig. 3 J, it is the manufacture method schematic diagram of second embodiment of plain conductor of the present invention.Please refer to Fig. 3 A, a substrate 30 at first is provided, and form one first rete 31 in regular turn on substrate 30, and form one second rete 32 on first rete 31.Wherein, substrate 30 comprises a glass substrate.
Then, be masked in the position that defines a wire openings 33 on first rete 31 and second rete 32 with one, then above-mentioned two retes carried out a dry ecthing operation, and form wire openings 33 on first rete 31 and second rete 32.And expose the upper surface of part substrate 30 by this wire openings 33, shown in Fig. 3 B.
Please refer to Fig. 3 C, after wire openings 33 forms, the opening sidewalls of first rete 31 is carried out etching, its sidewall is inwardly bounced back, and in 30 formation of second rete 32 and substrate, one side direction breach 33a.
Above-mentioned side direction breach 33a utilizes the operation of selective etch to reach.When the material of two retes not simultaneously, both etching selectivities also can be followed difference, in case when simultaneously first rete 31 and second rete 32 being carried out lateral etch (being generally wet etching), the amount of recovery of the sidewall of two retes will be different.In the present embodiment, the amount of recovery of the opening sidewalls of first rete 31 is greater than the amount of recovery of the opening sidewalls of second rete 32, and the amount of recovery of the opening sidewalls of first rete 31 comprises about 0.1 micron.
Yet, for the amount of recovery of the opening sidewalls of reaching first rete 31 result greater than the amount of recovery of the opening sidewalls of second rete 32.The material of above-mentioned first rete 31 and second rete 32 can comprise silicon nitride compound (SiN respectively
x) and silicon dioxide (SiO
2), and to carry out etching solution for etching be phosphoric acid (H
3PO
4).Perhaps, the material of above-mentioned first rete 31 and second rete 32 can comprise indium zinc oxide (IZO) and aluminium (Al) respectively, and carries out etching solution for etching and for example be oxalic acid.
Please refer to Fig. 3 D, form after the above-mentioned side direction breach 33a, then form a crystal seed layer 34 in via 33 exposed substrate 30 upper surfaces of wire openings, and second rete, 32 upper surfaces.In the present embodiment, crystal seed layer 21 can form by straight flow vacuum splashing and plating (DC-Sputter) operation, and its material can be conducting metals such as copper (Cu), tantalum (Ta), titanium (Ti), chromium (Cr) or aluminium (Al) .., in order to as the electrode in the follow-up electroplating work procedure.
Please refer to Fig. 3 E, form after the above-mentioned crystal seed layer 34, then carry out an electroplating work procedure, form a metal material 35, and be filled among wire openings 33 and the side direction breach 33a in crystal seed layer 34 upper surfaces.Wherein, the metal material 35 that is formed in wire openings 33 and the side direction breach 33a is required metal level 351.In the present embodiment, be electrode with crystal seed layer 34, CuSO
4Add H
2SO
4Solution is that electroplate liquid carries out above-mentioned electroplating work procedure, and therefore, the material of formed metal material 35 comprises copper (Cu).
Please refer to Fig. 3 F, form after the metal level 351, then carry out etching, removing second rete 32, and peel off (lift-off) simultaneously and be laminated in crystal seed layer 34 and metal material 35 on second rete 32 at second rete 32.At this moment, the structure on the substrate 30 is first rete 31, crystal seed layer 34 and metal level 351.Wherein metal level 351 is coated on the upper surface and the both side surface of crystal seed layer 34, and the two ends of metal level 351 are step structure.
Please refer to Fig. 3 G, remove after second rete 32, then first rete 31 is carried out etching, make metal level 351 two ends and 31 dialysis of first rete, and produce a gap 31a, and expose the substrate 30 of part.Wherein, above-mentioned etching work procedure carries out etching with wet etch solution to first rete 31.
Please continue H, then form a metal barrier 36 in metal level 351 surfaces, first rete, 31 surfaces, above-mentioned gap 31a and part substrate 30 upper surfaces in the mode of sputter with reference to Fig. 3.Wherein, the material of metal barrier 36 is titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride compound (WN
x), tungsten silicon nitride compound (WSiN
x) or titanium silicon nitride (TiSiN).
Since metal barrier 36 mainly act as the diffusion that prevents the copper metal, get final product so in fact only need be covered in metal level 351 upper surfaces.Therefore, please refer to Fig. 3 I, after above-mentioned metal barrier 36 forms, then can carry out wet etching, removing first rete 31, and peel off (lift-off) simultaneously and be laminated in metal barrier 36 on first rete 31 at first rete 31.At this moment, on substrate 30, be kind layer 34, metal level 351 and the metal barrier 36 that is coated on metal level 351 upper surfaces.
Please refer to Fig. 3 J, form a gate insulator (GI layer) 37 at last in metal barrier 36 and substrate 30 upper surfaces.Wherein, the material of gate insulator 37 is nitrogen silicon compound (SiN
x).Wherein, the removal of above-mentioned crystal seed layer 21 is handled in the mode of wet etching, for example: when the material of crystal seed layer 21 is copper, can HCl be wet etching solution.
After removing above-mentioned two retes and part crystal seed layer 21, the structure on the substrate 20 comprises metal level 251 and the crystal seed layer 21 between substrate 20 and metal level 251, and the two ends of metal level 251 are step structure.
Therefore, in the present embodiment, metallic conducting wire structure of the present invention has comprised the crystal seed layer 34 that is formed on the substrate 30 and has been formed at metal level 351 on the crystal seed layer 34.Wherein, metal level 351 is coated on the upper surface and the both side surface of crystal seed layer 34 comprehensively.
The metal level 251 of present embodiment has big and little two blocks, and block of cells is positioned at big block top.In preferred embodiment, the two ends of metal level 351 are stair-stepping structure, and symmetrical each other.
In addition, plain conductor more comprises metal barrier 36 and gate insulator 37, and wherein metal barrier 36 is formed at the surface of metal level 351, and gate insulator 37 is formed at the upper surface of metal barrier 36 and substrate 30.
In sum, metallic conducting wire structure of the present invention is a step structure, therefore, can improve the too steep problem of edge's gradient of plain conductor effectively, so have following advantage:
When one, reducing on the follow-up insulating layer deposition plain conductor, adhere to bad or the generation of the situation of broken hole, to produce preferable electrical effect.
Two, increase the enough and to spare of follow-up insulating barrier operation, promote the yield of subsequent handling.
Though the present invention as above describes with preferred embodiments, so it is not only to terminate in the foregoing description in order to limit the present invention's spirit with invention scope.To being familiar with those of ordinary skill in the art, when understanding and utilize other assembly or mode to produce identical effect easily.Therefore, the modification of being done in not breaking away from spirit of the present invention and scope all should be included in the scope of following claims.
Claims (37)
1. the manufacture method of a plain conductor comprises:
Form a crystal seed layer on a substrate;
Form one first rete on this crystal seed layer;
Form one second rete on this first rete;
Form a wire openings in this first with this second rete, and expose the part this crystal seed layer upper surface;
Opening sidewalls to this first rete carries out etching, and its sidewall is inwardly bounced back, and forms a side direction breach between this second rete and this crystal seed layer;
Carry out an electroplating work procedure, fill a metal material in this wire openings and this breach, and form a metal level;
Remove this first rete and this second rete, and peel off this metal level on this second rete; And
Remove this crystal seed layer that is not covered by this metal level.
2. the manufacture method of plain conductor according to claim 1 is characterized in that, this substrate comprises a glass substrate.
3. the manufacture method of plain conductor according to claim 1 is characterized in that, this wire openings of above-mentioned formation in this first with the step of this second rete, more comprise the following steps:
Be masked in this with one and first define the position of this wire openings with this second rete; And
Carry out a dry ecthing operation, to form this wire openings.
4. the manufacture method of plain conductor according to claim 1, it is characterized in that, above-mentioned sidewall to this first rete carries out the step that etching forms this side direction breach, it is a selective etch, simultaneously to this first with this second rete carry out lateral etch, wherein the amount of recovery of the opening sidewalls of this first rete is greater than the amount of recovery of the opening sidewalls of this second rete.
5. the manufacture method of plain conductor according to claim 4 is characterized in that, the amount of recovery of the opening sidewalls of this first rete comprises about 0.1 micron.
6. the manufacture method of plain conductor according to claim 4 is characterized in that, the material of above-mentioned this first rete and this second rete comprises silicon nitride compound (SiN respectively
x) and silicon dioxide (SiO
2), and to carry out etching solution for etching be phosphoric acid (H
3PO
4).
7. the manufacture method of plain conductor according to claim 4 is characterized in that, the material of above-mentioned this first rete and this second rete comprises indium zinc oxide (IZO) and aluminium (Al) respectively, and to carry out etching solution for etching be oxalic acid.
8. the manufacture method of plain conductor according to claim 1 is characterized in that, the material of this metal level comprises copper (Cu).
9. the manufacture method of plain conductor according to claim 8 is characterized in that, this electroplating work procedure comprises with copper sulphate (CuSO
4) add sulfuric acid (H
2SO
4) solution is electroplate liquid.
10. the manufacture method of plain conductor according to claim 1, it is characterized in that, after the above-mentioned step of carrying out this electroplating work procedure, more comprise a cmp operation, be formed at this this metal material of part more than second film surface in this electroplating work procedure to remove.
11. the manufacture method of plain conductor according to claim 1 is characterized in that, the step of this crystal seed layer that above-mentioned removal is not covered by this metal level comprises with wet etching and removes this above-mentioned crystal seed layer.
12. the manufacture method of plain conductor according to claim 1 is characterized in that, these metal level two ends are step structure.
13. the manufacture method of plain conductor according to claim 1 is characterized in that, after the step of this crystal seed layer that above-mentioned removal is not covered by this metal level, more comprises the following steps:
Form a metal barrier in this substrate and this layer on surface of metal; And
Form a gate insulator in this metal barrier laminar surface.
14. the manufacture method of plain conductor according to claim 13 is characterized in that, this metal barrier comprises with sputter and forming.
15. the manufacture method of a plain conductor comprises:
Form one first rete on a substrate;
Form one second rete on this first rete;
Form a wire openings in this first with this second rete, and expose the part this upper surface of base plate;
Opening sidewalls to this first rete carries out etching, and its sidewall is inwardly bounced back, and forms a side direction breach between this second rete and this substrate;
Form this upper surface of base plate and this second rete upper surface that a crystal seed layer exposes to the open air in this wire openings;
Carry out an electroplating work procedure, form a metal material in this crystal seed layer surface, and be filled in this opening and this breach, and form a metal level; And
Remove this second rete, and peel off this crystal seed layer and this metal material that is laminated on this second rete.
16. the manufacture method of plain conductor according to claim 15 is characterized in that, this substrate comprises a glass substrate.
17. the manufacture method of plain conductor according to claim 15 is characterized in that, this wire openings of above-mentioned formation in this first with the step of this second rete, more comprise the following steps:
Be masked in this with one and first define the position of this wire openings with this second rete; And
Carry out a dry ecthing operation, to form this wire openings.
18. the manufacture method of plain conductor according to claim 15, it is characterized in that, above-mentioned sidewall to this first rete carries out the step that etching forms this side direction breach, it is a selective etch, simultaneously to this first with this second rete carry out lateral etch, wherein the amount of recovery of the opening sidewalls of this first rete is greater than the amount of recovery of the opening sidewalls of this second rete.
19. the manufacture method of plain conductor according to claim 18 is characterized in that, the amount of recovery of the lateral openings sidewall of this first rete comprises about 0.1 micron.
20. the manufacture method of plain conductor according to claim 18 is characterized in that, the material of above-mentioned this first rete and this second rete comprises silicon nitride compound (SiN respectively
x) and silicon dioxide (SiO
2), and to carry out etching solution for etching be phosphoric acid (H
3PO
4).
21. the manufacture method of plain conductor according to claim 18 is characterized in that, the material of above-mentioned this first rete and this second rete comprises indium zinc oxide (IZO) and aluminium (Al) respectively, and to carry out etching solution for etching be oxalic acid.
22. the manufacture method of plain conductor according to claim 15 is characterized in that, this crystal seed layer comprises with the straight flow vacuum splashing and plating and forming.
23. the manufacture method of plain conductor according to claim 13 is characterized in that, the material of this metal level comprises copper (Cu).
24. the manufacture method of plain conductor according to claim 23 is characterized in that, this electroplating work procedure comprises with copper sulphate (CuSO
4) add sulfuric acid (H
2SO
4) solution is electroplate liquid.
25. the manufacture method of plain conductor according to claim 15 is characterized in that, these metal level two ends are step structure.
26. the manufacture method of plain conductor according to claim 15 is characterized in that, after the step of this second rete of above-mentioned removal, more comprises the following steps:
This first rete is carried out etching, make these metal level two ends and this first rete dialysis, and produce a gap, and expose this substrate of part;
Form a metal barrier in this layer on surface of metal, this first film surface, above-mentioned this gap with this substrate of part on; And
Remove this first rete, and peel off this metal barrier that is laminated on this first rete.
27. the manufacture method of plain conductor according to claim 26 is characterized in that, this metal barrier forms with sputter.
28. the manufacture method of plain conductor according to claim 26 is characterized in that, above-mentioned this first rete is carried out etched step after, more comprise forming a gate insulator in this metal barrier and this substrate surface.
29. a plain conductor comprises:
One crystal seed layer is formed on the substrate; And
One metal level is formed on this crystal seed layer, and these metal level two ends are step structure.
30. plain conductor according to claim 29 is characterized in that, the two ends of this metal level are symmetry each other.
31. plain conductor according to claim 29 is characterized in that, this plain conductor has more a metal barrier, is formed at this metal level and this substrate surface.
32. plain conductor according to claim 31 is characterized in that, this plain conductor has more a gate insulator, is formed at this metal barrier laminar surface.
33. plain conductor according to claim 29 is characterized in that, this metal level coats the upper surface and the both side surface of this crystal seed layer comprehensively.
34. plain conductor according to claim 29 is characterized in that, this plain conductor has more a metal barrier, is formed at this layer on surface of metal.
35. plain conductor according to claim 34 is characterized in that, this plain conductor has more a gate insulator, is formed at this metal barrier and this substrate surface.
36. plain conductor according to claim 29 is characterized in that, the material of this metal level comprises copper.
37. plain conductor according to claim 29 is characterized in that, this substrate comprises a glass substrate.
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|---|---|---|---|
| CNB2007100875323A CN100437915C (en) | 2007-03-16 | 2007-03-16 | Metal conducting wire and producing method thereof |
Applications Claiming Priority (1)
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|---|---|---|---|
| CNB2007100875323A CN100437915C (en) | 2007-03-16 | 2007-03-16 | Metal conducting wire and producing method thereof |
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|---|---|
| CN101022080A true CN101022080A (en) | 2007-08-22 |
| CN100437915C CN100437915C (en) | 2008-11-26 |
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| CNB2007100875323A Expired - Fee Related CN100437915C (en) | 2007-03-16 | 2007-03-16 | Metal conducting wire and producing method thereof |
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| WO2020082494A1 (en) * | 2018-10-26 | 2020-04-30 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method therefor as well as display module |
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Family Cites Families (5)
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| KR100400765B1 (en) * | 2000-11-13 | 2003-10-08 | 엘지.필립스 엘시디 주식회사 | Method for forming thin-film and liquid crystal display device fabricated by the same method |
| JP2004071942A (en) * | 2002-08-08 | 2004-03-04 | Denso Corp | Method for forming wire adopting electrolytic plating |
| JP2004304167A (en) * | 2003-03-20 | 2004-10-28 | Advanced Lcd Technologies Development Center Co Ltd | Wiring, display device and method for forming the same |
| US6887776B2 (en) * | 2003-04-11 | 2005-05-03 | Applied Materials, Inc. | Methods to form metal lines using selective electrochemical deposition |
| CN100338757C (en) * | 2005-12-21 | 2007-09-19 | 广辉电子股份有限公司 | Method for preparing copper conductor for plane display substrate |
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2007
- 2007-03-16 CN CNB2007100875323A patent/CN100437915C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102263060A (en) * | 2010-05-24 | 2011-11-30 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof as well as LCD (liquid crystal display) |
| CN102263060B (en) * | 2010-05-24 | 2014-09-24 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof as well as LCD (liquid crystal display) |
| CN103839887A (en) * | 2012-11-20 | 2014-06-04 | 三星显示有限公司 | Method of manufacturing thin film transistor array panel |
| CN103730190A (en) * | 2014-01-16 | 2014-04-16 | 广州新视界光电科技有限公司 | Composite copper electroconductive film, preparation method thereof and metal wiring circuit |
| CN105185787A (en) * | 2015-08-26 | 2015-12-23 | 深圳市华星光电技术有限公司 | Method for manufacturing array substrate, array substrate and liquid crystal display panel |
| WO2020082494A1 (en) * | 2018-10-26 | 2020-04-30 | 深圳市华星光电半导体显示技术有限公司 | Display panel and manufacturing method therefor as well as display module |
| CN113009733A (en) * | 2019-12-20 | 2021-06-22 | 京东方科技集团股份有限公司 | Pixel structure, preparation method thereof and display device |
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