CN112635495B - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN112635495B CN112635495B CN202110010849.7A CN202110010849A CN112635495B CN 112635495 B CN112635495 B CN 112635495B CN 202110010849 A CN202110010849 A CN 202110010849A CN 112635495 B CN112635495 B CN 112635495B
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- 239000000758 substrate Substances 0.000 title claims abstract description 71
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 230000000149 penetrating effect Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 27
- 239000003990 capacitor Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 238000003860 storage Methods 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910001887 tin oxide Inorganic materials 0.000 claims description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- JRBRVDCKNXZZGH-UHFFFAOYSA-N alumane;copper Chemical compound [AlH3].[Cu] JRBRVDCKNXZZGH-UHFFFAOYSA-N 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 239000000956 alloy Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000010936 titanium Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910010272 inorganic material Inorganic materials 0.000 description 3
- 239000011147 inorganic material Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- -1 or the like Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The invention discloses an array substrate, a preparation method thereof and a display device, wherein the array substrate comprises: a substrate; the buffer structure layer is arranged on the substrate; the active layer is arranged on the buffer structure layer; a first insulating layer disposed on the substrate and covering the active layer; a first insulating layer opening penetrating the first insulating layer and corresponding to the active layer; the grid electrode is arranged on the first insulating layer and corresponds to the active layer; and the source drain electrode is arranged on the first insulating layer, arranged on the side of the grid electrode and penetrates through the opening of the first insulating layer to be connected with the active layer.
Description
Technical Field
The application relates to the field of panels, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
With the development of display technology and the increase of differentiated demands, the market puts more demands on panel performance. Compared with the existing display driving TFT technology, the High-mu TFT has obvious advantages in device performance and is expected to be applied to the future High-end display industry. Through the development of a High-mu target and a new technology, the electrical property of a TFT device and the display property of a product can be improved, a positive effect is played in the aspects of new technology patent layout and the like, technical reserve is enriched and perfected, and company competitiveness is improved.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides an array substrate, a method for manufacturing the same, and a display device, so as to solve the technical problem in the prior art that additional steps are required to make an active layer and a storage capacitor electrode conductive.
The technical scheme for solving the technical problems is as follows: the invention provides an array substrate, comprising: a substrate; the buffer structure layer is arranged on the substrate; the active layer is arranged on the buffer structure layer; a first insulating layer disposed on the substrate and covering the active layer; a first insulating layer opening penetrating the first insulating layer and corresponding to the active layer; the grid electrode is arranged on the first insulating layer and corresponds to the active layer; and the source drain electrode is arranged on the first insulating layer, arranged on the side of the grid electrode and penetrates through the opening of the first insulating layer to be connected with the active layer.
Further, the active layer is made of indium gallium tin oxide.
The invention also discloses a preparation method of the array substrate, which comprises the following steps:
providing a substrate; preparing a buffer structure layer on the substrate; depositing a semiconductor material on the buffer structure layer to form a semiconductor layer; patterning the semiconductor layer to obtain an active layer; preparing a first insulating layer on the active layer, the first insulating layer covering the active layer; forming a hole in the first insulating layer to obtain a first insulating layer hole, wherein the active layer is partially exposed in the first hole; and preparing a grid electrode and a source drain electrode on the first insulating layer, wherein the grid electrode is arranged in the middle of the first insulating layer, the source drain electrode is arranged at the edge of the first insulating layer, and the source drain electrode is connected to the active layer through an opening of the first insulating layer.
Further, the preparation of the buffer structure layer specifically comprises the following steps:
preparing a metal layer on the substrate, and patterning the metal layer through a yellow light process to obtain at least one shading metal unit; and depositing a buffer layer on the substrate, wherein the buffer layer covers the metal unit.
Further, after the step of preparing the gate electrode and the source and drain electrodes, the method further comprises the following steps:
preparing a second insulating layer on the buffer structure layer, wherein the second insulating layer covers the grid layer and the source drain electrode; preparing a flat layer on the second insulating layer, and etching pixel openings on the flat layer, wherein the pixel openings correspond to the source and drain electrodes; and preparing a pixel electrode on the flat part, wherein the pixel electrode penetrates through the pixel opening and is connected to the source drain electrode.
Further, the specific preparation steps of the active layer comprise: preparing a layer of semiconductor material on the buffer structure layer to obtain a semiconductor layer, and processing the semiconductor layer by using an annealing process, wherein the temperature of the annealing process is 200-400 ℃, and the time is 0.5-4 hours; and patterning the semiconductor layer by utilizing a yellow light process and an etching process to obtain the active layer.
Further, the metal unit includes a light-shielding metal unit and a storage capacitor electrode, and the storage capacitor electrode is disposed on the substrate or on the light-shielding metal unit.
Further, the material of the light-shielding metal unit is molybdenum or aluminum, and the material of the storage capacitor electrode includes an ITO material.
Further, in the step of preparing the gate electrode and the source/drain electrode on the first insulating layer, the gate electrode and the source/drain electrode are prepared from copper-aluminum alloy as a raw material.
The invention also discloses a display device comprising the array substrate.
The array substrate, the preparation method thereof and the display device have the advantages that the grid electrode and the source drain electrode in the array substrate are arranged on the same insulating layer, the grid electrode and the source drain electrode can be simultaneously prepared, the thickness of the array substrate is reduced, and the source drain electrode is connected to the active layer through the opening of the insulating layer on the insulating layer. The material selection of the grid electrode and the source and drain electrodes and the material of the active layer have high etching selection ratio, so that when the grid electrode and the source and drain electrodes are prepared, the corrosion of the source and drain electrodes and the grid electrode on the active layer in the etching process is not required to be considered, and meanwhile, in the process of depositing the source and drain electrodes and the grid electrode, the energy generated by the energy can make the exposed active layer become a conductor, so that the preparation flow is saved. And the exposed active layer can be treated by gas plasma and made into a conductor when the source electrode, the drain electrode and the grid electrode are deposited.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic view of a buffer structure layer in an embodiment.
Fig. 2 is a schematic view of an active layer and a second storage capacitor electrode in the embodiment.
Fig. 3 is a schematic diagram of a first via structure in the embodiment.
Fig. 4 is a schematic diagram of a first insulating layer structure in an embodiment.
Fig. 5 is a schematic diagram of an opening structure of a first insulating layer in an embodiment.
Fig. 6 is a schematic structural diagram of a gate electrode and a source drain electrode in the embodiment.
Fig. 7 is a schematic structural view of a second insulating layer in the embodiment.
Fig. 8 is a schematic diagram of a pixel electrode structure in the embodiment.
Fig. 9 is a flowchart of preparing an array substrate in the example.
FIG. 10 is a flow chart of the preparation of the buffer structure layer in the example.
The numbers in the figures are as follows:
an array substrate 100; a substrate 110;
a buffer structure layer 120; an active layer 130;
a first insulating layer 140; a gate electrode 150;
source-drain electrodes 160; a second insulating layer 170;
a planarization layer 180; the pixel electrode 190;
a light shielding unit 121; a first storage capacitor electrode 122;
a buffer layer 123; a first through hole 1231;
a second storage capacitor electrode 125; the first insulating layer opening 141;
a first conductive layer 124; a pixel opening 181.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Examples
In this embodiment, the display device of the present invention includes an array substrate, where the array substrate includes a substrate 110, a buffer structure layer 120, an active layer 130, a first insulating layer 140, a gate 150, a source/drain electrode 160, a second insulating layer 170, a planarization layer 180, and a pixel electrode 190.
The substrate 110 is a hard substrate, generally a glass substrate, and plays a role of a support and a substrate.
As shown in fig. 1, fig. 1 is a schematic view of a buffer structure layer in an embodiment. The buffer structure layer 120 is disposed on a side surface of the substrate 110, and specifically, the buffer structure layer 120 includes a light shielding unit 121, a first storage capacitor electrode 122, and a buffer layer 123.
The light shielding unit 121 is a light shielding metal material, and is disposed on one side surface of the substrate 110 at an interval, the light shielding unit is made of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, or an alloy, and the thickness of the light shielding unit 121 is 2000 to 5500 angstroms. The light shielding unit 121 plays a light shielding role.
The first storage capacitor electrodes 122 are distributed on a surface of one side of the substrate 110 or on a surface of the light-shielding metal unit 121 at intervals, and the first storage capacitor electrodes 122 are made of ITO material and can store a capacitor after being conductive.
The buffer layer 123 is disposed on the light-shielding unit 121, the first storage capacitor electrode 122, and the upper surface of the substrate 110, and plays a role of buffering, the buffer layer 123 is made of an inorganic material, the inorganic material is SiOx (silicon oxide) or a composite layer of SiNx (silicon nitride) and SiOx (silicon oxide), and the buffer layer 123 has a thickness of 1500 to 4000 angstroms.
As shown in fig. 2, fig. 2 is a schematic view of an active layer and a second storage capacitor electrode in the embodiment. The active layer 130 is disposed on a surface of the buffer structure layer 120, which is far away from the substrate 110, the active layer 130 is made of a semiconductor material, the semiconductor material is Indium Gallium Tin Oxide (IGTO), and the thickness of the active layer 130 is 100 to 1000 angstroms. The active layer 130 is disposed above the light shielding unit 121, that is, the active layer 130 is disposed opposite to the light shielding layer 121, so as to prevent light from the substrate 110 from directly irradiating the active layer 130, thereby reducing the lifetime of the active layer 130. The active layer 130 provides circuit support to the display panel.
A second storage capacitor electrode 125 is disposed above the semiconductor material corresponding to the first storage capacitor electrode 122, and the second storage capacitor electrode 125 and the active layer 130 are disposed at the same layer.
As shown in fig. 3, fig. 3 is a schematic diagram of a first via structure in the embodiment. The buffer layer 123 is further provided with at least one first via 1231, the first via 1231 corresponds to a first storage capacitor electrode 122, and the first via 1231 is not overlapped with the active layer 130.
As shown in fig. 4, fig. 4 is a schematic diagram of a first insulating layer structure in an embodiment. The first insulating layer 140 is disposed on the active layer 130 and the upper surface of the substrate 110 around the active layer 130, i.e., the first insulating layer 140 completely covers the active layer 130. The first insulating layer 140 is made of an inorganic material including SiOx (silicon oxide) or a composite layer of SiNx (silicon nitride) and SiOx (silicon oxide), and the thickness of the first insulating layer 140 is 1500 to 4000 angstroms. The first insulating layer 140 serves as an insulator to prevent short circuits between the lines inside the display panel.
As shown in fig. 5, fig. 5 is a schematic view of an opening structure of a first insulating layer in an embodiment. At least two first insulating layer openings 141 are formed in the first insulating layer 140, and the first insulating layer openings 141 penetrate the first insulating layer 140 and have bottoms falling on the upper surface of the active layer 130.
As shown in fig. 6, fig. 6 is a schematic structural diagram of a gate electrode and a source/drain electrode in an embodiment. The gate electrode 150 is disposed on the first insulating layer 140, specifically, the gate electrode 150 is disposed on the first insulating layer 140 between the two first insulating layer openings 141, that is, the gate electrode 150 is completely insulated from the active layer 130, the gate electrode 150 is made of a metal material, the metal material is a Cu — Al alloy material, in this embodiment, the material used for the gate electrode 150 is preferably a material having a high etching selectivity ratio with respect to IGTO, and in other preferred embodiments of the present invention, the material used for the gate electrode 150 includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., or an alloy, or a multilayer thin film structure. The thickness of the gate 150 is 1500-4000 angstroms.
The source/drain electrode 160 and the gate 150 are disposed on the same layer, specifically, the source/drain electrode 160 is disposed on the upper surface of the first insulating layer 140, and is disposed on one side of the first insulating layer opening 141 away from the gate 150, that is, at the edge of the first insulating layer 140, the source/drain electrode 160 is connected to the active layer 130 through the first insulating layer opening 141, and in order to avoid the connection between the source/drain electrode 160 and the gate 150, a gap is formed between the inner sidewall of the first insulating layer opening 141 close to the gate 150 and the source/drain electrode 160.
In this embodiment, the source-drain electrodes 160 and the gate 150 are disposed on the same layer, so that the thickness of the array substrate 100 is reduced, which is beneficial to realizing ultra-thinning of the display device.
Specifically, the buffer layer 123 is provided with a first conductive layer 124, and the first conductive layer 124 penetrates through the first via 1231 and is connected to the first storage capacitor electrode 122 corresponding to the first via 1231. The material and thickness of the first conductive layer 124 are the same as those of the gate 150.
As shown in fig. 7, fig. 7 is a schematic structural view of a second insulating layer in the embodiment. The second insulating layer 170 is disposed on the gate 150, the source/drain electrode 160, the first conductive layer 124 and the buffer structure layer 120, and the second insulating layer 170 is further filled in the first insulating layer opening 141 to prevent the source/drain electrode 160 and the gate 150 from being conducted.
The flat layer 180 is disposed on a side surface of the second insulating layer 170 away from the buffer structure layer 120, the flat layer 180 is made of an insulating material, and the flat layer 180 enables the surface of the film layer to be flat, so that the subsequent preparation of the pixel electrode is facilitated, and the film layer is prevented from being separated.
A pixel opening 181 is disposed on the planarization layer 180, the pixel opening 181 corresponds to the source/drain electrode 160, and the pixel opening 181 provides a channel for the subsequent pixel electrode 190.
As shown in fig. 8, fig. 8 is a schematic diagram of a pixel electrode structure in an embodiment. The pixel electrode 190 is disposed on a side surface of the planarization layer 180 away from the second insulating layer 170, the pixel electrode 190 is made of ito, and the pixel electrode 190 fills the pixel opening 181 and is electrically connected to the source/drain electrode 160 to provide a circuit support for the subsequent light emission of the light emitting material.
In order to better explain the present invention, in this embodiment, a method for manufacturing the array substrate is further provided, as shown in fig. 9, including steps S1) to S11):
s1) providing a substrate, wherein the substrate is a hard glass substrate.
S2) preparing a buffer structure layer on the substrate.
And S3) preparing a layer of semiconductor material on the buffer structure layer to obtain a semiconductor layer, and repairing the defects of the semiconductor layer by using an annealing process, wherein the temperature of the annealing process is 200-400 ℃ and the time is 0.5-4 hours.
And S4) patterning the semiconductor layer by utilizing a yellow light process and an etching process to obtain the active layer and the second storage capacitor electrode.
S5) opening the buffer structure layer through a yellow light process, preferably performing Dry Etch (Dry etching) on the etching process, and preferably selecting CF as an etching gas 4 (tetrafluoromethane) and O 2 (oxygen) mixed gas.
S6) preparing a first insulating layer on the active layer through plasma enhanced chemical vapor deposition, wherein the material of the first insulating layer is SiOx (silicon oxide) or a composite layer of SiNx (silicon nitride) and SiOx (silicon oxide), the thickness of the deposited first insulating layer is 1500-4000 angstroms, and the first insulating layer covers the active layer.
S7) opening the first insulating layer through a yellow light process and an etching process to obtain the opening of the first insulating layer, wherein the etching process is preferably carried out by Dry Etch (Dry etching), and the etching gas is preferably CF 4 (tetrafluoromethane) and O 2 The active layer is partially exposed in the first opening.
S8) respectively depositing a grid electrode and a source drain electrode on the first insulating layer, wherein the grid electrode is arranged in the middle of the first insulating layer, the source drain electrode is arranged at the edge of the first insulating layer, the source drain electrode is connected to the active layer through the opening of the first insulating layer, the grid electrode and the source drain electrode are made of a copper-aluminum alloy material, in other preferable embodiments of the invention, the alloy material is preferably an etching high-selectivity material with Indium Gallium Tin Oxide (IGTO), crystal bloom is performed on the indium gallium tin oxide material through PVD deposition process energy, so that the active layer and the second storage capacitor electrode exposed from the opening of the first insulating layer are made conductive, and Al (aluminum) is doped, and the low-resistance characteristic of the IGTO is ensured.
And S9) preparing a second insulating layer on the buffer structure layer, wherein the second insulating layer covers the grid layer and the source and drain electrodes.
S10) preparing a flat layer on the second insulating layer, and etching pixel openings on the flat layer, wherein the pixel openings correspond to the source and drain electrodes.
S11) preparing a pixel electrode on the flat surface, wherein the pixel electrode penetrates through the pixel opening and is connected to the source drain electrode.
As shown in fig. 10, the step S2) of preparing the buffer structure layer specifically includes the following steps:
s201) preparing a metal layer on the substrate, patterning the metal layer through a yellow light process to obtain at least one shading metal unit, wherein the metal unit comprises a shading metal unit and a storage capacitor electrode, and the storage capacitor electrode is arranged on the substrate or the shading metal unit.
S202) depositing a buffer layer on the substrate, wherein the buffer layer covers the metal unit.
The array substrate, the manufacturing method thereof and the display device have the advantages that the gate electrode and the source drain electrode in the array substrate are arranged on the same insulating layer, the gate electrode and the source drain electrode can be simultaneously manufactured, the thickness of the array substrate is reduced, and the source drain electrode is connected to the active layer through the insulating layer opening in the insulating layer. The material selection of the grid electrode and the source and drain electrodes and the material of the active layer have high etching selection ratio, so that when the grid electrode and the source and drain electrodes are prepared, the corrosion of the source and drain electrodes and the grid electrode on the active layer in the etching process is not required to be considered, and meanwhile, in the process of depositing the source and drain electrodes and the grid electrode, the energy generated by the energy can make the exposed active layer become a conductor, so that the preparation flow is saved. The exposed active layer may also be treated with a gas plasma and rendered conductive during deposition of the source and drain electrodes and gate electrodes.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate;
the buffer structure layer is arranged on the substrate;
the active layer is arranged on the buffer structure layer;
a first insulating layer disposed on the substrate and covering the active layer;
a first insulating layer opening penetrating the first insulating layer and corresponding to the active layer;
the grid electrode is arranged on the first insulating layer and corresponds to the active layer; and
the source drain electrode is arranged on the first insulating layer, arranged at the side of the grid electrode and connected with the active layer by penetrating through the opening of the first insulating layer;
a gap is formed between the inner side wall of the first insulating layer opening close to the grid electrode and the source drain electrode.
2. The array substrate of claim 1,
the active layer is made of indium gallium tin oxide.
3. The preparation method of the array substrate is characterized by comprising the following steps:
providing a substrate;
preparing a buffer structure layer on the substrate;
depositing a semiconductor material on the buffer structure layer to form a semiconductor layer;
patterning the semiconductor layer to obtain an active layer;
preparing a first insulating layer on the active layer, the first insulating layer covering the active layer;
forming a hole in the first insulating layer to obtain a first insulating layer hole, wherein the active layer is partially exposed in the first insulating layer hole; and
preparing a grid electrode and a source drain electrode on the first insulating layer, wherein the grid electrode is arranged in the middle of the first insulating layer, the source drain electrode is arranged at the edge of the first insulating layer, and the source drain electrode is connected to the active layer through an opening of the first insulating layer; a gap is formed between the inner side wall of the first insulating layer opening close to the grid electrode and the source drain electrode.
4. The method of claim 3, wherein the step of forming the array substrate comprises the steps of,
the preparation of the buffer structure layer specifically comprises the following steps:
preparing a metal layer on the substrate, and patterning the metal layer through a yellow light process to obtain at least one metal unit; and
and depositing a buffer layer on the substrate, wherein the buffer layer covers the metal unit.
5. The method for preparing the array substrate according to claim 3, further comprising the following steps after the steps of preparing the gate electrode and the source drain electrode:
preparing a second insulating layer on the buffer structure layer, wherein the second insulating layer covers the grid layer and the source drain electrode;
preparing a flat layer on the second insulating layer, and etching pixel openings on the flat layer, wherein the pixel openings correspond to the source and drain electrodes; and
and preparing a pixel electrode on the flat layer, wherein the pixel electrode penetrates through the pixel opening and is connected to the source and drain electrodes.
6. The method of claim 3, wherein the step of forming the array substrate comprises the steps of,
the active layer is prepared by the following specific steps:
preparing a layer of semiconductor material on the buffer structure layer to obtain a semiconductor layer, and processing the semiconductor layer by using an annealing process, wherein the temperature of the annealing process is 200-400 ℃, and the time is 0.5-4 hours; and
and patterning the semiconductor layer by utilizing a yellow light process and an etching process to obtain the active layer.
7. The method of manufacturing an array substrate according to claim 4,
the metal unit comprises a shading metal unit and a storage capacitor electrode, and the storage capacitor electrode is arranged on the substrate or the shading metal unit.
8. The method of manufacturing an array substrate according to claim 7,
the material of the shading metal unit is molybdenum or aluminum, and the material of the storage capacitor electrode comprises an ITO material.
9. The method of claim 3, wherein the step of forming the array substrate comprises the steps of,
in the step of preparing the grid electrode and the source and drain electrodes on the first insulating layer, the raw materials for preparing the grid electrode and the source and drain electrodes are copper-aluminum alloy.
10. A display device comprising the array substrate according to claim 1 or 2.
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| WO2020062483A1 (en) * | 2018-09-30 | 2020-04-02 | 武汉华星光电技术有限公司 | Thin film transistor array substrate, fabrication method therefor and display panel |
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| WO2020062483A1 (en) * | 2018-09-30 | 2020-04-02 | 武汉华星光电技术有限公司 | Thin film transistor array substrate, fabrication method therefor and display panel |
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