CN1251323C - Method of improving surface flatness of embedded interlayer metal dielectric layer - Google Patents
Method of improving surface flatness of embedded interlayer metal dielectric layer Download PDFInfo
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- CN1251323C CN1251323C CN 02103600 CN02103600A CN1251323C CN 1251323 C CN1251323 C CN 1251323C CN 02103600 CN02103600 CN 02103600 CN 02103600 A CN02103600 A CN 02103600A CN 1251323 C CN1251323 C CN 1251323C
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Abstract
The present invention relates to a method for improving the surface flatness of a double-embedded interlayer metallic dielectric layer, which is suitable for a semiconductor substrate. The surface of the substrate is provided with a metallic circuit. The method comprises: orderly depositing a metallic sealing layer, an interlayer metallic dielectric layer, a protective sacrificial layer and a hard cover curtain layer on the metallic circuit; defining and removing the hard cover curtain layer and the protective sacrificial layer and forming a first opening on the interlayer metallic dielectric layer; defining and removing the interlayer metallic dielectric layer and forming a second opening in the interlayer metallic dielectric layer without exposing to the metallic circuit. The second opening is positioned in the first opening and aligns to the metallic circuit. The hard cover curtain layer and parts of the interlayer metallic dielectric layer are removed; meanwhile, a conducting wire groove and a contact through hole are formed, and the bottom of the contact through hole is exposed to the metallic circuit. The interlayer metallic dielectric layer forms a staircase-shaped (or T-shaped) section outline. The protective sacrificial layer is removed to expose the surface of the interlayer metallic dielectric layer. Metallic blocking layers are respectively formed on the interlayer metallic dielectric layer, the conducting wire groove and the contact through hole. Metal is filled in the conducting wire groove and the contact through hole to be jointed with the metallic circuit.
Description
Technical field
The invention relates to a kind of method of improving surface flatness of embedded interlayer metal dielectric layer, particularly relevant for a kind of protection sacrifice layer of solvable organic solvent, when dry ecthing definition lead groove, the method on interlayer metal dielectric layer surface is sacrificed in protection.
Background technology
Embed (damascene) speech, derived from Damascus (Damascus) craftsman's in ancient times embedding lithography, so also be called Damascus technique.The multiple layer metal line (multlevelInterconnection) of traditional integrated circuit is to make plain conductor in metal level dry ecthing mode, carries out the filling (dielectric gap fill) of dielectric layer then.Embedded technology then is the circuit pattern film that the etching metal lead is used on dielectric layer earlier, and then fills metal in the circuit pattern groove.The topmost characteristics of embedded technology are the etchings that do not need to carry out metal level.When the material of plain conductor converts the lower copper of resistivity to by aluminium, because the dry ecthing of copper difficulty comparatively, so embedded technology is just very important concerning copper wiring.
Common two kinds of known embedded structure: single embedded structure and two embedded structure (dual damascene).Single embedded structure only is that the production method of single-layer metal lead is changed into embedded mode (dielectric layer etch+metal filled) by traditional (metal level etching+dielectric layers fills) mode as previously mentioned, and is comparatively simple.Two embedded structures then are through hole (via) and plain conductor groove (trench) to be combined all use the mode that embeds to do.So only need one metal filled step, can simplify fabrication steps, but the control of known pair of embedding process conditions is also comparatively complicated and difficult.
Consult shown in Figure 1A, known two processing procedures that embed are at first on substrate 10 surfaces with metallic circuit (metal wiring) 11, and plated metal sealant 12, interlayer metal dielectric layer 13 and hard cover curtain layer 15 are on metallic circuit 11 in regular turn.Afterwards, use little shadow and dry-etching processing procedure, hard cover curtain layer (hardmask) 15 is carried out the dry-etching definition, form first opening 16 on interlayer metal dielectric layer 13, wherein first opening, 16 width are defined as the predetermined plain conductor groove width that forms.
See also Figure 1B, secondly, use little shadow and etch process, interlayer metal dielectric layer 13 is carried out the dry ecthing definition, form second opening 18 in interlayer metal dielectric layer 13, and aim at metallic circuit 11.Wherein, second opening 18 is positioned at first opening 16, second opening, 18 degree of depth and width are defined as predetermined formation plain conductor gash depth and Metal Contact through hole (contact via) width respectively, and the etch depth of second opening 18 is to control with the dry ecthing time.
See also Fig. 1 C, with hard cover curtain layer 15 is dry ecthing cover curtain, interlayer metal dielectric layer 13 and metallic seal layer 12 are carried out the dry ecthing definition, form plain conductor groove 17 and Metal Contact through hole 19 simultaneously, and make Metal Contact through hole 19 bottoms be exposed to metallic circuit 11.
Wherein, reactive ion electricity slurry can be removed hard cover curtain layer 15 fully in dry etch process, and can corrode the K dielectrics 13 below the matter cover curtain layer 15 slightly, causes interlayer metal dielectric layer 13 surface irregularities.Therefore, cause subsequently plated metal barrier layer (tantalum/tantalum nitride for example, Ta/TaN) 20 when interlayer metal dielectric layer 13 surfaces and groove, form discontinuous metal barrier layer 14, and cause in follow-up metal (for example copper) the electrochemical deposition processing procedure, with discontinuous metal barrier layer 20 is electroplated electrode, and metal can't be filled in interlayer metal dielectric layer 13 grooves (shown in Fig. 1 D).
Summary of the invention
In view of this, main purpose of the present invention just provides a kind of method of improving surface flatness of embedded interlayer metal dielectric layer, forms continuous metal barrier layer and is covered in fully in the interlayer metal dielectric layer groove.
The method of improving surface flatness of embedded interlayer metal dielectric layer of the present invention, be applicable to the semiconductor substrate, above-mentioned substrate surface has the plain conductor road, comprising: deposit a metallic seal floor one interlayer metal dielectric layer, a protection sacrifice layer and a hard cover curtain layer in regular turn on above-mentioned plain conductor road; Above-mentioned hard cover curtain layer is removed in definition and above-mentioned protection sacrifice layer formation first is opened on the above-mentioned interlayer metal dielectric layer; Above-mentioned interlayer metal dielectric layer is removed in definition, forms second and is opened on above-mentioned interlayer metal dielectric layer inside and does not expose above-mentioned plain conductor road, and wherein above-mentioned second opening is to be positioned at above-mentioned first opening and to aim at above-mentioned plain conductor road; Remove above-mentioned hard cover curtain layer and the above-mentioned interlayer metal dielectric layer of part, form lead groove and contact through hole simultaneously, make above-mentioned contact through hole bottom be exposed to metallic circuit, and above-mentioned interlayer metal dielectric layer constitutes notch cuttype (or T type) section profile; Remove above-mentioned protection sacrifice layer, expose above-mentioned interlayer metal dielectric layer surface; Form a metal barrier layer on above-mentioned interlayer metal dielectric layer, above-mentioned lead groove and above-mentioned contact through hole; And fill metal in above-mentioned lead groove and above-mentioned contact through hole, and engage with above-mentioned metallic circuit.
Wherein, when etching is removed above-mentioned hard cover curtain layer and is formed above-mentioned lead groove and above-mentioned contact through hole simultaneously; can slightly corrode the lower floor of above-mentioned hard cover curtain layer; because of above-mentioned protection sacrifice layer is positioned at below the above-mentioned hard cover curtain layer; so can prevent that above-mentioned interlayer metal dielectric layer surface from suffering erosion; and make the above-mentioned interlayer metal dielectric layer surface can be not uneven, help the continuous metal barrier layer of subsequent deposition one, to be covered in the above-mentioned interlayer metal dielectric layer groove.
Protection sacrifice layer material of the present invention can be organic antireflecting thing (ARC, photolithography in semiconductor manufacturing common used material), organic low dielectric constant material (for example SILK, FLARE, pi etc.) or dissolves in the polymer or the oligomerization compound (oligomer) of organic solvent (for example cyclohexane, acetone, different propane).
Therefore, form, have the following advantages according to method and the protection sacrifice layer material of the present invention of improving interlayer metal dielectric layer surface flatness degree in the two embedded processing procedures of metal of the present invention:
Prevent that interlayer metal electricity laminar surface is uneven, and help the continuous metal barrier layer of subsequent deposition in the interlayer metal dielectric layer surface; Protection sacrifice layer of the present invention can with an organic solvent dissolve removal and not damage the interlayer metal dielectric layer surface, and the processing procedure cost is low; Protection sacrifice layer of the present invention can be promoted interlayer metal dielectric layer and hard cover curtain layer adhesion strength.
Description of drawings
Figure 1A-1D is depicted as the two manufacturing method thereofs that embed of known metal;
Fig. 2-7 is depicted as the two manufacturing method thereofs that embed of metal of embodiments of the invention.
The figure number explanation
10 1 substrates; 11 1 plain conductor roads; 12 1 metallic seal layers:
13 1 interlayer metal dielectric layers; 14 1 protection sacrifice layers; 15 1 hard cover curtain layers;
16 one the first openings; 17 1 lead grooves; 18 one the second openings;
19 1 contact through holes; 20 1 metal barrier layers; 21 1 plain conductors;
22 1 contacting metals
Specific embodiment
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
See also Fig. 2, a substrate 10 at first is provided, it is the semiconductor material, comprises plain conductor road (metal wiring) 11 on substrate 10 surfaces.Afterwards, deposit a metallic seal floor 12, an interlayer metal dielectric layer 13, a protection sacrifice layer 14 and a hard cover curtain layer 15 in regular turn on plain conductor road 11.
Wherein, interlayer metal dielectric layer 13 can be the organic low dielectric constant material (for example SilK, FLARE, pi etc.) that thickness is about 6,000 dusts; Protection sacrifice layer 14 can be organic antireflecting thing (ARC, photolithography in semiconductor manufacturing common used material), organic low dielectric constant material (for example SiLK, pi etc.) or dissolves in the polymer or the oligomerization compound (oligomer) of organic solvent (for example cyclohexane, acetone, different propane); Hard cover curtain layer 15 can be carborundum (SiC), silicon nitride (SiN) or spin-on glasses (SOG); The metallic seal layer can be the silicon nitride (SiN) that thickness is about 300 dusts.
See also Fig. 3; use little shadow and dry-etching processing procedure, hard cover curtain layer 15 and protection sacrifice layer 14 are carried out the dry ecthing definition, form first opening 16; first opening 16 is on interlayer metal dielectric layer 13, and wherein the definition of first opening, 16 width is scheduled to form the plain conductor groove width.
See also Fig. 4, secondly, use little shadow and etch process, interlayer metal dielectric layer 13 is carried out the dry-etching definition, form second opening 18 in interlayer metal dielectric layer 13, the second opening degree of depth is about 2,500 dusts, and aims at metallic circuit 11.Wherein second opening, 18 degree of depth and width define predetermined formation plain conductor gash depth and Metal Contact through hole (contact via) width respectively, and the etch depth of second opening 18 is to control with etching period.
See also Fig. 5, with hard cover curtain layer 15 is etch mask, interlayer metal dielectric layer 13, metallic seal layer 12 are carried out dry ecthing, form the degree of depth simultaneously and be about 2, the plain conductor groove 17 and the degree of depth of 500 dusts are about 3, the Metal Contact through hole of 500 dusts (kontact via) 19, and make Metal Contact through hole 19 bottoms expose plain conductor road 11.Wherein, in dry etch process; reactive ion electricity slurry can be removed hard cover curtain layer 15 fully; and can slightly corrode protection sacrifice layer 14 surfaces; because of protection sacrifice layer 14 is still stayed on the interlayer metal dielectric layer 13; so interlayer metal dielectric layer 13 surfaces can be not uneven, and help the continuous metal barrier layer of subsequent deposition in interlayer metal dielectric layer 13 surfaces.
Please join Fig. 6, remove protection sacrifice layer 14, expose interlayer metal dielectric layer 13 surfaces with organic solvent (for example cyclohexane, acetone, different propane).(for example tantalum/tantalum nitride Ta/TaN) is covered in interlayer metal dielectric layer 13, plain conductor groove 17 and Metal Contact through hole 19 surfaces to deposit a metal barrier layer 20 then.
Seeing also Fig. 7, use the electrochemical deposition mode, is electroplated electrode with metal barrier layer 20, and metal (for example copper) complete filling in plain conductor groove 17 and Metal Contact through hole 19, is formed plain conductor 21 and contacting metal 22, is connected on the metallic circuit 11.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking the claim scope person of defining.
Claims (8)
1. a method of improving surface flatness of embedded interlayer metal dielectric layer is applicable to the semiconductor substrate, and above-mentioned substrate surface has the plain conductor road, comprising:
Deposit a metallic seal floor, an interlayer metal dielectric layer, a protection sacrifice layer and a hard cover curtain layer in regular turn on above-mentioned plain conductor road;
Above-mentioned hard cover curtain layer and above-mentioned protection sacrifice layer are removed in definition, form first and are opened on the above-mentioned interlayer metal dielectric layer;
Above-mentioned interlayer metal dielectric layer is removed in definition, forms second and is opened on above-mentioned interlayer metal dielectric layer inside and does not expose above-mentioned plain conductor road, and wherein above-mentioned second opening is to be positioned at above-mentioned first opening, aims at above-mentioned plain conductor road;
Remove above-mentioned hard cover curtain layer and the above-mentioned interlayer metal dielectric layer of part, form lead groove and contact through hole simultaneously, make above-mentioned contact through hole bottom expose the plain conductor road, and above-mentioned interlayer metal dielectric layer constitutes notch cuttype or T type profile profile;
Remove above-mentioned protection sacrifice layer, expose above-mentioned interlayer metal dielectric layer surface;
Form a metal barrier layer on above-mentioned interlayer metal dielectric layer, above-mentioned lead groove and above-mentioned contact through hole; And
Fill metal in above-mentioned lead groove and above-mentioned contact through hole, and engage with above-mentioned plain conductor road.
2. the method for improving surface flatness of embedded interlayer metal dielectric layer as claimed in claim 1 is characterized in that above-mentioned protection sacrifice layer is organic antireflecting thing, organic low dielectric constant material or polymer or the oligomerization compound that dissolves in organic solvent.
3. the method for improving surface flatness of embedded interlayer metal dielectric layer as claimed in claim 1 is characterized in that above-mentioned hard cover curtain layer is a kind of in carborundum, silicon nitride or the spin-on glasses.
4. the method for improving surface flatness of embedded interlayer metal dielectric layer as claimed in claim 1 is characterized in that above-mentioned metallic seal layer is a silicon nitride.
5. the method for improving surface flatness of embedded interlayer metal dielectric layer as claimed in claim 1 is characterized in that the metal barrier layer is tantalum/tantalum nitride.
6. the method for improving surface flatness of embedded interlayer metal dielectric layer as claimed in claim 1 is characterized in that above-mentioned first A/F defines above-mentioned lead groove width.
7. the method for improving surface flatness of embedded interlayer metal dielectric layer as claimed in claim 1 is characterized in that the above-mentioned second opening degree of depth and width define above-mentioned lead gash depth and above-mentioned contact through hole width respectively.
8. the described method of improving surface flatness of embedded interlayer metal dielectric layer of claim 1 is characterized in that with an organic solvent removing above-mentioned protection sacrifice layer, and organic solvent is cyclohexane, acetone or different propane.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 02103600 CN1251323C (en) | 2002-02-07 | 2002-02-07 | Method of improving surface flatness of embedded interlayer metal dielectric layer |
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| CN 02103600 CN1251323C (en) | 2002-02-07 | 2002-02-07 | Method of improving surface flatness of embedded interlayer metal dielectric layer |
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| CN1251323C true CN1251323C (en) | 2006-04-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100466381C (en) * | 2007-08-21 | 2009-03-04 | 中国科学院上海微系统与信息技术研究所 | Method for flexible interlinkage with built-in type device |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330039B (en) * | 2007-06-18 | 2010-06-09 | 中芯国际集成电路制造(上海)有限公司 | Method for eliminating load effect using through-hole plug |
| CN102131346B (en) * | 2010-01-15 | 2014-08-06 | 欣兴电子股份有限公司 | Circuit board and manufacturing process thereof |
| CN103531528B (en) * | 2012-07-03 | 2018-03-13 | 联华电子股份有限公司 | The preparation method of dual-damascene structure |
| CN109841594B (en) * | 2017-11-27 | 2021-04-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100466381C (en) * | 2007-08-21 | 2009-03-04 | 中国科学院上海微系统与信息技术研究所 | Method for flexible interlinkage with built-in type device |
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| CN1437244A (en) | 2003-08-20 |
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