CN101599445A - The formation method of welding pad structure - Google Patents

The formation method of welding pad structure Download PDF

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Publication number
CN101599445A
CN101599445A CNA2008101143153A CN200810114315A CN101599445A CN 101599445 A CN101599445 A CN 101599445A CN A2008101143153 A CNA2008101143153 A CN A2008101143153A CN 200810114315 A CN200810114315 A CN 200810114315A CN 101599445 A CN101599445 A CN 101599445A
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layer
welding pad
formation method
etching stop
pad structure
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CN101599445B (en
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王新鹏
沈满华
孙武
张世谋
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Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a kind of formation method of welding pad structure, comprising: the substrate with semiconductor device is provided, and described substrate comprises the etching stop layer on metal interconnecting layer, the described metal interconnecting layer at least, and the passivation layer on the etching stop layer; Forming the photoresist layer of patterning on described passivation layer, is mask etching opening in described passivation layer with described photoresist layer, and described etching ends in the etching stop layer; Dry method is removed described photoresist layer; Adopt fluorine-containing oxygen-free plasmas to remove remaining etching stop layer, to expose described metal interconnecting layer; The metal interconnected laminar surface that exposes is reduced processing; Form soldering pad layer on barrier layer and the described barrier layer being arranged in described opening on the metal interconnecting layer that exposes.It is good that the formation method of welding pad structure provided by the invention can guarantee that the barrier layer covers metal interconnecting layer, thereby effectively prevent the diffusion of the metal of metal interconnecting layer to soldering pad layer, improves the reliability of device.

Description

The formation method of welding pad structure
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of welding pad structure
Background technology
Along with very lagre scale integrated circuit (VLSIC) high integration and high performance demand are increased gradually, semiconductor technology is towards 65nm even the more technology node development of small-feature-size, and the resistance capacitance that the arithmetic speed of chip obviously is subjected to plain conductor and is caused postpones the influence of (Resistance Capacitance Delay Time, RC DelayTime).Therefore in present semiconductor fabrication, adopt copper metal interconnected with low-resistivity more, replace traditional aluminum metal interconnection, to improve the phenomenon that RC postpones.
Because copper has the characteristic of low-resistivity, is that the device of interconnection line can bear more intensive circuit arrangement with copper, reduces production costs, and more can promote the arithmetic speed of chip.In addition, copper also has good deelectric transferred ability, makes longer and stable advantage such as better of life-span of device.But for the aluminum metal interconnection, easier diffusion of copper and oxidized characteristics often cause the problem of device reliability.
In the technology that forms aluminium welding pad, the copper of last one deck metal interconnecting layer diffuses into the aluminium welding pad layer above it easily, and causes aluminium welding pad to lose efficacy, so usually between copper interconnection layer and aluminium welding pad layer, must form the barrier that prevents the copper diffusion, for example materials such as TaN, TaSiN, Ta.For example publication number is the manufacture method of aluminium welding pad structure that discloses a kind of semiconductor device of copper-connection among the embodiment of CN101136356A patent application document: the Semiconductor substrate that has buffer layer and copper wiring layer is provided, and described copper wiring layer is embedded in the buffer layer; Form the tantalum-nitride diffusion barrier layer at described copper wiring layer and dielectric isolation laminar surface then; Then on diffusion impervious layer, form passivation layer, on described passivation layer, etch opening and fill metallic aluminium, form aluminium welding pad.
The existing copper process technique forms the technology of aluminium welding pad specifically referring to shown in Figure 1A to Fig. 1 C.Semi-conductive substrate 100 at first is provided, have dielectric layer 110 on the described substrate and be embedded in last one deck copper interconnection layer 105 in the dielectric layer, on described copper interconnection layer 105, form etching stop layer 120 and passivation layer 130 successively, shown in Figure 1A, spin coating photoresist 140 on described passivation layer 130, be formed for the filling aluminum weld pad opening 135 pattern and in passivation layer 130, etch opening 135, for preventing the copper interconnection layer 105 of overetch destruction lower floor, etching ends in the etching stop layer 120; Shown in Figure 1B, be not less than under 250 ℃ at underlayer temperature then, adopt oxygen gas plasma to remove photoresist, then wet chemical cleans and removes residue; Shown in Fig. 1 C, with remaining etching stop layer 120 complete etchings and expose copper interconnection layer 105, wet chemical cleans and removes residue once more, behind the cvd nitride tantalum barrier layer 140, fills metallic aluminium opening 135 in, formation aluminium welding pad 145.
Yet in actual production process, the barrier layer to metal interconnected laminar surface can not be good covering, cause the metal of metal interconnecting layer to spread to the upper strata, cause that weld pad lost efficacy, for example, the copper in the copper interconnection layer passes the barrier layer to the diffusion of aluminium welding pad layer, and aluminium welding pad was lost efficacy.
The reason that produces the problems referred to above may be: inevitably can residually there be small spine 101 on copper interconnection layer 105 surfaces through cmp, after etching opening 135, these copper spines can not be covered and exposing surface by remaining etching stop layer, when next adopting dry method to remove photoresist 140, the copper spine 101 that exposes is oxidized to cupric oxide and extends in copper interconnection layer 105, in the process that wet chemical cleans, cupric oxide is dissolved in washing lotion, so formed rough surface, make the barrier layer 150 of subsequent deposition can not be to the good covering in copper interconnection layer 105 surface, cause the copper of lower floor to pass the aluminium welding pad 145 that barrier layer 150 diffuses into the upper strata, thereby aluminium welding pad was lost efficacy.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of welding pad structure, and it is good to guarantee that the barrier layer covers metal interconnecting layer, thereby effectively prevents the diffusion of the metal of metal interconnecting layer to soldering pad layer, improves the reliability of device.
For addressing the above problem, the invention provides a kind of formation method of welding pad structure, comprising:
Substrate with semiconductor device is provided, and described substrate comprises the etching stop layer on metal interconnecting layer, the described metal interconnecting layer at least, and the passivation layer on the etching stop layer;
Forming the photoresist layer of patterning on described passivation layer, is mask etching opening in described passivation layer with described photoresist layer, and described etching ends in the etching stop layer;
Dry method is removed described photoresist layer;
Adopt fluorine-containing oxygen-free plasmas to remove remaining etching stop layer, to expose described metal interconnecting layer;
The metal interconnected laminar surface that exposes is reduced processing;
Form soldering pad layer on barrier layer and the described barrier layer being arranged in described opening on the metal interconnecting layer that exposes.
Optionally, described etching opening and described removal photoresist layer original position in same chamber are carried out.
Optionally, described removal photoresist layer and the remaining etching stop layer of described removal original position in same chamber are carried out.
Optionally, remaining etching stop layer of described removal and the described metal interconnected laminar surface that exposes is reduced are handled in same chamber original position and are carried out.
Preferably, described etching opening, described removal photoresist layer, the remaining etching stop layer of described removal and the described metal interconnected laminar surface that exposes is reduced are handled all in same chamber original position and are carried out.
Preferably, described removal photoresist layer using plasma ashing method, the temperature of controlling described substrate is lower than 50 ℃.
Optionally, described fluorine-containing oxygen-free plasmas comprises CF 4, C 4F 8, CHF 3In a kind of or plasmas that at least two kinds of combination of gases produce.
Preferably, the method that adopts the metal interconnected laminar surface of hydrogen plasma bombardment is handled in described reduction.
Preferably, the gas that produces described hydrogen plasma comprises a kind of in hydrogen, the ammonia.
The method that adopts reducibility gas that metal interconnected laminar surface is reduced is handled in described reduction.
Optionally, also comprise removing before the remaining etching stop layer described remaining etching stopping laminar surface is reduced processing.
Compared with prior art, the present invention has the following advantages:
At first, do not carry out wet-cleaned after removing photoresist layer, and directly remove remaining etching stop layer, the metal oxide that produces in the time of can preventing to remove photoresist is dissolved among the cleaning fluid, and adopt the remaining etching stop layer of fluorine-containing oxygen-free plasmas etching, can remove the metal oxide of the generation of removing photoresist and preventing that metal interconnecting layer is by further oxidation; Secondly, remove remaining etching stop layer after, the metal interconnecting layer that exposes reduced to handle the natural oxide on surface is reduced.The resultant effect of above-mentioned technology makes the barrier layer of subsequent technique deposition form good covering and contact with metal interconnecting layer, thereby can effectively avoid the diffusion of the metal of metal interconnecting layer to soldering pad layer, improves the reliability of device.
In addition, in the formation method of welding pad structure of the present invention, etching opening, remove photoresist layer, remove the residue etching stop layer, the metal interconnecting layer surface reduction that exposes is handled these four processing steps can in a chamber, original position carry out, the oxidation that causes in the time of not only can avoiding wafer to change between distinct device is stain, and helps enhancing productivity.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Figure 1A to Fig. 1 C is a kind of process schematic representation that forms aluminium welding pad in the existing copper process technique;
Fig. 2 is the flow chart of the formation method of welding pad structure described in the embodiment of the invention;
Fig. 3 A to Fig. 3 F is the schematic diagram of the formation method of welding pad structure in the embodiment of the invention one;
Fig. 4 A to Fig. 4 C is the schematic diagram of the formation method of welding pad structure in the embodiment of the invention two.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 2 is the flow chart of the formation method of welding pad structure of the present invention, may further comprise the steps:
Step 11, substrate with semiconductor device is provided, described substrate includes multiple layer metal interconnection layer on source region, the active area and the passivation layer on last one deck metal interconnecting layer, also has etching stop layer between described passivation layer and the last one deck metal interconnecting layer, be used for determining etching terminal, prevent the damage of overetch simultaneously lower metal; In copper wiring, the material of described metal level is a copper.
Step 12, spin coating photoresist layer on described passivation layer, exposure, the back of developing form etching pattern, adopt dry plasma etch etching opening in described passivation layer, described etching ends in the etching stop layer, at once ablation goes just to stop behind a part of etching stop layer, and remaining etching stop layer is protected the metal of lower floor; Described opening is positioned at corresponding position, metal interconnecting layer top, fills metal to form soldering pad layer in opening after waiting to remove remaining etching stop layer.
Step 13, the using plasma dry method is removed photoresist and is removed described photoresist layer, does not carry out wet-cleaned then and directly enters next step and remove etching stop layer, prevents that the oxide that forms in the process of removing photoresist is cleaned the liquid dissolving, in copper wiring, described oxide is a cupric oxide.
Step 14 adopts fluorine-containing oxygen-free plasmas to remove remaining etching stop layer, to expose metal interconnecting layer, does not have oxygen in the gas of generation plasma, to prevent that metal interconnecting layer is oxidized in the etching process.
Step 15 is reduced processing to the metal interconnected laminar surface that exposes, and removes natural oxide, to form surface of good, its barrier layer that can be formed is later on well covered.
Step 16 is carried out wet-cleaned to the wafer after the reduction processing, forms the barrier layer then on described metal interconnecting layer, then fills metal in being coated with the opening on barrier layer, forms soldering pad layer behind the patterning; The material of described soldering pad layer is aluminium, aluminium copper or alusil alloy.
The formation method of welding pad structure of the present invention is described in detail in detail below in conjunction with specific embodiment.
Embodiment one
Fig. 3 A to Fig. 3 F is the schematic diagram of the formation method of welding pad structure among the embodiment one.In the present embodiment, the material of metal interconnecting layer is a copper, and the material of soldering pad layer is an aluminium.
Shown in Fig. 3 A, a substrate 200 with semiconductor device is provided, described substrate 200 includes the multiple layer metal interconnection layer on source region, the active area; Form last one deck metal interconnecting layer 205 and buffer layer 210 in described substrate 200, described metal interconnecting layer 205 is embedded among the buffer layer 210; The material of metal interconnecting layer 205 is a copper, and its formation method includes but not limited to physical vaporous deposition and chemical vapour deposition technique; The material of buffer layer 210 includes but not limited to unadulterated silicon dioxide (USG), phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG), fluorine silex glass (FSG) or has a kind of or its combination in the advanced low-k materials, described have advanced low-k materials include but not limited to black diamond (Black Diamond, BD) or coral TM, (U.S. Novellus company product), its formation method includes but not limited to HDPCVD, PECVD or SACVD.
On described metal interconnecting layer 205 and buffer layer 210, form etching stop layer 220, be used for determining etching terminal, prevent the damage of overetch simultaneously lower metal; Described etching stop layer 220 includes but not limited to a kind of in silicon nitride, silicon oxynitride, carborundum, the nitrogen-doped silicon carbide, and its formation method is a chemical vapour deposition technique, is 100 dust to 500 dusts according to device property and size design deposit thickness.
On described etching stop layer 220, form passivation layer 230, be used to protect the semiconductor device of lower floor to avoid the pollution of moisture and impurity, also be used for the isolated insulation weld pad, to prevent the metal connecting line short circuit; Passivation layer can be individual layer or two-layer at least, and its material includes but not limited to silica, silicon oxynitride, silicon nitride, adopts chemical vapour deposition technique to form;
Passivation layer 230 in the present embodiment is made up of two-layer, comprise silicon oxide layer that is positioned on the etching stop layer 220 and the silicon nitride layer that is positioned on the silicon oxide layer, reach the effect that discharges stress by adjusting two-layer thickness and technology, wherein, the thickness of silicon oxide layer is about 4000 dusts, and the thickness of silicon nitride layer is about 6000 dusts.
Shown in Fig. 3 B, spin coating photoresist layer 240 on described passivation layer 230 forms pattern through exposure imaging, and the photoresist layer 240 with patterning is that mask using plasma method in passivation layer 230 etches opening 235 then; Described opening 235 ends in the etching stop layer 220, that is to say, promptly stops etching after removing a part of etching stop layer, and the metal of remaining etching stop layer protection lower floor is not by plasma damage; Opening 235 is positioned at the position of metal interconnecting layer 205 top correspondences, waits to remove and fills metal behind the remaining etching stop layer to form soldering pad layer in opening 235.
In plasma etching equipment, carry out etching technics in the present embodiment.The plasma of the fluoro-gas that the silicon nitride layer in the etching passivation layer 230 adopts, described fluoro-gas includes but not limited to CF 4, CHF 3, simultaneously also be mixed with oxygen and argon gas in the etching gas, be used to dilute the concentration of fluoro-gas and improve selection ratio lower floor's silica, as example, gas flow is respectively, CF 4: 120sccm, CHF 3: 15sccm, oxygen: 30sccm, argon gas: 600sccm, etch period 65s; Silicon oxide layer in the etching passivation layer 230 also adopts the plasma of fluoro-gas, and described fluoro-gas includes but not limited to C 4F 8, also be mixed with oxygen and argon gas simultaneously, as example, gas flow is respectively, C 4F 8: 10sccm, oxygen: 10sccm, argon gas: 600sccm, etch period 90s.
Shown in Fig. 3 C, adopt plasma to remove photoresist layer 240 after the etching opening 235, produce isoionic gas and include but not limited to oxygen, NO, N 2A kind of among the O, the temperature at the semiconductor-based end is controlled in below 50 ℃, usually above 250 ℃, the low temperature method of removing photoresist described in the present embodiment can be avoided the oxidation to the copper spine that exposes the etching stopping laminar surface to a certain extent with respect to the base reservoir temperature of prior art when removing photoresist; As example, the flow of oxygen is: 800sccm, the driving source power of plasma is 800w.
Preferably, etching opening 235 backs original position in same chamber is removed photoresist layer 240, reduces oxidation and contaminating impurity in the wafer transfer process.
Shown in Fig. 3 D, adopt the plasma etching of fluorine-containing anaerobic to remove remaining etching stop layer, to expose the surface of metal interconnecting layer 205, described fluorine-containing oxygen-free plasmas comprises CF 4, C 4F 8, CHF 3In a kind of or plasmas that at least two kinds of combination of gases produce, also be mixed with argon gas simultaneously as diluent gas, the oxygen-containing gas that does not comprise oxygen and other in the etching gas, for example ozone, carbon monoxide, carbon dioxide can prevent that the copper spine of metal surface of lower floor is oxidized; As example, the flow of gas is CF 4: 100sccm, argon gas: 200sccm, etch period 60s.
After removing photoresist layer 240, do not carry out wet-cleaned in the said process, but the direct remaining etching stop layer of etching, the cupric oxide of avoiding generating in the process of removing photoresist is dissolved in cleaning fluid, make the layer on surface of metal out-of-flatness, and cause the barrier layer of subsequent deposition relatively poor the spreadability of metal interconnected laminar surface; Preferably, behind the removal photoresist layer 240, the remaining etching stop layer of original position etching in same chamber.
Then, adopt hydrogen plasma to bombard to metal interconnecting layer 205 surfaces of exposing, the cupric oxide on copper interconnection layer surface and hydrogen plasma reaction, and be reduced to copper.The gas that produces hydrogen plasma includes but not limited to hydrogen, ammonia, and preferred gas is the higher hydrogen of ionization level, and as example, the exciting power in plasma excitation source is 500w, and the flow of hydrogen is 1000sccm, and the time of plasma treatment is 60s.In addition, plasma bombards and also plays the effect of removing the residual polyalcohol on metal interconnecting layer 205 surfaces and opening 235 sidewalls.
Preferably, removing behind the remaining etching stop layer in same chamber original position carries out plasma deoxidization and handles.
Preferred, above-mentioned etching opening 235, remove photoresist layer 240, remove residue etching stop layer 220, copper interconnection layer 205 surface reductions that expose are handled these four processing steps can in a chamber, original position carry out, the oxidation that causes in the time of not only can avoiding wafer to change between distinct device is stain, and helps enhancing productivity.
Shown in Fig. 3 E, wet-cleaned is removed after the residue, form barrier layer 250 on metal interconnecting layer 205, the metal interconnecting layer 205 that expose to the major general on described barrier layer 250 and the sidewall of opening 235 cover, and the copper that is used for the barrier metal interconnection layer spreads to the upper strata.This barrier layer 250 can be individual layer or two-layer at least, its material includes but not limited to the combination of a kind of among Ta, TaN, TaSiN, the WN or at least two kinds, adopting physical vaporous deposition, chemical vapour deposition technique, pulsed laser deposition or known other film deposition techniques, is about 100 dusts according to device property and size design deposit thickness.
Shown in Fig. 3 F, in the opening 235 that is coated with barrier layer 250, fill metallic aluminium, patterning forms aluminium welding pad layer 245, adopts physical vaporous deposition deposition of aluminum soldering pad layer, and thickness is 9000 dust to 10000 dusts.
The method that adopts the hydrogen plasma bombardment among the above embodiment is reduced processings to the metal interconnecting layer that exposes, and in fact, the method that the employing reducibility gas reduces to metal interconnected laminar surface is handled in described reduction, specifically describes in detail as following examples.
Embodiment two
Fig. 4 A to Fig. 4 C is the schematic diagram of the formation method of welding pad structure among the embodiment two.In the present embodiment, the material of metal interconnecting layer is a copper, and the material of soldering pad layer is an aluminium.
Shown in Fig. 4 A, a substrate 300 with semiconductor device is provided, described substrate 300 includes the multiple layer metal interconnection layer on source region, the active area; Form last one deck metal interconnecting layer 305 and buffer layer 310 in described substrate 300, described metal interconnecting layer 305 is embedded among the buffer layer 310; On described metal interconnecting layer 305 and buffer layer 310, form etching stop layer 320, be used for determining etching terminal, prevent the damage of overetch simultaneously lower metal; On described etching stop layer 320, form passivation layer 330, be used to protect the semiconductor device of lower floor to avoid the pollution of moisture and impurity, also be used for the isolated insulation weld pad, to prevent the metal connecting line short circuit; The material of above-mentioned metal interconnecting layer 305, buffer layer 310, etching stop layer 320, passivation layer 330, formation method, thickness etc. are similar to embodiment one, do not repeat them here.
Spin coating photoresist layer 340 on described passivation layer 330 forms pattern through exposure imaging, and using plasma etches opening 335 in passivation layer 330 then; Described opening 335 ends in the etching stop layer 320.
Shown in Fig. 4 B, adopt plasma to remove photoresist layer 340 after the etching opening 335, produce isoionic gas and include but not limited to oxygen, NO, N 2O, the temperature at the semiconductor-based end is controlled in below 50 ℃; Adopt fluorine-containing oxygen-free plasmas etching to remove remaining etching stop layer then, expose the metal interconnecting layer 305 of lower floor.
Then directly processing is reduced on metal interconnecting layer 305 surfaces of exposing, the method that adopts reducibility gas that metal interconnected laminar surface is reduced in the present embodiment, described reducibility gas includes but not limited to hydrogen, carbon monoxide, at a certain temperature, reducibility gas can be a copper with the copper oxide reduction on metal interconnecting layer 305 surfaces, makes metal interconnecting layer 305 by the good covering in the barrier layer of subsequent deposition.As example, reducibility gas is a carbon monoxide, flow 800sccm, and base reservoir temperature is 300 ℃, recovery time 90s.
Shown in Fig. 4 C, wet-cleaned is removed after the residue, form barrier layer 350 on metal interconnecting layer 305, the metal interconnecting layer 305 that expose to the major general on described barrier layer 350 and the sidewall of opening 335 cover, and the copper that is used for the barrier metal interconnection layer spreads to the upper strata.Then fill metallic aluminium in the opening 335 that is coated with barrier layer 350, patterning forms aluminium welding pad layer 345.The material of above-mentioned barrier layer 350, aluminium welding pad layer 345, formation method, thickness etc. are similar to embodiment one, do not repeat them here.
Similar with embodiment one, etching opening 335 in this example, remove photoresist layer 340, remove residue etching stop layer 320, copper interconnection layer 305 surface reductions that expose are handled these four processing steps also can in a chamber, original position carry out.
In another embodiment of the present invention, the formation method of described welding pad structure also comprises to be removed before the remaining etching stop layer reducing processing in its surface, be used for removing of photoresist by plasma process, the copper spine that exposes the etching stopping laminar surface may be oxidized, and described reduction is handled and the oxide of copper spine can be reduced; The method that reduction is handled is identical with embodiment one, embodiment two, and promptly hydrogen plasma bombards under metal interconnected laminar surface or the reducing atmosphere metal interconnected laminar surface is reduced.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Method that reduction described in the embodiment is handled has only provided hydrogen plasma and has bombarded and under metal interconnected laminar surface or the reducing atmosphere metal interconnected laminar surface is reduced two kinds; other can make the cupric oxide of metal interconnected laminar surface be reduced, and improve the barrier layer to the method for reduction treatment of metal interconnecting layer covering power also within the scope of protection of the invention.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.

Claims (11)

1, a kind of formation method of welding pad structure is characterized in that, comprising:
Substrate with semiconductor device is provided, and described substrate comprises the etching stop layer on metal interconnecting layer, the described metal interconnecting layer at least, and the passivation layer on the etching stop layer;
Forming the photoresist layer of patterning on described passivation layer, is mask etching opening in described passivation layer with described photoresist layer, and described etching ends in the etching stop layer;
Dry method is removed described photoresist layer;
Adopt fluorine-containing oxygen-free plasmas to remove remaining etching stop layer, to expose described metal interconnecting layer;
The metal interconnected laminar surface that exposes is reduced processing;
Form soldering pad layer on barrier layer and the described barrier layer being arranged in described opening on the metal interconnecting layer that exposes.
2, the formation method of welding pad structure according to claim 1 is characterized in that, described etching opening and described removal photoresist layer original position in same chamber are carried out.
3, the formation method of welding pad structure according to claim 1 is characterized in that, described removal photoresist layer and the remaining etching stop layer of described removal original position in same chamber are carried out.
4, the formation method of welding pad structure according to claim 1 is characterized in that, remaining etching stop layer of described removal and the described metal interconnected laminar surface that exposes is reduced are handled in same chamber original position and carried out.
5, the formation method of welding pad structure according to claim 1, it is characterized in that described etching opening, described removal photoresist layer, the remaining etching stop layer of described removal and the described metal interconnected laminar surface that exposes is reduced are handled all in same chamber original position and carried out.
6, according to the formation method of each described welding pad structure of claim 1 to 5, it is characterized in that, described removal photoresist layer using plasma ashing method, the temperature of controlling described substrate is lower than 50 ℃.
According to the formation method of each described welding pad structure of claim 1 to 5, it is characterized in that 7, described fluorine-containing oxygen-free plasmas comprises CF 4, C 4F 8, CHF 3In a kind of or plasmas that at least two kinds of combination of gases produce.
According to the formation method of each described welding pad structure of claim 1 to 5, it is characterized in that 8, the method that adopts the metal interconnected laminar surface of hydrogen plasma bombardment is handled in described reduction.
9, the formation method of welding pad structure according to claim 8 is characterized in that, the gas that produces described hydrogen plasma comprises a kind of in hydrogen, the ammonia.
According to the formation method of each described welding pad structure of claim 1 to 5, it is characterized in that 10, the method that adopts reducibility gas that metal interconnected laminar surface is reduced is handled in described reduction.
11, according to the formation method of each described welding pad structure of claim 1 to 5, it is characterized in that, also comprise removing before the remaining etching stop layer described remaining etching stopping laminar surface is reduced processing.
CN2008101143153A 2008-06-03 2008-06-03 Forming method of welding pad structure Expired - Fee Related CN101599445B (en)

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CN105448749A (en) * 2014-08-20 2016-03-30 中芯国际集成电路制造(上海)有限公司 Method for manufacturing lead bonding pad
CN105511176A (en) * 2016-01-29 2016-04-20 京东方科技集团股份有限公司 Preparation method of array substrate
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CN112201615A (en) * 2020-09-09 2021-01-08 长江存储科技有限责任公司 Method for manufacturing bonding pad of semiconductor device and method for manufacturing semiconductor device
CN113097075A (en) * 2020-01-08 2021-07-09 华邦电子股份有限公司 Semiconductor device and method of forming the same
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US8466063B2 (en) 2010-02-09 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integration of bottom-up metal film deposition
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US9214543B2 (en) 2010-02-09 2015-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integration of bottom-up metal film deposition
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CN103972160A (en) * 2014-04-22 2014-08-06 上海华力微电子有限公司 Method for lowering influence on copper interconnection reliability from online WAT testing
CN103972160B (en) * 2014-04-22 2017-01-18 上海华力微电子有限公司 Method for lowering influence on copper interconnection reliability from online WAT testing
CN105448749A (en) * 2014-08-20 2016-03-30 中芯国际集成电路制造(上海)有限公司 Method for manufacturing lead bonding pad
CN105448749B (en) * 2014-08-20 2018-03-30 中芯国际集成电路制造(上海)有限公司 The manufacture method of lead wire welding mat structure
CN105742231A (en) * 2014-12-11 2016-07-06 中国科学院微电子研究所 Method for forming nanowire array
CN105185787A (en) * 2015-08-26 2015-12-23 深圳市华星光电技术有限公司 Method for manufacturing array substrate, array substrate and liquid crystal display panel
CN105185787B (en) * 2015-08-26 2018-08-14 深圳市华星光电技术有限公司 Make method, array substrate and the liquid crystal display panel of array substrate
CN105511176A (en) * 2016-01-29 2016-04-20 京东方科技集团股份有限公司 Preparation method of array substrate
CN110767556A (en) * 2019-10-30 2020-02-07 华虹半导体(无锡)有限公司 Smart card chip processing method and smart card chip
CN113097075A (en) * 2020-01-08 2021-07-09 华邦电子股份有限公司 Semiconductor device and method of forming the same
CN113097075B (en) * 2020-01-08 2024-03-22 华邦电子股份有限公司 Semiconductor device and method of forming the same
CN112201615A (en) * 2020-09-09 2021-01-08 长江存储科技有限责任公司 Method for manufacturing bonding pad of semiconductor device and method for manufacturing semiconductor device
CN112201615B (en) * 2020-09-09 2024-04-19 长江存储科技有限责任公司 Method for manufacturing bonding pad of semiconductor device and method for manufacturing semiconductor device
CN113388827A (en) * 2021-04-25 2021-09-14 全立传感科技(南京)有限公司 Method for depositing a metal film on a substrate having high aspect ratio patterned features

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