CN106611743A - Method of manufacturing air gap/copper interconnection structure - Google Patents

Method of manufacturing air gap/copper interconnection structure Download PDF

Info

Publication number
CN106611743A
CN106611743A CN201611240356.8A CN201611240356A CN106611743A CN 106611743 A CN106611743 A CN 106611743A CN 201611240356 A CN201611240356 A CN 201611240356A CN 106611743 A CN106611743 A CN 106611743A
Authority
CN
China
Prior art keywords
copper
interconnection structure
medium
copper interconnection
gap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201611240356.8A
Other languages
Chinese (zh)
Inventor
左青云
林宏
李铭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Original Assignee
Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Integrated Circuit Research and Development Center Co Ltd filed Critical Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority to CN201611240356.8A priority Critical patent/CN106611743A/en
Publication of CN106611743A publication Critical patent/CN106611743A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method of manufacturing an air gap/copper interconnection structure comprises the following steps: providing a semiconductor substrate, completing a CMOS device front-end process on the semiconductor substrate, and forming a conventional first medium/copper interconnection structure on the semiconductor substrate; carrying out surface treatment on the conventional first medium/copper interconnection structure in a nitrogen atmosphere, and forming a layer of nitrogen-containing compound of copper on the surface of a copper interconnection line; using an etching device to etch a first medium in the middle of the copper interconnection line, wherein the first medium is etched with a fluorine-based gas and an oxygen-based gas, and the layer of nitrogen-containing compound of copper protects the copper interconnection line from exposure in the etching gas atmosphere; using wet solution to remove residual photoresist, and carrying out cleaning; and depositing a second medium to form an air gap/copper interconnection structure.

Description

A kind of manufacture method of air-gap/copper interconnection structure
Technical field
The present invention relates to field of semiconductor processing and manufacturing, more particularly to a kind of manufacture method of air-gap/copper interconnection structure.
Background technology
Transistor constantly develops with Moore's Law, and characteristic line breadth is less and less, and integration density more and more higher, performance is more next It is more powerful.For complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor, abbreviation CMOS) for transistor, speed is the important indicator for characterizing its performance.
It will be apparent to those skilled in the art that the speed of CMOS is related to the delay of CMOS, before the delay of CMOS can be subdivided into The delay of road device and the delay of post-channel interconnection line;Also, as semiconductor processing dimensions are reduced, the CMOS of post-channel interconnection line prolongs Slow impact becomes increasing, and topmost delay is had become in advanced technologies.The delay of post-channel interconnection line is mainly By interconnecting lead resistance R and interconnecting lead between electric capacity C (i.e. RC) determine.
In order to reduce post-channel interconnection line RC retardation ratio, Integrated circuit manufacturers trying every possible means to reduce always interconnecting lead resistance and Electric capacity between interconnecting lead, such as replaces aluminum conductor, using the lower low-k media of dielectric constant using the lower copper conductor of resistivity Replace silica dioxide medium.
For the latter, the technology innovation of several technology bands is had already been through, medium is from SiO between interconnecting lead2→F doped SiO2(FSG) in the development of → BD I → BD II → BD III, the dielectric constant of medium is persistently dropping between interconnecting lead It is low, the demand for reducing post-channel interconnection line RC is met with this.
It is well known that the relative dielectric constant of vacuum is 1, the relative dielectric constant of air is also about 1, and it is modal The medium of minimum relative dielectric constant.Therefore, the traditional sucrose between interconnection line is replaced also to be suggested therewith using air part, Here it is air-gap/copper interconnection structure technology.
The forming method of air-gap may be roughly divided into following two big class:
The first kind, first forms normal medium/copper interconnection structure using traditional technique, is then removed by etching technics Medium between copper interconnecting line, finally by chemical vapor deposition method air-gap is formed;
Equations of The Second Kind, using sacrifice layer, such as thermal degradable polymer, removes after copper interconnection structure is completed Sacrifice layer, forms air-gap.
At present for most of integrated circuit manufacturing enterprises, the processing compatibility of first kind method is higher, therefore more Easily received.Below by accompanying drawing 1-3, sketch in prior art and air-gap/copper-connection is prepared using first kind method The process of structure.
Step S01:First traditional interconnection structure of 102/ bronze medal of first medium 104, the part are formed in Semiconductor substrate 101 Technique is just the same with existing CMOS technology, without extra process costs and risk (as shown in Figure 1), will not be described here;
Step S02:The first medium between copper-connection wire is removed, such as part first is removed using dielectric etch technique and is situated between Matter obtains structure as shown in Figure 2;However, the surface that copper 104 can be caused in etching process is oxidized, certain thickness copper is obtained Oxide 105;
Step S03:Photoresist and cleaning silicon chip that medicinal liquid removes residual are cleaned using rear road;During cleaning, by It is easy to by rear road cleaning medicinal liquid corrosion in Cu oxide 105, and rear road cleans medicinal liquid not corrosion barrier layer 103, therefore, finally Barrier layer " ear " 103 ' is left, as shown in Figure 3.
Due to the presence of barrier layer " ear " 103 ', the structure brings series of negative on subsequent technique and device performance Affect, for example, when using chemical vapor deposition medium, it may appear that:
1., the Step Coverage performance around the barrier layer " ear " 103 ' is deteriorated;
2., the bad mechanical strength on the barrier layer " ear " 103 ' and cause to cave in;
3., the sophisticated electric field intensity in the barrier layer " ear " 103 ' changes, and directly results in CMOS transistor performance evil Change etc..
The content of the invention
In view of the shortcomings of the prior art, it is an object of the invention to provide a kind of system of air-gap/copper interconnection structure Method is made, to solve the problems, such as prior art because there is barrier layer " ear " and the deterioration of caused transistor performance, it is avoided The generation of barrier layer " ear ", not only contributes to chemical vapor deposition method deposit medium and forms air-gap, and improves Transistor performance.
For achieving the above object, technical scheme is as follows:
A kind of manufacture method of air-gap/copper interconnection structure, it is characterised in that include:
Step S1:Semi-conductive substrate is provided, first the front road technique of cmos device is completed on a semiconductor substrate, is then continued to Road copper interconnecting line after formation, i.e., form on the semiconductor substrate conventional first medium/copper interconnection structure;
Step S2:Conventional first medium/the copper interconnection structure is surface-treated in nitrogenous atmosphere, described Copper interconnecting line surface forms the nitrogen-containing compound of one layer of copper;
Step S3:First medium in the middle of the copper interconnecting line is etched using etching apparatus;Wherein, in etching first medium During performed etching using fluorine base gas and epoxide gas, the nitrogen containing compound layer of the copper protects the copper interconnecting line not have In being exposed to etching gas atmosphere;
Step S4:Residual photoresist is removed using wet liquid medicine and is cleaned;
Step S5:Deposit second medium, forms the air-gap/copper interconnection structure.
Preferably, step S1 is specifically included:
Step S11:First medium layer is deposited on a semiconductor substrate;
Step S12:Damascus groove or double damascenes are formed in the first medium layer using lithographic etch process Leather hole slot;
Step S13:Difference deposition preventing layer material and copper interconnection material;
Step S14:Barrier layer and copper interconnection layer are formed through grinding technics, i.e., forms conventional on the semiconductor substrate First medium/copper interconnection structure.
Preferably, the first medium material in the conventional first medium/copper interconnection structure is silicon oxide, the oxygen of Fluorin doped One or more in SiClx, the silicon oxide of carbon doping, silicon nitride, the carborundum of N doping.
Preferably, the oxidation silicon/oxidative silicon multi-layer laminate structure of the silicon carbide/carbon doping of the medium N doping.
Preferably, in step s 2, the thickness of the nitrogen-containing compound of the one layer of copper for being formed on the copper interconnecting line surface can Control and thickness is uniform.
Preferably, the thickness of the nitrogen-containing compound of the copper is 50~300 angstroms.
Preferably, in step s3, using CF4/O2Mixed gas etch the first medium layer.
Preferably, in step s 4, corrosion of the rear road wet liquid medicine for removing residual photoresist to residual photoresist Corrosion rate of the speed more than the nitrogen-containing compound to the copper.
Preferably, in step s 5, the second dielectric layer is deposited using chemical vapor deposition device.
Preferably, the second dielectric layer is silicon oxide, the silicon oxide of Fluorin doped, the silicon oxide of carbon doping, silicon nitride, nitrogen One or more in the carborundum of doping.
From above-mentioned technical proposal as can be seen that in a kind of manufacture method of air-gap/copper-connection that the present invention is provided, first Copper surface by process for treating surface in conventional media/copper interconnection structure forms the nitrogenous chemical combination of the uniform copper of a layer thickness Thing, the nitrogen-containing compound of the copper can protect interconnection line copper not to be etched and aoxidize in subsequent medium etching, and will not By rear road wet liquid medicine fast erosion, it is to avoid cause because rear road wet liquid medicine corrodes the oxide of copper in prior art Barrier layer " ear " structure, is conducive to the deposit of subsequent medium and the formation of air-gap, improves the performance of transistor.
Description of the drawings
Fig. 1 show in prior art the typical case of the first medium/copper interconnection structure for forming traditional on a semiconductor substrate Schematic diagram
Fig. 2 show in prior art and completes first medium between first medium/copper interconnection structure removing copper-connection wire Structural representation afterwards
Fig. 3 leaves the structural representation of barrier layer " ear " after road cleaning step after the completion of showing in prior art
Fig. 4 is a kind of manufacture method schematic flow sheet of air-gap/copper interconnection structure proposed by the invention
Fig. 5 in the embodiment of manufacture method one of air-gap/copper interconnection structure of the present invention by completing what is formed after step S1 Generalized section
Fig. 6 in the embodiment of manufacture method one of air-gap/copper interconnection structure of the present invention by completing what is formed after step S2 Generalized section
Fig. 7 in the embodiment of manufacture method one of air-gap/copper interconnection structure of the present invention by completing what is formed after step S3 Generalized section
Specific embodiment
The specific embodiment of the present invention is described in detail below in conjunction with the accompanying drawings.It should be understood that the present invention can There is various changes in different examples, it is neither departed from the scope of the present invention, and explanation therein and be shown in essence It is taken in explain and is used, and is not used to limit the present invention.
In conjunction with accompanying drawing 4-7, a kind of air-gap/copper wiring technique of the present invention is made further in detail by specific embodiment Describe in detail bright.It should be noted that, accompanying drawing in the form of simplifying very much and uses non-accurately ratio, only to convenient, bright The purpose of the embodiment of the present invention is aided in illustrating clearly.
Fig. 4 is referred to, one of manufacture method of a kind of air-gap/copper interconnection structure of the present invention as shown is preferably The schematic flow sheet of embodiment.In the present embodiment, a kind of manufacture method of air-gap/copper interconnection structure comprises the steps:
Step S01:Semi-conductive substrate is provided, first the front road technique of cmos device is completed on a semiconductor substrate, then after Road copper interconnecting line after continuous formation, i.e., form on the semiconductor substrate conventional first medium/copper interconnection structure.Specifically, Fig. 5 is referred to, Fig. 5 in the embodiment of manufacture method one of air-gap/copper interconnection structure of the present invention by completing to be formed after step S1 Generalized section.
As illustrated, this step first completes the front road technique of cmos device on silicon substrate 301, then continue to form rear road Interconnection line, forms the conventional structure of 302/ copper-connection of medium 304, wherein, label 303 is barrier layer.
Below by one 12 inches of wafer silicon chips as an optional embodiment, to using known CMOS technology, Conventional front road cmos device structure is formed on silicon chip, the concrete steps for then forming interconnection line using copper wiring technique are carried out Explanation.
Specifically, in this embodiment, step S1 may include steps of:
Step S11:First medium layer 302 is deposited in Semiconductor substrate 301;
Step S12:Damascus groove or dual damascene are formed in first medium layer 302 using lithographic etch process Hole slot;
Step S13:Difference deposition preventing layer material and copper interconnection material;
Step S14:Barrier layer 303 and copper interconnection layer 304 are formed through grinding technics, i.e., forms normal on a semiconductor substrate First medium/the copper interconnection structure of rule.
It is preferred that the conventional first medium 302 for being deposited can be silicon oxide, the silicon oxide of Fluorin doped, the oxygen of carbon doping One or more in SiClx, silicon nitride, the carborundum of N doping, in an embodiment of the present invention, first medium 302 is adopted The oxidation silicon/oxidative silicon multi-layer laminate structure of the silicon carbide/carbon doping of N doping.
Step S2:Conventional first medium/the copper interconnection structure is surface-treated in nitrogenous atmosphere, described Copper interconnecting line surface forms the nitrogen-containing compound of one layer of copper.Fig. 6 is referred to, Fig. 6 is the system of air-gap/copper interconnection structure of the present invention Make the generalized section for completing to be formed after step S2 in the embodiment of method one.
As shown in fig. 6, in the present embodiment, conventional first medium/copper interconnection structure is placed in nitrogenous atmosphere to be carried out Surface treatment, forms that a layer thickness is controllable and nitrogen-containing compound 305 of copper in uniform thickness on the surface of interconnection metallic copper 304, It is preferred that the thickness of the nitrogen-containing compound of copper can be 50~300 angstroms.
In the present embodiment, conventional first medium/copper interconnection structure can be placed in plasma chemical vapor deposition and is set In standby, processed using nitrogen plasma, the nitrogenate 305 of the copper of 120 angstroms of thickness is obtained on the surface of copper-connection 304.
In another embodiment, conventional first medium/copper interconnection structure can be placed in plasma chemical vapor deposition In equipment, nitrogenous precursor gas are selected, only optionally deposit the nitrogen-containing compound of 100 angstroms of thickness on the surface of copper-connection 304 CuNSi, and first medium surface can't form the nitrogen-containing compound of copper.
The nitrogen-containing compound 305 of the copper is difficult by fluorine-containing gas etching, and rear nitrogen of the road wet liquid medicine to the copper The corrosion rate of compound 305 is far smaller than the corrosion rate to remaining photoresist, therefore after the nitrogen containing compound layer of the copper is served as Protective layer in continuous technique.
In addition, the nitrogen-containing compound 305 of the copper is also used as the coating (capping of copper interconnecting line 304 Layer), electromigration resistance properties can be effectively improved.
Step S3:First medium in the middle of the copper interconnecting line is etched using etching apparatus;Wherein, in etching first medium During performed etching using fluorine base gas and epoxide gas, the nitrogen containing compound layer of the copper protects the copper interconnecting line not have In being exposed to etching gas atmosphere.Specifically, Fig. 7 is referred to, Fig. 7 is the manufacture method of air-gap/copper interconnection structure of the present invention The generalized section formed after step S3 is completed in one embodiment.
As shown in fig. 7, in the present embodiment, first Jie between copper interconnecting line 304 is removed using photoetching, etching technics Matter.Performed etching using fluorine base gas and epoxide gas during etching first medium, but because the surface of copper interconnecting line 304 has The nitrogen-containing compound 305 of one layer of copper as protective layer, therefore, can only etch away the first medium for needing to remove.
In the present embodiment, CF4/O can be adopted2Mixed gas etch media layer 302, because the surface of copper-connection 304 has The nitrogen-containing compound 305 of one layer of copper, can prevent metallic copper 304 from being oxidized, therefore, the nitrogen-containing compound 305 of copper plays etching The effect of protective layer.
Step S4:Residual photoresist is removed using wet liquid medicine and is cleaned.
Specifically, the photoresist of etching residue is removed and silicon wafer surface cleaning is clean using rear road wet liquid medicine, and Afterwards the corrosion rate of photoresist of the road wet liquid medicine to remaining is far longer than the corrosion of the nitrogen-containing compound to metallic copper or copper Speed, therefore, barrier layer " ear " will not be re-formed.
Step S5:Deposit second medium material, forms the air-gap/copper interconnection structure.
Specifically, second dielectric layer can be deposited using chemical gas-phase deposition method, forms air-gap/copper interconnection structure. Second dielectric layer can be in silicon oxide, the silicon oxide of Fluorin doped, the silicon oxide of carbon doping, silicon nitride, the carborundum of N doping One or more, the air-gap for being formed be located at copper interconnecting line between.In the present embodiment, can be strengthened with using plasma Chemical vapor deposition device deposits according to this carborundum of nitrating and the silicon oxide of carbon dope, due to the depth of the groove between copper-connection 304 It is wide higher, therefore, air-gap can be formed between metal copper-connection automatically when second medium material is deposited, form air Gap/copper interconnection structure.
In sum, in a kind of manufacture method of air-gap/copper interconnection structure that the present invention is provided, by first adopting table It is controllable and copper in uniform thickness nitrogenous that copper surface of the face treatment technology in conventional media/copper interconnection structure forms a layer thickness Compound, by the use of the nitrogen-containing compound of the copper as mask layer during copper metal protective layer and wet-cleaning during dielectric etch, Barrier layer " ear " structure is avoided the formation of, process controllability and concordance is improve, transistor device performance can be effectively improved.
Only embodiments of the invention above, embodiment is simultaneously not used to limit the scope of patent protection of the present invention, therefore The equivalent structure change that every description and accompanying drawing content with the present invention is made, should be included in the same manner the protection of the present invention In the range of.

Claims (10)

1. a kind of manufacture method of air-gap/copper interconnection structure, it is characterised in that include:
Step S1:Semi-conductive substrate is provided, first the front road technique of cmos device is completed on a semiconductor substrate, then described half Conventional first medium/copper interconnection structure is formed on conductor substrate;
Step S2:Conventional first medium/the copper interconnection structure is surface-treated in nitrogenous atmosphere, it is mutual in the copper Line surface forms the nitrogen-containing compound of one layer of copper;
Step S3:First medium in the middle of the copper interconnecting line is etched using etching apparatus;Wherein, in etching first medium process Middle employing fluorine base gas and epoxide gas are performed etching, and the nitrogen containing compound layer of the copper protects the copper interconnecting line not expose In etching gas atmosphere;
Step S4:Residual photoresist is removed using wet liquid medicine and is cleaned;
Step S5:Deposit second medium, forms the air-gap/copper interconnection structure.
2. a kind of manufacture method of air-gap/copper interconnection structure according to claim 1, it is characterised in that the step S1 is specifically included:
Step S11:First medium layer is deposited on a semiconductor substrate;
Step S12:Damascus groove or dual damascene hole are formed in the first medium layer using lithographic etch process Groove;
Step S13:Difference deposition preventing layer material and copper interconnection material;
Step S14:Barrier layer and copper interconnection layer are formed through grinding technics, i.e., forms conventional the on the semiconductor substrate One medium/copper interconnection structure.
3. the manufacture method of a kind of air-gap/copper interconnection structure according to claim 1 and 2, it is characterised in that it is described often Rule first medium/copper interconnection structure in first medium material be silicon oxide, the silicon oxide of Fluorin doped, the silicon oxide of carbon doping, One or more in silicon nitride, the carborundum of N doping.
4. a kind of manufacture method of air-gap/copper interconnection structure according to claim 3, it is characterised in that the medium The oxidation silicon/oxidative silicon multi-layer laminate structure adulterated with the silicon carbide/carbon of N doping.
5. the manufacture method of a kind of air-gap/copper interconnection structure according to claim 1, it is characterised in that in step S2 In, on the copper interconnecting line surface, the thickness of the nitrogen-containing compound of one layer of copper of formation is controllable and thickness is uniform.
6. the manufacture method of a kind of air-gap/copper interconnection structure according to claim 5, it is characterised in that the copper The thickness of nitrogen-containing compound is 50~300 angstroms.
7. the manufacture method of a kind of air-gap/copper interconnection structure according to claim 1, it is characterised in that in step S3 In, using CF4/O2Mixed gas etch the first medium layer.
8. the manufacture method of a kind of air-gap/copper interconnection structure according to claim 1, it is characterised in that in step S4 In, the rear road wet liquid medicine for removing residual photoresist is to remaining the corrosion rate of photoresist more than the nitrogen to the copper The corrosion rate of compound.
9. the manufacture method of a kind of air-gap/copper interconnection structure according to claim 1, it is characterised in that in step S5 In, the second dielectric layer is deposited using chemical vapor deposition device.
10. according to a kind of manufacture method of the arbitrarily described air-gap/copper interconnection structure of claim 1 or 9, it is characterised in that The second dielectric layer is in silicon oxide, the silicon oxide of Fluorin doped, the silicon oxide of carbon doping, silicon nitride, the carborundum of N doping One or more.
CN201611240356.8A 2016-12-28 2016-12-28 Method of manufacturing air gap/copper interconnection structure Pending CN106611743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201611240356.8A CN106611743A (en) 2016-12-28 2016-12-28 Method of manufacturing air gap/copper interconnection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611240356.8A CN106611743A (en) 2016-12-28 2016-12-28 Method of manufacturing air gap/copper interconnection structure

Publications (1)

Publication Number Publication Date
CN106611743A true CN106611743A (en) 2017-05-03

Family

ID=58636176

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611240356.8A Pending CN106611743A (en) 2016-12-28 2016-12-28 Method of manufacturing air gap/copper interconnection structure

Country Status (1)

Country Link
CN (1) CN106611743A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110676216A (en) * 2019-12-03 2020-01-10 长江存储科技有限责任公司 Interconnection structure and forming method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040232552A1 (en) * 2002-12-09 2004-11-25 Advanced Micro Devices, Inc. Air gap dual damascene process and structure
US20080299758A1 (en) * 2007-06-04 2008-12-04 Matsushita Electric Industrial Co., Ltd. Method of manufacturing semiconductor device
CN102969273A (en) * 2012-10-25 2013-03-13 上海集成电路研发中心有限公司 Forming method of copper Damascus interconnection structure with air gaps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040232552A1 (en) * 2002-12-09 2004-11-25 Advanced Micro Devices, Inc. Air gap dual damascene process and structure
US20080299758A1 (en) * 2007-06-04 2008-12-04 Matsushita Electric Industrial Co., Ltd. Method of manufacturing semiconductor device
CN102969273A (en) * 2012-10-25 2013-03-13 上海集成电路研发中心有限公司 Forming method of copper Damascus interconnection structure with air gaps

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110676216A (en) * 2019-12-03 2020-01-10 长江存储科技有限责任公司 Interconnection structure and forming method thereof

Similar Documents

Publication Publication Date Title
US7871923B2 (en) Self-aligned air-gap in interconnect structures
US9281211B2 (en) Nanoscale interconnect structure
US9812390B2 (en) Semiconductor devices including conductive features with capping layers and methods of forming the same
JP2001338978A (en) Semiconductor device and its manufacturing method
JP2004133384A (en) Resist removing agent composition and method for manufacturing semiconductor device
JP2005142369A (en) Method for manufacturing semiconductor device
US6806191B2 (en) Semiconductor device with a copper line having an increased resistance against electromigration and a method of forming the same
US8097536B2 (en) Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layer
JP2009026864A (en) Method of manufacturing semiconductor device and semiconductor device
US8377821B2 (en) Method for forming contact hole structure
EP1401015A1 (en) Selective dry etching of tantalum and tantalum nitride
JP4854938B2 (en) Semiconductor device and manufacturing method thereof
US20070218214A1 (en) Method of improving adhesion property of dielectric layer and interconnect process
CN106611743A (en) Method of manufacturing air gap/copper interconnection structure
JP2004235256A (en) Semiconductor device and its fabricating process
JP2006054251A (en) Method for manufacturing semiconductor device
CN106847740A (en) A kind of process for forming air-gap/copper-connection
KR20030077455A (en) Method for manufacturing semiconductor device using dual-damascene techniques
CN106783730A (en) A kind of method for forming air-gap/copper-connection
JP2004363447A (en) Semiconductor device and method of manufacturing the same
JP4948278B2 (en) Manufacturing method of semiconductor device
JP5125743B2 (en) Manufacturing method of semiconductor device
JP2005191034A (en) Method of manufacturing semiconductor device
JP5387627B2 (en) Manufacturing method of semiconductor device
JP2005136308A (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20170503