KR20040014064A - 실리콘 산화막을 이용한 미세 패턴 형성방법 - Google Patents
실리콘 산화막을 이용한 미세 패턴 형성방법 Download PDFInfo
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- KR20040014064A KR20040014064A KR1020020047233A KR20020047233A KR20040014064A KR 20040014064 A KR20040014064 A KR 20040014064A KR 1020020047233 A KR1020020047233 A KR 1020020047233A KR 20020047233 A KR20020047233 A KR 20020047233A KR 20040014064 A KR20040014064 A KR 20040014064A
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- South Korea
- Prior art keywords
- pattern
- film
- silicon oxide
- photoresist
- layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 73
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 64
- 229910052814 silicon oxide Inorganic materials 0.000 title claims abstract description 64
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 80
- 239000000463 material Substances 0.000 claims abstract description 76
- 238000001312 dry etching Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 25
- 238000000231 atomic layer deposition Methods 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 41
- 239000000758 substrate Substances 0.000 description 6
- 229920006254 polymer film Polymers 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
- G03F7/405—Treatment with inorganic or organometallic reagents after imagewise removal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Organic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (18)
- 물질막 상에 포토레지스트막을 형성하는 단계;상기 포토레지스트막을 노광 및 현상하여 포토레지스트 패턴을 형성하는 단계;상기 물질막 및 포토레지스트 패턴 상에 상기 포토레지스트 패턴에 손상이 생기지 않도록 정합적으로 제 1 실리콘 산화막을 형성하는 단계; 및상기 물질막을 건식 식각하여 물질막 패턴을 형성하는 단계를 포함하는 것을 특징으로 하는 미세 패턴 형성방법.
- 제1항에 있어서, 상기 제 1 실리콘 산화막은 상온에서 400℃ 사이의 온도에서 형성하는 것을 특징으로 하는 미세 패턴 형성방법.
- 제1항에 있어서, 상기 제 1 실리콘 산화막은 200Å 이하의 두께로 형성하는 것을 특징으로 하는 미세 패턴 형성방법.
- 제3항에 있어서, 상기 제 1 실리콘 산화막은 원자층 증착법(Atomic Layer Deposition, ALD)을 이용하여 형성하는 것을 특징으로 하는 패턴 형성방법.
- 제1항에 있어서, 상기 물질막 패턴은 바아 타입(bar type) 패턴인 것을 특징으로 하는 미세 패턴 형성방법.
- 제5항에 있어서, 상기 물질막 패턴은 비트 라인 패턴 또는 워드 라인 패턴인 것을 특징으로 하는 미세 패턴 형성방법.
- 제6항에 있어서, 상기 물질막은 제 2 실리콘 산화막, 폴리 실리콘막, 금속 실리사이드막 및 반사 방지막의 적층체인 것을 특징으로 하는 미세 패턴 형성방법.
- 제1항에 있어서, 상기 물질막 패턴은 홀 타입(hole type) 패턴인 것을 특징으로 하는 미세 패턴 형성방법.
- 물질막 상에 포토레지스트막을 형성하는 단계;상기 포토레지스트막을 노광 및 현상하여 포토레지스트 패턴을 형성하는 단계;상기 물질막 및 포토레지스트 패턴 상에 상기 포토레지스트 패턴에 손상이 생기지 않도록 정합적으로 실리콘 산화막을 형성하는 단계;상기 포토레지스트 패턴보다 상기 제 1 실리콘 산화막에 대하여 식각이 더 잘 일어나는 공정 조건(process recipe)에서 상기 물질막을 식각하는 제 1 건식 식각 단계; 및상기 제 1 실리콘 산화막보다 상기 포토레지스트 패턴에 대하여 식각이 더 잘 일어나는 공정 조건에서 상기 물질막을 식각하여 물질막 패턴을 형성하는 제 2 건식 식각 단계를 포함하는 것을 특징으로 하는 미세 패턴 형성방법.
- 제9항에 있어서, 상기 제 1 실리콘 산화막은 상온에서 400℃ 사이의 온도에서 형성하는 것을 특징으로 하는 미세 패턴 형성방법.
- 제9항에 있어서, 상기 제 1 실리콘 산화막은 200Å 이하의 두께로 형성하는 것을 특징으로 하는 미세 패턴 형성방법.
- 제11항에 있어서, 상기 제 1 실리콘 산화막은 원자층 증착법(Atomic Layer Deposition, ALD)을 이용하여 형성하는 것을 특징으로 하는 패턴 형성방법.
- 제9항에 있어서, 상기 제 1 건식 식각 단계에서는 상기 포토레지스트 패턴의 측벽에 상기 제 1 실리콘 산화막으로 스페이서를 형성하는 것을 특징으로 하는 미세 패턴 형성방법.
- 제9항에 있어서, 상기 제 2 건식 식각 단계에서는 폴리머막이 상기 포토레지스트 패턴 상부에 형성되는 것을 특징으로 하는 미세 패턴 형성방법.
- 제9항에 있어서, 상기 물질막 패턴은 바아 타입(bar type) 패턴인 것을 특징으로 하는 미세 패턴 형성방법.
- 제15항에 있어서, 상기 물질막 패턴은 비트 라인 패턴 또는 워드 라인 패턴인 것을 특징으로 하는 미세 패턴 형성방법.
- 제16항에 있어서, 상기 물질막은 제 2 실리콘 산화막, 폴리 실리콘막, 금속 실리사이드막 및 반사 방지막의 적층체인 것을 특징으로 하는 미세 패턴 형성방법.
- 제9항에 있어서, 상기 물질막 패턴은 홀 타입(hole type) 패턴인 것을 특징으로 하는 미세 패턴 형성방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0047233A KR100480610B1 (ko) | 2002-08-09 | 2002-08-09 | 실리콘 산화막을 이용한 미세 패턴 형성방법 |
US10/452,413 US6989231B2 (en) | 2002-08-09 | 2003-06-03 | Method of forming fine patterns using silicon oxide layer |
JP2003290758A JP2004080033A (ja) | 2002-08-09 | 2003-08-08 | シリコン酸化膜を利用した微細パターン形成方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0047233A KR100480610B1 (ko) | 2002-08-09 | 2002-08-09 | 실리콘 산화막을 이용한 미세 패턴 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040014064A true KR20040014064A (ko) | 2004-02-14 |
KR100480610B1 KR100480610B1 (ko) | 2005-03-31 |
Family
ID=31492862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2002-0047233A KR100480610B1 (ko) | 2002-08-09 | 2002-08-09 | 실리콘 산화막을 이용한 미세 패턴 형성방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6989231B2 (ko) |
JP (1) | JP2004080033A (ko) |
KR (1) | KR100480610B1 (ko) |
Cited By (1)
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KR20170041154A (ko) * | 2015-10-06 | 2017-04-14 | 도쿄엘렉트론가부시키가이샤 | 피처리체의 처리 방법 |
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JPS62194624A (ja) * | 1986-02-21 | 1987-08-27 | Oki Electric Ind Co Ltd | 微細パタ−ンの形成方法 |
KR970024184A (ko) * | 1995-10-16 | 1997-05-30 | 김광호 | 반도체장치의 캐패시터 제조방법(Method of fabricating a capacitor in semiconductor device) |
KR19980054746A (ko) * | 1996-12-27 | 1998-09-25 | 김광호 | 반도체 장치의 패턴 분리방법 |
US6004853A (en) * | 1999-05-27 | 1999-12-21 | Vanguard International Semiconductor Corporation | Method to improve uniformity and the critical dimensions of a DRAM gate structure |
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2003
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KR20170041154A (ko) * | 2015-10-06 | 2017-04-14 | 도쿄엘렉트론가부시키가이샤 | 피처리체의 처리 방법 |
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JP2004080033A (ja) | 2004-03-11 |
US20040029052A1 (en) | 2004-02-12 |
KR100480610B1 (ko) | 2005-03-31 |
US6989231B2 (en) | 2006-01-24 |
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