KR101386858B1 - 반도체 디바이스 및 이의 제조 방법 - Google Patents
반도체 디바이스 및 이의 제조 방법 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims description 46
- 239000000463 material Substances 0.000 claims abstract description 137
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 230000008569 process Effects 0.000 claims description 23
- 239000002243 precursor Substances 0.000 claims description 13
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
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- 125000006850 spacer group Chemical group 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 5
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- 150000001875 compounds Chemical class 0.000 description 3
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 229910017115 AlSb Inorganic materials 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 1
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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Abstract
반도체 디바이스 및 이의 제조 방법이 개시된다. 하나의 실시예에서, 반도체 디바이스의 제조 방법은 작업물에 채널 영역을 형성하고, 채널 영역에 근접하게 소스 또는 드레인 영역을 형성하는 것을 포함한다. 소스 또는 드레인 영역은 SiP, SiAs, 또는 실리사이드를 포함하는 접촉 저항 낮춤 재료층을 포함한다. 소스 또는 드레인 영역은 또한 SiCP 또는 SiCAs를 포함하는 채널 스트레싱 재료층을 포함한다.
Description
본 출원은 다음의 공동 계류중이고 공동 양도된 특허 출원, 즉 2011년 7월 7일 출원되고 발명의 명칭이 "소스 및 드레인 에피텍시를 위한 비소의 인시추 도핑(In-Situ Doping of Arsenic for Source and Drain Epitaxy)"인 출원 번호 제13/178,294호와 관련되며, 이 출원은 참조에 의해 여기에 포함된다.
반도체 디바이스는 예로서 개인용 컴퓨터, 휴대 전화, 디지털 카메라, 및 기타 전자 장비와 같은 다양한 전자 응용제품에서 사용된다. 반도체 디바이스는 통상적으로, 반도체 기판 위에 절연 또는 유전체 재료층, 전도성 재료층, 및 반도성 재료층을 순차적으로 증착하고, 그 위에 회로 컴포넌트 및 요소를 형성하도록 리소그래피를 사용하여 다양한 재료층들을 패터닝함으로써 제조된다.
다중 게이트 전계 효과 트랜지스터(MuGFET; Multiple gate field-effect transistor)는 반도체 기술에서의 최근의 발전이며, 이는 통상적으로 하나보다 많은 수의 게이트를 단일 디바이스로 통합한 금속 산화물 반도체 FET(MOSFET; metal oxide semiconductor)이다. 다중 게이트는 다중 게이트 표면이 전기적으로 단일 게이트로서 작용하도록 단일 게이트 전극에 의해 제어될 수 있거나, 또는 독립적인 게이트 전극에 의해 제어될 수 있다. 한 유형의 MuGFET는 FinFET로 지칭되는데, 이는 집적 회로의 실리콘 표면의 수직 위로 상승된(raised) 핀형 반도체 채널을 구비한 트랜지스터 구조이다.
반도체 디바이스 및 이의 제조 방법이 개시된다.
하나의 실시예에서, 반도체 디바이스의 제조 방법은 작업물에 채널 영역을 형성하고, 채널 영역에 근접하게 소스 또는 드레인 영역을 형성하는 것을 포함한다. 소스 또는 드레인 영역은 SiP, SiAs, 또는 실리사이드를 포함하는 접촉 저항 낮춤 재료층을 포함한다. 소스 또는 드레인 영역은 또한 SiCP 또는 SiCAs를 포함하는 채널 스트레싱 재료층을 포함한다.
본 발명에 따라 반도체 디바이스 및 이의 제조 방법을 제공할 수 있다.
본 개시 및 이의 이점의 보다 완전한 이해를 위해, 이제 첨부 도면과 함께 다음의 설명을 참조한다.
도 1 내지 도 4는 FinFET 응용에서 구현되는 본 개시의 실시예에 따라 다양한 제조 단계들에서 반도체 디바이스를 제조하는 방법의 단면도들을 도시한다.
도 5 및 도 6은 FinFET 응용에서 구현되는 각각 제2 및 제3 실시예의 단면도들이다.
도 7은 추가의 재료층이 반도체 디바이스 위에 형성된 후의 도 6에 도시된 실시예의 단면도이다.
도 8은 플래너 트랜지스터에서 구현되는 실시예를 도시한다.
도 9는 실시예에 따라 반도체 디바이스를 제조하는 방법의 흐름도이다.
다양한 도면에서 대응하는 번호 및 부호는 달리 지시하지 않는 한 일반적으로 대응하는 부분을 지칭한다. 도면은 실시예의 관련 양상을 명확하게 예시하고자 도시된 것이며 반드시 축척대로 도시된 것은 아니다.
도 1 내지 도 4는 FinFET 응용에서 구현되는 본 개시의 실시예에 따라 다양한 제조 단계들에서 반도체 디바이스를 제조하는 방법의 단면도들을 도시한다.
도 5 및 도 6은 FinFET 응용에서 구현되는 각각 제2 및 제3 실시예의 단면도들이다.
도 7은 추가의 재료층이 반도체 디바이스 위에 형성된 후의 도 6에 도시된 실시예의 단면도이다.
도 8은 플래너 트랜지스터에서 구현되는 실시예를 도시한다.
도 9는 실시예에 따라 반도체 디바이스를 제조하는 방법의 흐름도이다.
다양한 도면에서 대응하는 번호 및 부호는 달리 지시하지 않는 한 일반적으로 대응하는 부분을 지칭한다. 도면은 실시예의 관련 양상을 명확하게 예시하고자 도시된 것이며 반드시 축척대로 도시된 것은 아니다.
본 개시의 실시예를 형성하고 사용하는 것이 아래에 상세하게 설명된다. 그러나, 본 개시는 광범위하게 다양한 특정 상황에서 구현될 수 있는 많은 적용 가능한 본 발명의 개념을 제공하는 것임을 알아야 한다. 설명되는 구체적 실시예는 단지 본 개시를 형성하고 사용하기 위한 특정 방식을 예시하는 것이며, 본 개시의 범위를 한정하지 않는다.
본 개시의 실시예는 반도체 디바이스 제조에 관한 것이며, 보다 상세하게는 트랜지스터의 소스 및 드레인 영역의 형성에 관한 것이다. 반도체 디바이스 및 트랜지스터에 대한 신규의 제조 방법 및 이의 구조가 여기에 기재될 것이다.
도 1 내지 도 4는 FinFET 응용에서 구현되는 본 개시의 실시예에 따라 반도체 디바이스(100)를 제조하는 방법의 단면도들을 도시한다. 먼저 도 1을 참조하면, 디바이스를 제조하기 위해, 작업물(workpiece)(102)이 제공된다. 도 1 내지 도 7에 도시된 실시예에서 반도체 재료의 복수의 핀(104)이 작업물(102)에 형성된다.
참조에 의해 여기에 포함되는, 2011년 7월 7일 출원되고 발명의 명칭이 "소스 및 드레인 에피텍시를 위한 비소의 인시추 도핑(In-Situ Doping of Arsenic for Source and Drain Epitaxy)"인 특허 출원 번호 제13/178,294호에 기재된 방법(관련 출원의 도 1 내지 도 4, 도 5a, 및 도 5b, 핀(30) 그리고 이의 설명 참조)을 사용하여 핀(104)이 작업물(102)에 형성될 수 있다. 본 개시의 도 1에 도시된 바와 같이(그리고 관련 참조문헌의 도 6a 및 도 6b에 도시된 바와 같이), 게이트 유전체 재료가 핀(104)을 포함하는 채널 영역(105) 위에 형성되고, 게이트 재료가 게이트 유전체 재료 위에 형성되고, 게이트 재료 및 게이트 유전체 재료가 패터닝되어 게이트(108) 및 게이트 유전체(106)를 형성한다. 측벽 스페이서(110)가 게이트(108) 및 게이트 유전체(106) 위에 형성된다. 본 개시의 도 1에 도시된 도면은 관련 출원의 도 6b에 도시된 것과 유사한 도면임을 유의하자. 쉘로우 트렌치 아이솔레이션(STI; shallow trench isolation) 영역이 작업물(102)에 형성되지만 도 1의 도면에서는 보이지 않으며, STI 영역은 작업물(102) 내에서 도시된 도면에서 종이 안팍으로 종이로부터 떨어져 배치된다.
예를 들어 게이트(108) 상부 부분이 에피텍셜 성장 공정을 사용하여 형성되는 경우, 게이트(108)의 상부 부분은 하부 부분보다 더 좁을 수 있다. 핀(104)을 포함하는 채널 영역(105)은 치수 d1을 구성하는 작업물(102) 내의 높이를 포함한다. 치수 d1은 약 10 내지 50 nm를 포함할 수 있지만, 대안으로서 치수 d1은 다른 값을 포함할 수 있다. 관련 출원에 기재된 바와 같이, 핀(104)은 SiGe, 실리콘, 또는 Ⅲ족 원소와 Ⅴ족 원소를 포함하는 Ⅲ-Ⅴ 화합물 반도체를 포함할 수 있다. Ⅲ-Ⅴ 화합물 반도체는 GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, 이들의 조합 및, 이들의 다층을 포함할 수 있지만, 이에 한정되는 것은 아니다. 핀(104)의 재료는 약 3,000 내지 40,000 cm2/V-s와 같은 높은 이동성(mobility)을 갖는 채널 영역(105)을 달성하도록 선택될 수 있지만, 대안으로서, 핀(104)의 이동성은 다른 값을 포함할 수 있다. 핀(104)은 대안으로서 여기에 개시된 실시예에 따라 다른 반도체 재료를 포함할 수 있다.
도면에는 3개의 트랜지스터 게이트(108) 및 핀(104)만 도시되어 있지만, 실시예에 따르면, 수십 또는 수백의 게이트(108) 및 핀(104)이 예를 들어 도시되지 않은 작업물(102) 상에 제조될 각각의 다이에 대하여 작업물(102)의 표면에 걸쳐 형성될 수 있다.
실시예에 따르면, 도 2에 도시된 바와 같이, 작업물(102)은 예를 들어 측벽 스페이서(110) 사이에 채널 영역(105)에 근접하게 리세스 형성된다(recessed). 작업물(102)은 작업물(102) 재료의 일부가 측벽 스페이서(110) 아래로부터 제거되도록 이방성 성분을 포함하는 에칭 공정(112)을 사용하여 리세스 형성된다. 작업물(102)에 형성된 리세스(114)는 치수 d2를 구성하는 작업물(102)의 상부 표면 내의 깊이를 포함한다. 본 개시의 실시예에 따라 치수 d2는 치수 d1보다 더 크다. 일부 실시예에서, 치수 d2는 치수 d1의 약 2배 이상이다(예를 들어, 도 2 내지 도 4, 및 도 5의 실시예 참조). 다른 실시예에서, 치수 d2는 치수 d1의 약 3배보다 더 크다(도 6의 실시예 참조).
리세스(114)는, 예를 들어 에칭 공정(112) 화학 및/또는 작업물(102)의 결정 구조로 인해, 도시된 바와 같이 실질적으로 사다리꼴 형상을 포함할 수 있다. 대안으로서, 리세스(114)는 원형 또는 타원형(도 8 참조)과 같은 다른 형상을 포함할 수 있다. 실시예에 따르면, 에칭 공정(112)은 채널 영역(105)을 포함하는 핀(104)에 근접하게 또는 "근접 푸시(proximity push)"를 달성하도록 선택된다. 116으로 도시된 리세스(114)의 가장 넓은 부분은 일부 실시예에서 약 10 nm 이하를 구성할 수 있는 치수 d3만큼 핀(104)으로부터 떨어져 있을 수 있다. 치수 d3은 대안으로서 다른 값을 포함할 수 있다.
다음으로, 도 3 및 도 4에 도시된 바와 같이, 리세스(114) 내에 소스 영역(124a) 및 드레인 영역(124b)이 형성된다. 실시예에 따르면, 채널 영역(105)에 매우 근접하게 리세스(114)를 형성하는 것은 유리하게도 채널 영역(105)으로부터 최소한으로 떨어진 간격을 갖는 소스 및 드레인 영역(124a 및 124b)의 형성이 되며, 이는 접촉 저항을 감소시킨다. 제1 실시예에서는, 먼저, 도 3에 도시된 바와 같이, 제1 접촉 저항 낮춤(contact resistance-lowering) 재료층(120a)이 리세스(114)에 증착된다. 제1 접촉 저항 낮춤 재료층(120a)은 예를 들어 에피텍셜 성장 공정 또는 화학 기상 증착(CVD; chemical vapor deposition) 공정과 같은 성장 공정에 의해 형성된 SiP 또는 SiAs를 포함한다. 제1 접촉 저항 낮춤 재료층(120a)은 증착되는 대로 실질적으로 등각이고(conformal), 예를 들어 약 10nm의 두께를 포함할 수 있다. 제1 접촉 저항 낮춤 재료층(120a)은, 예를 들어 측벽 스페이서(110) 상이나 게이트(108)의 상부 표면 상이 아니라, 작업물(102) 재료 상에(또는 여기에 더 기재될 선택적 라이너(118 및 119) 상에) 형성하도록 조정된 선택적 성장 또는 증착 공정을 사용하여 형성될 수 있다. 대안으로서, 제1 접촉 저항 낮춤 재료층(120a)은 다른 방법을 사용하여 형성될 수 있고 다른 치수를 포함할 수 있다.
일부 실시예에서, 제1 접촉 저항 낮춤 재료층(120a)은 트리실란(Si3H8), 아르신(AsH3), 및/또는 기타 전구체를 사용하여 저온 성장을 사용해 형성될 수 있다. 제1 접촉 저항 낮춤 재료층(120a)은 매우 낮은 저항을 달성하도록 고농도 도핑될 수 있다. 예를 들어, 제1 접촉 저항 낮춤 재료층(120a)은 약 1x1020 내지 1x1021의 인, 비소, 또는 기타 물질의 도핑 농도 및 약 0.2 내지 0.4 밀리옴-cm의 저항을 가질 수 있다. 대안으로서, 제1 접촉 저항 재료층(120a)은 다른 양으로 도핑될 수 있고 다른 저항값을 포함할 수 있다. 제1 접촉 저항 낮춤 재료층(120a)은, 예를 들어 소스 및 드레인 영역(124a 및 124b)의, 작업물(102) 및 채널 영역(105)과 같은 인접 컴포넌트 및 요소에 대한 접촉 저항을 낮추도록 조정된다.
제1 접촉 저항 낮춤 재료층(120a)의 형성 전에, 2개의 선택적인 얇은 재료 라이너(118 및 119)가 리세스(114) 내에 형성될 수 있다. 여기에서 제1 라이너라고도 불리는 라이너(118)는 리세스(114)의 하부 표면 상의 SiP 층의 버텀업(bottom-up) 에피텍셜 성장을 포함할 수 있다. 라이너(118)의 형성은 예를 들어 <001> 결정 성장 배향을 포함할 수 있다. 라이너(118)는 예를 들어 소스 및 드레인 영역(124a 및 124b)의 핀(104)에 대한 근접성을 증가시킬 수 있다. 여기에서 제2 라이너라고도 불리는 라이너(119)는 리세스(114)의 측벽 상의 SiAs 층의 핀 측벽 성장을 포함할 수 있다. 라이너(119)의 형성은 예를 들어 <110> 결정 성장 배향을 포함할 수 있다. 라이너(119)는 핀(104) 측벽 상의 전류 확산을 생성할 수 있으며, 전체 핀(104)을 통한 전류 수송 효율을 증가시킬 수 있다. 라이너(118 및 119)는 예를 들어 약 2 내지 10 nm의 두께를 가질 수 있지만, 대안으로서 라이너(118 및 119)는 다른 치수를 포함할 수 있다. 라이너(118 및 119)는 또한 예를 들어 도 5 내지 도 8을 참조하여 여기에 기재될 추가의 실시예에도 포함될 수 있다(도면에는 도시되지 않음).
다음으로, 도 4에 도시된 바와 같이, 채널 스트레싱(channel-stressing) 재료층(122)이 리세스(114)에서 제1 접촉 저항 낮춤 재료층(120a) 위에 증착된다. 채널 스트레싱 재료층(122)은 예를 들어 에피텍셜 성장 공정 또는 CVD 공정과 같은 성장 공정에 의해 형성되는 SiCP 또는 SiCAs를 포함할 수 있다. 채널 스트레싱 재료층(122)은 예를 들어 리세스(144)를 실질적으로 채우도록 또는 작업물(102)의 상부 표면 아래의 미리 결정된 레벨로 리세스(114)를 채우도록 증착될 수 있다. 채널 스트레싱 재료층(122)은 예를 들어 <001> 결정 성장 배향의 SiCP의 에피텍셜 성장을 사용하여 형성될 수 있다. 대안으로서, 채널 스트레싱 재료층(122)은 다른 방법을 사용하여 형성될 수 있고 다른 치수를 포함할 수 있다. 일부 실시예에서, 채널 스트레싱 재료층(122)은 트리실란(Si3H8), 헥사클로로디실란2(HCD: Si2Cl6), 아르신(AsH3), 모노메틸실란(MMS: SiH3CH3), 및/또는 기타 전구체와 같은 전구체를 사용하여 저온 성장을 사용해 형성될 수 있다. 채널 스트레싱 재료층(122)은 매우 낮은 저항을 달성하도록 고농도 도핑될 수 있다. 예를 들어, 채널 스트레싱 재료층(122)은 1x1019 내지 1x1021의 인, 비소 또는 기타 물질의 도핑 농도 및 약 0.3 내지 0.7 밀리옴-cm의 저항을 가질 수 있다. 대안으로서, 채널 스트레싱 재료층(122)은 다른 양으로 도핑될 수 있고 다른 저항값을 포함할 수 있다. 일부 실시예에서 채널 스트레싱 재료층(122)은 예를 들어 채널 영역(105)의 인장 변형(tensile strain)을 유도하도록 C로 도핑된다. 채널 스트레싱 재료층(122)은 예를 들어 핀(104)을 포함하는 채널 영역에 인장 변형을 생성하기 위해 스트레서(stressor)로서 기능하도록 조정된다.
그 다음, 제2 접촉 저항 낮춤 재료층(120b)이 도 4에도 도시된 채널 스트레싱 재료층(122) 위의 리세스(114)에 또는 그 위에 증착된다. 제2 접촉 저항 낮춤 재료층(120b)은 예를 들어 제1 접촉 저항 낮춤 재료층(120a)에 대하여 기재된 바와 유사한 방법에 의해 그리고 유사한 전구체, 유사한 도핑 농도, 및 유사한 저항을 사용하여 성장된 유사한 재료를 포함할 수 있다. 제2 접촉 저항 낮춤 재료층(120b)의 형성은, 예를 들어 측벽 스페이서(110) 상이나 게이트(108)의 상부 표면 상이 아니라, 채널 스트레싱 재료층(122) 상에 형성하도록 조정되는 선택적 성장 또는 증착 공정을 포함할 수 있다. 대안으로서, 제2 접촉 저항 낮춤 재료층(120b)은 다른 방법을 사용하여 형성될 수 있고 다른 치수를 포함할 수 있다. 제2 접촉 저항 낮춤 재료층(120b)은, 나중에 형성되는 컨택(도 7의 컨택(130) 참조)과 같은 인접 컴포넌트 및 요소에 대한, 예를 들어 소스 및 드레인 영역(124a 및 124b)의 접촉 저항을 낮추도록 조정된다. 일부 실시예에서 제2 접촉 저항 낮춤 재료층(120b)의 상부 표면은 작업물(102)의 상부 표면과 실질적으로 동일 평면을 이룰 수 있지만, 대안으로서 제2 접촉 저항 낮춤 재료층(120b)의 상부 표면은 작업물(102)의 상부 표면보다 낮거나 높을 수 있다.
따라서, 도 4에 도시된 실시예에서, 형성되어진 트랜지스터(126)의 신규의 소스 및 드레인 영역(124a 및 124b)은 핀(104)을 포함하는 채널 영역(105)에 대한 증가된 스트레스 및 낮아진 접촉 저항으로 인해 개선된 기능을 달성하는 다층 구조를 포함한다. 소스 및 드레인 영역(124a 및 124b)은 유리하게도 채널 영역(105)에 근접하게 배치되고, 소스 및 드레인 영역(124a 및 124b)은 소스 또는 드레인 영역(124a 및 124b)의 가장 넓은 지점에서, 예를 들어 리세스(114)의 가장 넓은 부분(116)에서 핀(104)을 포함한 채널 영역(105)으로부터 약 20 nm 이하만큼 떨어져 있다.
도 5는 FinFET 응용에서 구현되는 본 개시의 제2 실시예의 단면도를 예시한다. 이 실시예에서는, 제1 실시예에 대하여 기재된 바와 같이 리세스(114)가 형성된 후에 그리고 선택적 라이너(118 및 119)가 리세스(114)에 형성된 후에, 도 5에 도시된 바와 같이, 채널 스트레싱 재료층(122)이 리세스(114)를 부분적으로 채우도록 형성된다. 채널 스트레싱 재료층(122)의 형상은 리세스(114)의 토포그래피(topography)에 실질적으로 일치할 수 있다. 이 실시예에서 채널 스트레싱 재료층(122)의 두께는 약 15 내지 20 nm를 포함할 수 있지만, 대안으로서 채널 스트레싱 재료층(122)은 다른 치수를 포함할 수 있다. 채널 스트레싱 재료층(122)은 예를 들어 제1 실시예에서 채널 스트레싱 재료층(122)에 대하여 기재된 바와 유사한 방법, 전구체, 도핑 레벨 및 저항을 사용하여 형성될 수 있다. 채널 스트레싱 재료층(122)은 리세스(114) 내의 작업물(102)의 하부 표면 및 측벽 상에, 또는 선택적으로 제1 실시예에서 기재되었던 하부 표면 및 측벽 상의 각각의 라이너(118 및 119) 위에 형성된다.
그 다음, 도 5에 도시된 바와 같이, 접촉 저항 낮춤 재료층(120)이 채널 스트레싱 재료층(122) 위에 형성된다. 접촉 저항 낮춤 재료층(120)은 제1 실시예에서 접촉 저항 낮춤 재료층(120a)에 대하여 기재된 바와 유사한 방법, 전구체, 도핑 레벨, 및 저항을 사용하여 형성된 유사한 재료를 포함할 수 있다. 대안으로서, 접촉 저항 낮춤 재료층(120)은 예로서 SiNix, 또는 기타 실리사이드 재료와 같은 실리사이드를 포함할 수 있다. 접촉 저항 낮춤 재료층(120)은 소스 및 드레인 영역(124a 및 124b)의 접촉 저항을 낮춘다.
따라서, 제2 실시예에서, 채널 스트레싱 재료층(122)은 실질적으로 등각이고, 작업물(102)에 집적 접촉하거나 리세스(114)에서 작업물(102) 위에 형성된 라이너(118 및 119)에 직접 접촉하고, 소스 및 드레인 영역(124a 및 124b)의 상부 표면 상의 접촉 저항 낮춤 재료층(120)은 SiP, SiAs 또는 실리사이드를 포함할 수 있다.
도 6은 FinFET 응용에서 구현되는 본 개시의 제3 실시예의 단면도를 예시한다. 이 실시예에서, 채널 스트레싱 재료층(122)은 리세스(114) 내에 먼저 형성되며, 이는 핀(104)을 포함하는 채널 영역(105)에 인장 변형을 생성한다. 이 실시예에서는 채널 스트레싱 재료층(122)이 제2 실시예에서와 같이 등각의 증착 공정을 포함하지 않는다. 오히려, 채널 스트레싱 재료층(122)은 비등각(non-conformal) 증착 공정을 사용하여 리세스(114)의 하부 부분에 형성된다. 채널 스트레싱 재료층(122)은 예를 들어 제1 실시예에서의 채널 스트레싱 재료층(122)에 대해 기재된 바와 유사한 방법, 전구체, 도핑 레벨, 및 저항을 사용하여 형성될 수 있다. 그 다음, 도 6에 도시된 바와 같이 접촉 저항 낮춤 재료층(120)이 리세스를 채우도록 채널 스트레싱 재료층(122) 위에 형성된다. 접촉 저항 낮춤 재료층(120)은 예를 들어 제1 실시예에서의 제1 접촉 저항 낮춤 재료층(120a)에 대해 기재된 바와 유사한 방법, 전구체, 도핑 레벨 및 저항을 사용하여 형성될 수 있다.
도 6에 도시된 실시예에서의 리세스(114)는 치수 d4를 갖는 깊이를 포함할 수 있으며, 치수 d4는 채널 영역(105)을 포함하는 핀(104)의 높이의 치수 d1보다 약 3배 더 크다. 접촉 저항 낮춤 재료층(120)과 채널 스트레싱 재료층(122) 사이의 경계(127)는 이 실시예에서 채널 영역(105)의 바닥에 근접하게 배치될 수 있다. 경계(127)의 위치는 트랜지스터(126)의 성능을 위해 최적화될 수 있다. 예를 들어, 경계(127)는 각각 더 많거나 더 적은 채널 스트레싱 재료층(122)을 형성함으로써 리세스(144)의 위로 또는 아래로 이동될 수 있다.
채널 스트레싱 재료층(122)의 형성은 채널 스트레싱 재료층(122)의 원하는 형상을 달성하도록, 예를 들어 도 5에 도시된 바와 같이 등각이거나 도 6에 도시된 바와 같이 비등각이도록, 증착 공정의 하나 이상의 파라미터를 변경함으로써, 예를 들어 증착 공정의 공정 온도, 압력, 전구체의 유량, 증착, 및/또는 에칭 성분을 제어함으로써 제어될 수 있다.
여기에 기재된 신규의 소스 및 드레인 영역(124a 및 124b)이 형성된 후에, 트랜지스터(126) 및 반도체 디바이스(100)에 대한 제조 공정이 이어질 수 있다. 예를 들어, 도 7은 추가적인 재료층이 반도체 디바이스(100) 위에 형성된 후의 도 6에 도시된 실시예의 단면도이다. 층간 유전체(ILD; inter-level dielectric) 또는 기타 절연체를 포함할 수 있는 절연 재료(128)가 트랜지스터(126)와 소스 및 드레인 영역(124a 및 124b) 위에 형성될 수 있다. 도시된 바와 같이, 전도성 재료를 포함하며 게이트(108)와 소스 및 드레인 영역(124a 및 124b)과의 전기 접촉을 이루는 컨택(130)이 절연 재료(128)에 형성될 수 있다. 전도성 라인(132)이 컨택(130) 위에 형성될 수 있으며, 이는 완성된 반도체 디바이스(100)의 상부 표면 상의 상부 재료층(도시되지 않음) 또는 컨택 패드(또한 도시되지 않음)에 대한 전기 접속을 이룬다.
본 개시의 실시예는 FinFET 디바이스를 참조하여 여기에 기재되었다. 대안으로서, 여기에 기재된 실시예는 도 8에서 단면도로 도시된 바와 같이 플래너(planar) 트랜지스터에서 구현될 수 있다. 반도체 디바이스(100)를 제조하기 위해, STI 영역 또는 기타 절연 영역을 포함할 수 있는 아이솔레이션 영역(134)이 작업물(102)에 형성된다. 게이트 유전체(106) 재료 및 게이트(108) 재료가 작업물(102) 위에 증착되고, 리소그래피를 사용하여 패터닝되어 트랜지스터(126)의 게이트 유전체(106) 및 게이트(108)를 형성한다. 채널 영역(105')은 도시된 바와 같이 게이트 유전체(106) 아래의 플래너 작업물(102)의 일부를 구성한다. 이전 실시예에 대하여 기재된 바와 같이, 측벽 스페이서(110)가 게이트(108) 및 게이트 유전체(106)의 측벽 상에 형성되고, 리세스(114)가 작업물(102)의 상부 표면에 형성된다. 리세스(114)는 예를 들어 채널 영역의 치수 d1와 실질적으로 동일하거나 치수 d1보다 큰 치수 d5를 갖는 깊이를 포함할 수 있다. 리세스(114)는 일부 실시예에서 단면도로 원형 또는 타원형 형상을 포함할 수 있지만, 리세스(114)는 대안으로서 사다리꼴 형상을 포함할 수 있다. 리세스(114)는 도 2 내지 도 6에 도시된 제1, 제2 및 제3 실시예에 대하여 기재된 바와 같이 적어도 하나의 접촉 저항 낮춤 재료층(120, 120a, 또는 120b) 및 채널 스트레싱 재료층(122)으로 채워질 수 있다. 도 2 내지 도 4에 도시된 제1 실시예의 예는 도 8에 예시되며, 이는 2개의 접촉 저항 낮춤 재료층(120a 및 120b)을 포함한다.
도 9는 실시예에 따라 반도체 디바이스(100)를 제조하는 방법의 흐름도(150)이다. 방법은 작업물(102)을 제공하고(단계 152) 작업물(102)에 채널 영역(105)(예를 들어, 핀(104)을 포함함)을 형성하는 것(단계 154)을 포함한다. 게이트 유전체(106)가 채널 영역(105) 위에 형성되고(단계 156), 게이트(108)가 게이트 유전체(108) 위에 형성된다(단계 158). 여기에 기재된 바와 같이, 소스 영역(124a) 및 드레인 영역(124b)은 채널 영역(105)에 근접하게 형성되며(단계 160), 소스 영역(124a) 및 드레인 영역(124b)은 채널 영역(105)에 근접한 접촉 저항 낮춤 재료층(120)(또는 층(120a 및 120b)) 및 채널 스트레싱 재료층(122)을 포함한다.
본 발명의 실시예의 이점은 트랜지스터(126)의 다층 소스 및 드레인 영역(124a 및 124b)에 대한 신규의 구조 및 제조 방법을 제공하는 것을 포함한다. 소스 및 드레인 영역(124a 및 124b)의 다수의 층은 제조 공정 챔버로부터 작업물(102)을 뺄 필요 없이 인시츄(in-situ) 연속적으로 전구체를 변경함으로써 형성될 수 있다. 신규의 소스 및 드레인 영역(124a 및 124b)의 형성은 어닐링 공정 또는 주입 공정을 필요로 하지 않으며, 소스 및 드레인 영역(124a 및 124b)은 저온을 사용하여 형성될 수 있다. 소스 및 드레인 영역(124a 및 124b)을 형성하는 것은 예를 들어 소스 및 드레인 영역(124a 및 124b)에 As를 형성하기 위해 주입 공정을 이용하는 것이 아니라 도펀트 가스로서 AsH3을 사용하는 것을 포함할 수 있다. 여기에 기재된 신규의 제조 방법, 구조 및 설계는 제조 공정 흐름에 쉽게 주입될 수 있다.
소스 영역(124a) 및 드레인 영역(124b)은 적어도 하나의 접촉 저항 낮춤 재료층(120, 120a 및 120b) 및 채널 스트레싱 재료층(122)을 포함하는 다층 구조를 포함한다. 접촉 저항 낮춤 재료층(120a 및 120b)은 SiP, SiAs, 또는 실리사이드를 포함하고, 채널 스트레싱 재료층(122)은 SiCP 또는 SiCAs를 포함한다. 접촉 저항 낮춤 재료층(120a 또는 120b)은 소스 및 드레인 영역(124a 및 124b)의 상부 표면 상에 배치되며, 소스 및 드레인 영역(124a 및 124b)의 접촉 저항을 낮춘다. 또한, 채널 영역(105)에 매우 근접하게 리세스(114)를 형성하는 것은 유리하게도 소스 및 드레인 영역(124a 및 124b)이 채널 영역(105)으로부터 최소한의 간격으로 떨어져 있게 되며, 이는 접촉 저항을 더 감소시킨다.
형성되어진 트랜지스터(126)의 신규의 소스 및 드레인 영역(124a 및 124b)은 일부 실시예에서 핀(104)을 포함하는 채널 영역(105) 및 다른 실시예에서 플래너 작업물(102)의 일부를 포함하는 채널 영역(105')에 대한 낮아진 접촉 저항 및 증가된 스트레스로 인해 개선된 기능을 달성하는 다층 구조를 포함한다. 일부 실시예에서, 높은 이동성을 달성하도록 SiGe 또는 Ⅲ-Ⅴ 화합물 반도체와 같은 재료가 채널 영역(105)에 대하여 사용될 수 있다. 소스 및 드레인 영역(124a 및 124b)의 재료층을 형성하는데 사용되는 저온 성장 공정은 유리하게도 채널 스트레싱 재료층(122)의 스트레스 유도 재료의 완화를 막는다.
본 개시의 실시예는 예를 들어 종종 P 및 As와 같은 n형 불순물을 필요로 하는 n채널 금속 산화물 반도체(NMOS) 트랜지스터의 소스 및 드레인 영역의 형성에 특히 유리할 수 있다. 대안으로서, 여기에 기재된 실시예는 또한 다른 유형의 트랜지스터에 사용될 때 유용하다.
본 개시의 하나의 실시예에 따르면, 반도체 디바이스를 제조하는 방법은, 작업물에 채널 영역을 형성하고, 채널 영역에 근접하게 소스 또는 드레인 영역을 형성하는 것을 포함한다. 소스 또는 드레인 영역은 SiP, SiAs, 또는 실리사이드를 포함하는 접촉 저항 낮춤 재료층을 포함한다. 소스 또는 드레인 영역은 또한 SiCP 또는 SiCAs를 포함하는 채널 스트레싱 재료층을 포함한다.
다른 실시예에 따르면, 반도체 디바이스를 제조하는 방법은, 작업물을 제공하고, 작업물에 채널 영역을 형성하고, 채널 영역 위에 게이트 유전체를 형성하는 것을 포함한다. 방법은 게이트 유전체 위에 게이트를 형성하고, 채널 영역에 근접하게 소스 영역 및 드레인 영역을 형성하는 것을 포함한다. 소스 영역 및 드레인 영역은 SiP, SiAs, 또는 실리사이드를 포함하는 접촉 저항 낮춤 재료층을 포함한다. 소스 영역 및 드레인 영역은 SiCP 또는 SiCAs를 포함하는 채널 스트레싱 재료층을 포함한다.
또 다른 실시예에 따르면, 반도체 디바이스는, 작업물에 배치된 채널 영역, 채널 영역 위에 배치된 게이트 유전체, 게이트 유전체 위에 배치된 게이트, 및 채널 영역에 근접한 소스 영역 및 드레인 영역을 갖는 트랜지스터를 포함한다. 소스 영역 및 드레인 영역은 SiP, SiAs, 또는 실리사이드를 포함하는 접촉 저항 낮춤 재료층 및 SiCP 또는 SiCAs를 포함하는 채널 스트레싱 재료층을 포함한다.
본 개시의 실시예 및 이의 이점이 상세하게 기재되었지만, 첨부된 청구항에 의해 정의되는 본 개시의 진정한 의미 및 범위로부터 벗어나지 않고서 다양한 변경, 치환 및 대안이 여기에 행해질 수 있다는 것을 이해하여야 한다. 예를 들어, 당해 기술 분야에서의 숙련자라면 본 개시의 범위 내에 유지되면서 여기에 기재된 많은 특징, 기능, 공정, 및 재료가 바뀔 수 있다는 것을 쉽게 이해할 것이다. 더욱이, 본 출원의 범위는 명세서에 기재된 공정, 기계, 제조, 물질 조성물, 수단, 방법 및 단계의 특정 실시예에 한정하고자 하는 것이 아니다. 당해 기술 분야에서의 통상의 지식을 가진 자라면 본 개시의 개시로부터 여기에 기재된 대응하는 실시예와 실질적으로 동일한 기능을 수행하거나 실질적으로 동일한 결과를 달성하는, 현재 존재하거나 추후 개발된 공정, 기계, 제조, 물질 조성물, 수단, 방법 또는 단계가 본 개시에 따라 이용될 수 있다는 것을 용이하게 알 수 있을 것이다. 따라서, 첨부된 청구항은 이러한 공정, 기계, 제조, 물질 조성물, 수단, 방법 또는 단계를 본 발명의 범위 내에 포함하고자 한다.
100: 반도체 디바이스 102: 작업물
104: 핀 105: 채널 영역
106: 게이트 유전체 108: 게이트
110: 측벽 스페이서 114: 리세스
120a, 120b: 접촉 저항 낮춤 재료층
122: 채널 스트레싱 재료층
124a, 124b: 소스 및 드레인 영역
126: 트랜지스터
104: 핀 105: 채널 영역
106: 게이트 유전체 108: 게이트
110: 측벽 스페이서 114: 리세스
120a, 120b: 접촉 저항 낮춤 재료층
122: 채널 스트레싱 재료층
124a, 124b: 소스 및 드레인 영역
126: 트랜지스터
Claims (10)
- 반도체 디바이스의 제조 방법에 있어서,
작업물(workpiece)에 채널 영역을 형성하는 단계; 및
상기 채널 영역에 근접하게 소스 또는 드레인 영역을 형성하는 단계
를 포함하고,
상기 소스 또는 드레인 영역은 SiP, SiAs, 또는 실리사이드를 포함하는 접촉 저항 낮춤(contact resistance-lowering) 재료층을 포함하고, 상기 소스 또는 드레인 영역은 SiCP 또는 SiCAs를 포함하는 채널 스트레싱(channel-stressing) 재료층을 포함하고, 상기 접촉 저항 낮춤 재료층 및 상기 채널 스트레싱 재료층은 전구체를 변경함으로써 순차적으로 인시츄(in-situ) 형성되고, 상기 접촉 저항 낮춤 재료층은 상기 채널 스트레싱 재료층 위에 형성되는 것인 반도체 디바이스의 제조 방법. - 삭제
- 청구항 1에 있어서,
상기 소스 또는 드레인 영역을 형성하는 단계는 추가 접촉 저항 낮춤 재료층을 형성하는 단계를 포함하고, 상기 채널 스트레싱 재료층은 상기 추가 접촉 저항 낮춤 재료층 위에 형성되는 것인 반도체 디바이스의 제조 방법. - 청구항 1에 있어서,
상기 채널 영역을 형성하는 단계는 SiGe 또는 Ⅲ-Ⅴ 재료를 형성하는 것을 포함하는 것인 반도체 디바이스의 제조 방법. - 청구항 1에 있어서,
상기 접촉 저항 낮춤 재료층 또는 상기 채널 스트레싱 재료층을 형성하는 것은 주입 공정 또는 어닐링 공정을 포함하지 않는 것인 반도체 디바이스의 제조 방법. - 청구항 1에 있어서,
상기 소스 또는 드레인 영역을 형성하는 단계는 에칭 공정을 사용하여 상기 채널 영역에 근접하게 상기 작업물에 리세스 형성하고(recessing), 상기 리세스에 상기 접촉 저항 낮춤 재료층 및 상기 채널 스트레싱 재료층을 형성하는 것을 포함하는 것인 반도체 디바이스의 제조 방법. - 청구항 1에 있어서,
상기 소스 또는 드레인 영역을 형성하는 단계는 상기 소스 또는 드레인 영역의 가장 넓은 지점에서 상기 채널 영역으로부터 20 nm 이하만큼 떨어져 있는 상기 소스 또는 드레인 영역을 형성하는 것을 포함하는 것인 반도체 디바이스의 제조 방법. - 반도체 디바이스의 제조 방법에 있어서,
작업물을 제공하는 단계;
상기 작업물에 채널 영역을 형성하는 단계;
상기 채널 영역 위에 게이트 유전체를 형성하는 단계;
상기 게이트 유전체 위에 게이트를 형성하는 단계; 및
상기 채널 영역에 근접하게 소스 영역 및 드레인 영역을 형성하는 단계
를 포함하고,
상기 소스 영역 및 상기 드레인 영역은 SiP, SiAs, 또는 실리사이드를 포함하는 접촉 저항 낮춤 재료층을 포함하며, 상기 소스 영역 및 상기 드레인 영역은 SiCP 또는 SiCAs를 포함하는 채널 스트레싱 재료층을 포함하고, 상기 접촉 저항 낮춤 재료층 및 상기 채널 스트레싱 재료층은 전구체를 변경함으로써 순차적으로 인시츄(in-situ) 형성되고, 상기 접촉 저항 낮춤 재료층은 상기 채널 스트레싱 재료층 위에 형성되는 것인 반도체 디바이스의 제조 방법. - 청구항 8에 있어서,
상기 소스 영역 및 상기 드레인 영역을 형성하는 단계는 상기 작업물에 리세스들을 형성하는 것을 포함하며, 상기 방법은,
상기 리세스들의 하부 표면들 상에 제1 라이너를 형성하는 단계; 및
상기 리세스들의 측벽들 상에 제2 라이너를 형성하는 단계
를 더 포함하는 반도체 디바이스의 제조 방법. - 트랜지스터를 포함하는 반도체 디바이스에 있어서,
상기 트랜지스터는,
작업물에 배치된 채널 영역;
상기 채널 영역 위에 배치된 게이트 유전체;
상기 게이트 유전체 위에 배치된 게이트; 및
상기 채널 영역에 근접한 소스 영역 및 드레인 영역
을 포함하고,
상기 소스 영역 및 상기 드레인 영역은,
SiP, SiAs, 또는 실리사이드를 포함하는 접촉 저항 낮춤 재료층; 및
SiCP 또는 SiCAs를 포함하는 채널 스트레싱 재료층
을 포함하고,
상기 접촉 저항 낮춤 재료층 및 상기 채널 스트레싱 재료층은 전구체를 변경함으로써 순차적으로 인시츄(in-situ) 형성되고, 상기 접촉 저항 낮춤 재료층은 상기 채널 스트레싱 재료층 위에 형성되는 것인 반도체 디바이스.
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US8866188B1 (en) | 2014-10-21 |
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