CN103311124A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103311124A
CN103311124A CN2012105869847A CN201210586984A CN103311124A CN 103311124 A CN103311124 A CN 103311124A CN 2012105869847 A CN2012105869847 A CN 2012105869847A CN 201210586984 A CN201210586984 A CN 201210586984A CN 103311124 A CN103311124 A CN 103311124A
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蔡济印
黄耀聪
柯志欣
万幸仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Abstract

公开了半导体器件及其制造方法。在一个实施例中，一种制造半导体器件的方法包括在工件中形成沟道区，以及接近沟道区形成源极或者漏极区。源极或者漏极区包括接触电阻降低材料层，其包含SiP、SiAs或者硅化物。源极或者漏极区还包括沟道应力材料层，其包含SiCP或者SiCAs。

Description

半导体器件及其制造方法
相关申请的交叉参考
本申请涉及以下于2011年7月7日提交的名称为“In-Situ Doping ofArsenic for Source and Drain Epitaxy(用于源极和漏极外延的原位砷掺杂)”的共同待决和普通转让的专利申请序列号13/178,294号，据此将该申请结合于此作为参考。
技术领域
本发明的实施例涉及半导体器件制造，更具体而言，涉及形成晶体管的源极和漏极区。
背景技术
半导体器件用于各种电子应用，举例来说，诸如个人电脑、手机、数码相机以及其他电子设备。通常通过在半导体衬底上方相继沉积绝缘或介电层、导电层和半导体层的材料，并且采用光刻图案化各个材料层以在其上形成电路元件和组件来制造半导体器件。
多栅极场效应晶体管(MuGFET)是半导体技术中的最新发展，其通常是将多于一个栅极结合到单个器件中的金属氧化物半导体FET(MOSFET)。可以通过单个栅电极来控制多个栅极，其中多个栅极表面在电学上充当单个栅极；或者可以通过独立的栅电极来控制多个栅极。MuGFET的一种类型是指FinFET，其是具有从集成电路的硅表面垂直凸出的鳍状半导体沟道的晶体管结构。
发明内容
为了解决上述技术问题，一方面，本发明提供了一种制造半导体器件的方法，所述方法包括：在工件中形成沟道区；以及接近所述沟道区形成源极或者漏极区，其中，所述源极或者漏极区包括接触电阻降低材料层，所述接触电阻降低材料层包含SiP、SiAs或者硅化物，并且其中，所述源极或者漏极区包括沟道应力材料层，所述沟道应力材料层包含SiCP或者SiCAs。
在所述的方法中，形成所述源极或者漏极区包括在所述沟道应力材料层的上方形成所述接触电阻降低材料层。
在所述的方法中，形成所述源极或者漏极区包括在所述接触电阻降低材料层上方形成所述沟道应力材料层。
在所述的方法中，形成所述源极或者漏极区包括在所述接触电阻降低材料层上方形成所述沟道应力材料层，其中，形成所述接触电阻降低材料层包括形成第一接触电阻降低材料层，还包括在所述沟道应力材料层的上方形成第二接触电阻降低材料层。
在所述的方法中，形成所述沟道区包括形成SiGe或者III-V族材料。
在所述的方法中，形成所述接触电阻降低材料层或者所述沟道应力材料层不包括注入工艺或者退火工艺。
在所述的方法中，形成所述源极或者漏极区包括采用蚀刻工艺接近所述沟道区使所述工件凹进，以及在所述凹槽中形成所述接触电阻降低材料层和所述沟道应力材料层。
在所述的方法中，形成所述源极或者漏极区包括采用蚀刻工艺接近所述沟道区使所述工件凹进，以及在所述凹槽中形成所述接触电阻降低材料层和所述沟道应力材料层，其中，所述蚀刻工艺包括各向异性元件。
在所述的方法中，形成所述源极或者漏极区包括形成在所述源极或者漏极区的最宽处与所述沟道区间隔分开了约20nm或者更小距离的源极或者漏极区。
另一方面，本发明提供了一种制造半导体器件的方法，所述方法包括：提供工件；在所述工件中形成沟道区；在所述沟道区的上方形成栅极电介质；在所述栅极电介质的上方形成栅极；以及接近所述沟道区形成源极区和漏极区，所述源极区和所述漏极区包括接触电阻降低材料层，所述接触电阻降低材料层包含SiP、SiAs或者硅化物，并且所述源极区和漏极区包括沟道应力材料层，所述沟道应力材料层包含SiCP或者SiCAs。
在所述的方法中，形成所述半导体器件包括形成鳍式场效应晶体管(FinFET)或者平面晶体管。
在所述的方法中，形成所述源极区和所述漏极区包括在所述工件中形成凹槽，还包括：在所述凹槽的底面上形成第一衬垫；以及在所述凹槽的侧壁上形成第二衬垫。
在所述的方法中，形成所述源极区和所述漏极区包括在所述工件中形成凹槽，还包括：在所述凹槽的底面上形成第一衬垫；以及在所述凹槽的侧壁上形成第二衬垫，其中，形成所述第一衬垫包括形成SiP，并且其中，形成所述第二衬垫包括形成SiAs。
在所述的方法中，形成所述源极区和所述漏极区包括采用AsH3作为掺杂剂气体。
又一方面，本发明提供了一种半导体器件，包括：晶体管，所述晶体管包括：沟道区，设置在工件中；栅极电介质，设置在所述沟道区的上方；栅极，设置在所述栅极电介质的上方；以及源极区和漏极区，接近所述沟道区，所述源极区和所述漏极区包括：接触电阻降低材料层，包含SiP、SiAs或者硅化物；以及沟道应力材料层，包含SiCP或者SiCAs。
在所述的半导体器件中，所述沟道区包括半导体材料鳍片。
在所述的半导体器件中，所述沟道区包括半导体材料鳍片，其中，所述源极区或所述漏极区设置在接近所述半导体材料鳍片的所述工件中的凹槽中。
在所述的半导体器件中，所述沟道区包括半导体材料鳍片，其中，所述源极区或所述漏极区设置在接近所述半导体材料鳍片的所述工件中的凹槽中，其中，所述鳍片包含在所述工件内具有第一尺寸的高度，其中，所述凹槽包含具有第二尺寸的深度，并且其中，所述第二尺寸是所述第一尺寸的约两倍或者更大。
在所述的半导体器件中，所述沟道区包括半导体材料鳍片，其中，所述源极区或所述漏极区设置在接近所述半导体材料鳍片的所述工件中的凹槽中，其中，所述鳍片包含在所述工件内具有第一尺寸的高度，其中，所述凹槽包含具有第二尺寸的深度，并且其中，所述第二尺寸是所述第一尺寸的约两倍或者更大，其中，所述接触电阻降低材料层设置在所述沟道应力材料层的上方，并且其中，所述第二尺寸是所述第一尺寸的约三倍或者更大。
在所述的半导体器件中，所述沟道区包括半导体材料鳍片，其中，所述源极区或所述漏极区设置在接近所述半导体材料鳍片的所述工件中的凹槽中，其中，所述鳍片包含在所述工件内具有第一尺寸的高度，其中，所述凹槽包含具有第二尺寸的深度，并且其中，所述第二尺寸是所述第一尺寸的约两倍或者更大，其中，所述接触电阻降低材料层设置在所述沟道应力材料层的上方，并且其中，所述第二尺寸是所述第一尺寸的约三倍或者更大，其中，所述接触电阻降低材料层和所述沟道应力材料层之间的边界设置成接近所述沟道区的底部。
附图说明
为了更充分地理解本发明及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图4示出根据在FinFET应用中应用的本发明的实施例在各个制造阶段的制造半导体器件的方法的截面图。
图5和图6分别是在FinFET应用中应用的第二实施例和第三实施例的截面图；
图7是在半导体器件上方形成其他材料层之后的图6中示出的实施例截面图；
图8示出在平面晶体管中应用的实施例；以及
图9是根据实施例的制造半导体器件的方法的流程图。
除非另有说明，不同附图中的相应标号和符号通常是指相应部件。绘制附图用于清楚地示出实施例的相关方面且不必按比例绘制。
具体实施方式
在下文详细地论述本发明实施例的制造和使用。然而，应当理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所论述的具体实施例仅仅是制造和使用本发明的示例性具体方式，而不是用于限制本发明的范围。
本发明的实施例涉及半导体器件制造，更具体而言，涉及形成晶体管的源极区和漏极区。在本文将描述用于半导体器件和晶体管的新制造方法及其结构。
图1至图4示出根据在FinFET应用中应用的本发明的实施例制造半导体器件100的方法的截面图。首先参照图1，为了制造器件，提供工件102。在图1至图7示出的实施例中，在工件102中形成多个半导体材料鳍片104。
可以采用于2011年7月7日提交的名称为“In-Situ Doping of Arsenic forSource and Drain Epitaxy(用于源极和漏极外延的原位砷掺杂)”的专利申请序列号13/178,294号(将该申请结合于此作为参考)中所述的方法(参见图1至图4、图5A和图5B、鳍片30以及相关申请中关于其的描述)在工件102中形成鳍片104。在包含鳍片104的沟道区105的上方形成栅极介电材料，在栅极介电材料上方形成栅极材料，并且图案化栅极材料和栅极介电材料以形成栅极108和栅极电介质106，如本发明图1中所示(以及如相关参考文件的图6A和图6B中所示)。在栅极108和栅极电介质106上方形成侧壁间隔件110。注意到，在本发明的图1中示出的视图与相关申请的图6B中示出的视图类似。在工件102中形成浅沟槽隔离(STI)区，但是该STI区在图1的视图中是不可见的；在工件102内与纸间隔开在示出的视图中的纸内外设置STI区。
例如如果采用外延生长工艺形成栅极108的顶部，栅极108的顶部可以窄于底部。包含鳍片104的沟道区105在工件102内的高度具有尺寸d1。尺寸d1可以包含约10nm至50nm，然而可选地，尺寸d1可以包含其他值。如相关申请中所述的，鳍片104可以包含SiGe、硅或者包含III族元素和V族元素的III-V族化合物半导体。III-V族化合物半导体可以包括但不限于：GaAs、InP、GaN、InGaAs、InAlAs、GaSb、AlSb、AlAs、AlP、GaP、其组合以及其多层。可以对鳍片104的材料进行选择以实现例如具有高迁移率(诸如约3000cm2/V-s至40000cm2/V-s)的沟道区105，然而可选地，鳍片104的迁移率可以包含其他值。根据本文中公开的实施例，鳍片104可以可选地包含其他半导体材料。
在附图中仅示出三个晶体管栅极108和鳍片104；但是，根据实施例，在工件102上的整个表面对于例如将在工件102上制造的每个管芯可以形成数十或数百个栅极108和鳍片104(未示出)。
根据实施例，如图2中所示，接近沟道区105，例如在侧壁间隔件110之间使工件102凹进。采用包含各向异性元件的蚀刻工艺112使工件102凹进，从而从侧壁间隔件110的下面去除一部分工件102的材料。在工件102中形成的凹槽114在工件102的顶面内的深度具有尺寸d2。根据本发明的实施例，尺寸d2大于尺寸d1。在一些实施例中，尺寸d2是尺寸d1的约两倍或者更大(例如，参见图2至图4和图5中的实施例)。在其他实施例中，尺寸d2比尺寸d1大了约三倍或者更大(参见图6中的实施例)。
例如，由于蚀刻工艺112的化学过程和/或工件102的晶体结构，凹槽114可以包含所示的基本上不规则四边形的形状。可选地，凹槽114可以包含其他形状，诸如圆形或者椭圆形(参见图8)。根据实施例，对蚀刻工艺112进行选择以实现“接近推向(proximity push)”或者紧密接近于包含鳍片104的沟道区105。凹槽114的最宽部分(在116处示出)可以与鳍片104间隔分开尺寸d3，在一些实施例中尺寸d3可以包含约10nm或者更小的值。尺寸d3可以可选地包含其他值。
接下来，如图3和图4中所示，在凹槽114内形成源极区124a和漏极区124b。根据实施例，形成极为接近于沟道区105的凹槽114有利地导致形成与沟道区105相距最小距离的源极区124a和漏极区124b，该最小距离降低接触电阻。在第一实施例中，首先，如图3中示出，在凹槽114中沉积第一接触电阻降低材料层120a。第一接触电阻降低材料层120a包含通过例如生长工艺(诸如外延生长工艺或者化学汽相工艺(CVD))形成的SiP或者SiAs。第一接触电阻降低材料层120a在沉积时基本上是共形的并且可以包含例如约10nm的厚度。可以采用例如适合在工件102材料上(或者在将在本文中进一步描述的可选衬垫118或者119上)形成，而不适合在侧壁间隔件110上或者在栅极108的顶面上形成的选择性生长或者沉积工艺来形成第一接触电阻降低材料层120a。可选地，第一接触电阻降低材料层120a可以采用其他方法来形成并且可以包含其他尺寸。
在一些实施例中，可以采用低生长温度，使用诸如丙硅烷(Si3H8)、砷化氢(AsH3)的前体和/或其他前体形成第一接触电阻降低材料层120a。第一接触电阻降低材料层120a可以是重掺杂的以实现极低的电阻。例如，第一接触电阻降低材料层120a可以掺杂有掺杂浓度为约1×1020至1×1021的磷、砷或者其他物质以及第一接触电阻降低材料层120a可以具有约0.2至0.4毫欧姆-厘米(milliohm-cm)的电阻。可选地，第一接触电阻降低材料层120a可以用其他量进行掺杂并且可以包含其他电阻值。第一接触电阻降低材料层120a适合于降低接触电阻，例如降低源极区124a和漏极区124b与邻近的元件和组件(诸如工件102和沟道区105)的接触电阻。
在形成第一接触电阻降低材料层120a之前，可以在凹槽114内形成两个可选的薄材料衬垫118和119。衬垫118在本文中也被称为第一衬垫，可以包括在凹槽114的底面上自下向上外延生长的SiP层。衬垫118的形成可以包括例如<001>晶体生长取向。衬垫118可以例如增加源极区124a和漏极区124b与鳍片104的接近程度。衬垫119在本文中也被称为第二衬垫，可以包括在凹槽114的侧壁上的鳍片侧壁生长的SiAs层。衬垫119的形成可以包括例如<110>晶体生长取向。衬垫119可以在鳍片104的侧壁上产生电流分散，增加通过整个鳍片104的电流传输效率。衬垫118和119可以具有例如约2nm至10nm的厚度，然而可选地，衬垫118和119可以包含其他尺寸。衬垫118和119也可以包括在例如本文中参照图5至图8(在附图中未示出)所述的其他实施例中。
接下来，如图4中所示，在第一接触电阻降低材料层120a的上方，在凹槽114中沉积沟道应力(channel-stressing)材料层122。沟道应变材料层122可以包含通过例如生长工艺(诸如外延生长工艺或者化学汽相沉积(CVD)工艺)形成的SiCP或者SiCAs。可以沉积沟道应力材料层122至例如基本上填充凹槽114或者将凹槽114填充至低于工件102的顶面的预定水平面。例如，可以采用以<001>晶体生长取向外延生长SiCP形成沟道应力材料层122。可选地，可以采用其他方法形成沟道应力材料层122并且其可以包含其他尺寸。在一些实施例中，可以采用低生长温度使用诸如丙硅烷(Si3H8)、六氯乙硅烷(HCD：8i2Cl6)、砷化氢(AsH3)、单甲基硅烷(MMS：SiH3CH3)的前体和/或其他前体形成沟道应力材料层122。沟道应力材料层122可以是重掺杂的以实现极低的电阻。例如，沟道应力材料层122可以掺杂有掺杂浓度为约1×1019至1×1021的磷、砷或者其他物质以及沟道应力材料层122可以具有约0.3至0.7毫欧姆-厘米的电阻。可选地，沟道应力材料层122可以用其他量进行掺杂并且可以包含其他电阻值。在一些实施例中，沟道应力材料层122掺杂有C，从而例如诱导沟道区105的拉伸应变。沟道应力材料层122适合于充当应力件，从而例如在包含鳍片104的沟道区105中产生拉伸应力。
然后，也如图4中所示，在位于沟道应力材料层122上方的凹槽114中或者凹槽114上方沉积第二接触电阻降低材料层120b。第二接触电阻降低材料层120b可以包括例如通过与对第一接触电阻降低材料层120a所述的类似方法以及采用类似前体、类似掺杂浓度和类似电阻生长的类似材料。第二接触电阻降低材料层120b的形成可以包括例如适合在沟道应力材料层122上形成但是不适合在侧壁间隔件110上或者在栅极108的顶面上形成的选择性生长或者沉积工艺。可选地，可以采用其他方法形成第二接触电阻降低材料层120b并且其可以包含其他尺寸。第二接触电阻降低材料层120b适合于降低接触电阻，例如降低源极区124a和漏极区124b与邻近的元件和组件(诸如后续形成的接触件(参见图7中的接触件130))的接触电阻。在一些实施例中，第二接触电阻降低材料层120b的顶面可以基本上与工件102的顶面共面，然而可选地，第二接触电阻降低材料层120b的顶面可以低于或者高于工件102的顶面。
因此，在图4中示出的实施例中，形成的晶体管126的新源极区124a和漏极区124b包括多层结构，由于在包含鳍片104的沟道区105上具有更低的接触电阻以及增大的应力而实现改进的功能性。源极区124a和漏极区124b优选设置成紧密接近于沟道区105：在源极区124a和漏极区124b的最宽处，例如，在凹槽114的最宽部分116处，源极区124a和漏极区124b与包含鳍片104的沟道区105间隔分开了约20nm或者更小的距离。
图5示出在FinFET应用中应用的本发明的第二实施例的截面图。在该实施例中，在如第一实施例所述的形成凹槽114之后以及在凹槽114中形成可选的衬垫118和119之后，形成沟道应力材料层122以部分地填充凹槽114，如图5中所示。沟道应力材料层122的形状可以基本上遵循凹槽114的形貌(topography)。在该实施例中，沟道应力材料层122的厚度可以包含约15nm至20nm，然而可选地，沟道应力材料层122可以包含其他尺寸。可以采用例如对第一实施例中的沟道应力材料层122所述的类似的方法、前体、掺杂水平和电阻形成沟道应力材料层122。沟道应力材料层122形成在凹槽114内的工件102的侧壁上和底面上，或者可选地形成在第一实施例中描述的分别位于底面和侧壁上的衬垫118和119的上方。
如图5中所示，然后在沟道应力材料层122上方形成接触电阻降低材料层120。接触电阻降低材料层120可以包含采用对第一实施例中的接触电阻降低材料层120a所述的类似的方法、前体、掺杂水平和电阻形成的类似材料。可选地，作为实例，接触电阻降低材料层120可以包含诸如SiNix的硅化物或者其他硅化物材料。接触电阻降低材料层120降低源极区124a和漏极区124b的接触电阻。
因此，在第二实施例中，沟道应力材料层122基本上是共形的并且直接接触工件102或者直接接触在凹槽114中的工件102的上方形成的衬垫118和119，并且位于源极区124a和漏极区124b顶面上的接触电阻降低材料层120可以包含SiP、SiAs或者硅化物。
图6示出在FinFET应用中应用的本发明的第三实施例的截面图。在该实施例中，首先在凹槽114内形成沟道应力材料层122，其在包含鳍片104的沟道区105中产生拉伸应变。在该实施例中，沟道应力材料层122如在第二实施例中一样不包括共形沉积工艺。然而，在凹槽114的下部采用非共形沉积工艺形成沟道应力材料层122。可以采用例如对第一实施例中的沟道应力材料层122所述的类似的方法、前体、掺杂水平和电阻来形成沟道应力材料层122。然后在沟道应力材料层122的上方形成接触电阻降低材料层120以填充凹槽，如图6中所示。可以采用例如对第一实施例中的第一接触电阻降低材料层120a所述的类似的方法、前体、掺杂水平和电阻来形成接触电阻降低材料层120。
在图6中示出的实施例中的凹槽114可以包括具有尺寸d4的深度，其中尺寸d4比包含鳍片104的沟道区105的高度尺寸d1大了约3倍。在该实施例中，位于接触电阻降低材料层120和沟道应力材料层122之间的边界127可以设置成接近沟道区105的底部。为了增强晶体管126的性能可以优化边界127的位置。例如，边界127可以通过形成更多或更少的沟道应力材料层122在凹槽114中分别向上或者向下移动。
可以控制沟道应力材料层122的形成以实现期望形状的沟道应力材料层122，例如，通过改变沉积工艺的一个或多个参数，例如通过控制沉积工艺的工艺温度、压力、前体的流速、沉积和/或蚀刻元件如图5中所示是共形的或者如图6中所示是非共形的。
在形成本文所述的新源极区124a和漏极区124b之后，继续晶体管126和半导体器件100的制造工艺。例如，图7是在半导体器件100的上方形成其他材料层之后的图6中示出的实施例的截面图。可以在晶体管126以及源极区124a和漏极区124b的上方形成绝缘材料128，其可以包含层间电介质(ILD)或者其他绝缘体。如图所示，可以在绝缘材料128中形成接触件130，其包含导电材料并且与栅极108以及源极区124a和漏极区124b形成电接触。可以在接触件130的上方形成导线132，其与完成的半导体器件100的顶面上的上部材料层(未示出)和接触焊盘(也未示出)形成电连接。
在本文中参照FinFET器件已经描述了本发明的实施例。可选地，如截面图图8所示，可以在平面晶体管中应用本文中描述的实施例。为了制造半导体器件100，在工件102中形成隔离区134，其可以包括STI区或者其他绝缘区。在工件102上方沉积栅极电介质106材料和栅极108材料并且采用光刻对其进行图案化以形成晶体管126的栅极电介质106和栅极108。如图所示，沟道区105′包括位于栅极电介质106下方的一部分平面工件102。如先前实施例所述的，在栅极108和栅极电介质106的侧面上方形成侧壁间隔件110，并且在工件102的顶面中形成凹槽114。凹槽114可以包含具有尺寸d5的深度，尺寸d5例如与沟道区的尺寸d1基本上相同，或者大于尺寸d1。在一些实施例中，在截面图中，凹槽114可以包含圆形或者椭圆形形状；但是，凹槽114可以可选地包含不规则四边形形状。可以用如在图2至图6中示出的第一、第二和第三实施例所述的至少一个接触电阻降低材料层120、120a或者120b以及沟道应力材料层122填充凹槽114。在图8中示出图2至图4中示出的第一实施例的实例，其包括两个接触电阻降低材料层120a和120b。
图9是根据实施例的制造半导体器件100的方法的流程图150。该方法包括提供工件102(步骤152)以及在工件102中形成沟道区105(例如，包含鳍片104)(步骤154)。在沟道区105的上方形成栅极电介质106(步骤156)，以及在栅极电介质108的上方形成栅极108(步骤158)。如本文所述，接近沟道区105形成源极区124a和漏极区124b(步骤160)，其中源极区124a和漏极区124b包括接近沟道区105的接触电阻降低材料层120(或者层120a和层120b)和沟道应力材料层122。
本发明的实施例的优势包括提供用于晶体管126的多层源极区124a和漏极区124b的制造新方法和结构。可以通过改变前体而不是从制造工艺室去除工件102，在原位相继地形成源极区124a和漏极区124b的多层。形成新源极区124a和漏极区124b不需要退火工艺或者注入工艺，并且可以采用低温形成源极区124a和漏极区124b。例如，形成源极区124a和漏极区124b可以包括采用AsH3作用掺杂剂气体而不是利用注入工艺在源极区124a和漏极区124b中形成As。本文中所述的新制造方法、结构和设计在制造工艺流程中是很容易实现的。
源极区124a和漏极区124b包括多层结构，其包括至少一个接触电阻降低材料层120、120a和120b以及沟道应力材料层122。接触电阻降低材料层120a和120b包含SiP、SiAs或者硅化物，并且沟道应力材料层122包含SiCP或者SiCAs。在源极区124a和漏极区124b的顶面上设置接触电阻降低材料层120b或者120，降低源极区124a和漏极区124b的接触电阻。此外，形成极为邻近于沟道区105的凹槽114有利地导致源极区124a和漏极区124b与沟道区105相距最小距离，该最小距离进一步降低接触电阻。
形成的晶体管126的新源极区124a和漏极区124b包括多层结构，其由于在一些实施例中在包含鳍片104的沟道区105以及在其他实施例中在包含部分平面工件102的沟道区105′上具有降低的接触电阻以及增大的应力实现了改进的功能性。在一些实施例中，诸如SiGe或者III-V族化合物半导体的材料可以用于沟道区105以实现高迁移率。用于形成源极区124a和漏极区124b的材料层的低温生长工艺有利地防止沟道应力材料层122的应力引发材料的松弛。
本发明的实施例在例如形成n沟道金属氧化物半导体(NMOS)晶体管的源极和漏极区(其常需要诸如P和As的n型杂质)可能是特别有益的。可选地，用于其他类型的晶体管时，本文所述的实施例也是有用的。
根据本发明的一个实施例，一种制造半导体器件的方法包括在工件中形成沟道区，以及接近沟道区形成源极或漏极区。源极或漏极区包括接触电阻降低材料层，其包含SiP、SiAs或者硅化物。源极或漏极区还包括沟道应力材料层，其包含SiCP或者SiCAs。
根据另一实施例，一种制造半导体器件的方法包括提供工件，在工件中形成沟道区，以及在沟道区的上方形成栅极电介质。该方法包括在栅极电介质上方形成栅极，以及接近沟道区形成源极区和漏极区。源极区和漏极区包括接触电阻降低材料层，其包含SiP、SiAs或者硅化物。源极区和漏极区包括沟道应力材料层，其包含SiCP或者SiCAs。
根据又一实施例，一种半导体器件包括晶体管，该晶体管具有设置在工件中的沟道区、设置在沟道区上方的栅极电介质、设置在栅极电介质上方的栅极、以及接近沟道区的源极区和漏极区。源极区和漏极区包括接触电阻降低材料层，其包含SiP、SiAs或者硅化物；以及沟道应力材料层，其包含SiCP或者SiCAs。
尽管已经详细地描述了本发明的实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变、替换和更改。例如，本领域的技术人员将很容易理解本文中描述的许多部件、功能、工艺和材料可以发生改变并且仍保留在本发明的范围内。此外，本申请的范围并不仅限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的发明内容将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与根据本文所述相应实施例基本上相同的功能或获得基本上相同结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求应该在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种制造半导体器件的方法，所述方法包括：
在工件中形成沟道区；以及
接近所述沟道区形成源极或者漏极区，其中，所述源极或者漏极区包括接触电阻降低材料层，所述接触电阻降低材料层包含SiP、SiAs或者硅化物，并且其中，所述源极或者漏极区包括沟道应力材料层，所述沟道应力材料层包含SiCP或者SiCAs。
2.根据权利要求1所述的方法，其中，形成所述源极或者漏极区包括在所述沟道应力材料层的上方形成所述接触电阻降低材料层。
3.根据权利要求1所述的方法，其中，形成所述源极或者漏极区包括在所述接触电阻降低材料层上方形成所述沟道应力材料层。
4.根据权利要求1所述的方法，其中，形成所述沟道区包括形成SiGe或者III-V族材料。
5.根据权利要求1所述的方法，其中，形成所述接触电阻降低材料层或者所述沟道应力材料层不包括注入工艺或者退火工艺。
6.根据权利要求1所述的方法，其中，形成所述源极或者漏极区包括采用蚀刻工艺接近所述沟道区使所述工件凹进，以及在所述凹槽中形成所述接触电阻降低材料层和所述沟道应力材料层。
7.根据权利要求1所述的方法，其中，形成所述源极或者漏极区包括形成在所述源极或者漏极区的最宽处与所述沟道区间隔分开了约20nm或者更小距离的源极或者漏极区。
8.一种制造半导体器件的方法，所述方法包括：
提供工件；
在所述工件中形成沟道区；
在所述沟道区的上方形成栅极电介质；
在所述栅极电介质的上方形成栅极；以及
接近所述沟道区形成源极区和漏极区，所述源极区和所述漏极区包括接触电阻降低材料层，所述接触电阻降低材料层包含SiP、SiAs或者硅化物，并且所述源极区和漏极区包括沟道应力材料层，所述沟道应力材料层包含SiCP或者SiCAs。
9.根据权利要求8所述的方法，其中，形成所述源极区和所述漏极区包括在所述工件中形成凹槽，还包括：
在所述凹槽的底面上形成第一衬垫；以及
在所述凹槽的侧壁上形成第二衬垫。
10.一种半导体器件，包括：
晶体管，包括：
沟道区，设置在工件中；
栅极电介质，设置在所述沟道区的上方；
栅极，设置在所述栅极电介质的上方；以及
源极区和漏极区，接近所述沟道区，所述源极区和所述漏极区包括：
接触电阻降低材料层，包含SiP、SiAs或者硅化物；以及
沟道应力材料层，包含SiCP或者SiCAs。
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