CN108257954B - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN108257954B CN108257954B CN201710799098.5A CN201710799098A CN108257954B CN 108257954 B CN108257954 B CN 108257954B CN 201710799098 A CN201710799098 A CN 201710799098A CN 108257954 B CN108257954 B CN 108257954B
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Abstract
一种半导体器件包括提供有电子器件的衬底、形成在电子器件上方的层间介电(ILD)层、形成在ILD层上的布线图案和形成在ILD层中并且将布线图案物理地且电连接至电子器件的导电区的接触件。在位于接触件和ILD层之间的接触件的侧壁上提供绝缘衬垫层。从电子器件的导电区的顶部测量的绝缘衬垫层的高度小于在导电区的顶部和界面的水平面之间测量的接触件的高度的90%,该界面位于ILD层和布线图案之间。本发明的实施例还涉及制造半导体器件的方法。
Description
技术领域
本发明涉及一种用于制造半导体器件的方法,更具体地涉及一种位于栅极、源极/漏极区和/或衬底上方的导电层的结构及其制造方法。
背景技术
随着半导体器件的尺寸的减小,在减小例如接触电阻的电阻的同时,导电层之间的分离或绝缘变得更重要。
发明内容
本发明的实施例提供了一种半导体器件,包括:衬底,提供有电子器件;层间介电(ILD)层,形成在所述电子器件上方;布线图案,形成在所述层间介电层上或中;以及接触件,形成在所述层间介电层中并且将所述布线图案物理地且电连接至所述电子器件的导电区;以及绝缘衬垫层,提供在位于所述接触件和所述层间介电层之间的所述接触件的侧壁上,其中,从所述电子器件的所述导电区的顶部测量的所述绝缘衬垫层的高度小于在所述导电区的所述顶部和界面的水平面之间测量的所述接触件的高度的90%,所述界面位于所述层间介电层和所述布线图案之间。
本发明的另一实施例提供了一种半导体器件,包括:衬底,提供有电子器件;层间介电(ILD)层,形成在所述电子器件上方;第一布线图案,形成在所述层间介电层上;第二布线图案,形成在所述层间介电层上;第一接触件,形成在所述层间介电层中并且将所述第一布线图案物理地且电连接至所述电子器件的第一导电区;以及第二接触件,形成在与所述第一接触件相邻的所述层间介电层中并且将所述第二布线图案物理地且电连接至所述电子器件的第二导电区;第一绝缘衬垫层,提供在位于所述第一接触件和所述层间介电层之间的所述第一接触件的侧壁上;以及第二绝缘衬垫层,提供在位于所述第二接触件和所述层间介电层之间的所述第二接触件的侧壁上,其中:从所述电子器件的所述第一导电区的顶部测量的所述第一绝缘衬垫层的高度小于在所述第一导电区的所述顶部和所述层间介电层与所述第一布线图案之间的界面的水平面之间测量的所述第一接触件的高度的90%,以及从所述电子器件的所述第二导电区的顶部测量的所述第二绝缘衬垫层的高度小于在所述第二导电区的所述顶部和所述层间介电层与所述第二布线图案之间的界面的水平面之间测量的所述第二接触件的高度的90%。
本发明的又一实施例提供了一种制造半导体器件的方法,所述方法包括:在提供有电子器件的衬底上方形成层间介电层,从而覆盖所述电子器件;在所述层间介电层中形成接触开口;在所述接触开口中形成绝缘衬垫层;部分地去除形成在所述接触开口中的所述绝缘衬垫层的上部;以及在去除所述绝缘衬垫层的所述上部之后,在所述接触开口中形成导电材料,从而使得所形成的所述导电材料与剩余的所述绝缘衬垫层接触。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1A示出根据本发明的一些实施例的半导体器件的相继的制造工艺的各个阶段中的一个阶段的平面图(从上面观察)。图1B示出沿着图1A的线X1-X1的截面图。图1C是栅极结构的放大图。图1D示出根据本发明的一些实施例的半导体器件的相继的制造工艺的各个阶段中的一个阶段的透视图。
图2示出对应于图1A的线X1-X1的截面图,其中,图1A示出根据本发明的一些实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图3示出对应于图1A的线X1-X1的截面图,其中,图1A示出根据本发明的一些实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图4示出对应于图1A的线X1-X1的截面图,其中,图1A示出根据本发明的一些实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图5示出对应于图1A的线X1-X1的截面图,其中,图1A示出根据本发明的一些实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图6示出对应于图1A的线X1-X1的截面图,其中,图1A示出根据本发明的一些实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图7示出对应于图1A的线X1-X1的截面图,其中,图1A示出根据本发明的一些实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图8示出对应于图1A的线X1-X1的截面图,其中,图1A示出根据本发明的一些实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图9示出根据本发明的一些实施例的截面图。
图10示出根据本发明的其他实施例的截面图。
图11示出根据本发明的其他实施例的截面图。
图12示出根据本发明的其他实施例的截面图。
图13示出根据本发明的其他实施例的截面图。
图14示出根据本发明的其他实施例的截面图。
图15示出根据本发明的其他实施例的截面图。
图16示出根据本发明的其他实施例的截面图。
图17A和17B示出根据本发明的一些实施例的示例性截面图。
图18示出根据本发明的其他实施例的截面图。
图19示出根据本发明的其他实施例的截面图。
图20示出截面图,该截面图示出根据本发明的其他实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图21示出截面图,该截面图示出根据本发明的其他实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图22示出截面图,该截面图示出根据本发明的其他实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。
图23示出根据本发明的其他实施例的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,元件的尺寸不限于所公开的范围或值,但可能依赖于工艺条件和/或器件所需的性能。此外,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。为了简化和清楚,可以以不同的尺寸任意地绘制各个部件。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。另外,术语“由...制成”可以意为“包括”或者“由...组成”。
图1A和图1B示出根据本发明的一些实施例的相继的半导体器件制造工艺的各个阶段中的一个阶段。图1A示出平面(顶视)图,并且图1B示出沿着图1A的线X1-X1的截面图。
图1A和图1B示出在形成源极/漏极和金属栅极结构之后的半导体器件的结构。在图1A和图1B中,分别在沟道层(例如鳍结构5的部分)上方形成金属栅极结构10,且在金属栅极结构10上方设置盖绝缘层20。鳍结构5设置在衬底1上方并且从隔离绝缘层3(例如,浅沟槽隔离(STI))突出。在图1A中,设置三个鳍结构5。然而,鳍结构的数量不限于三个。在图2中并且之后,除非另有明确说明,否则省略衬底1和隔离绝缘层3。
在一些实施例中,金属栅极结构10的厚度在从约10nm至约100nm的范围内。在一些实施例中,盖绝缘层20的厚度在从约10nm至约30nm的范围内,并且在其他实施例中,该厚度在从约15nm至约20nm的范围内。在一些实施例中,不在金属栅极结构10上形成盖绝缘层。
在金属栅极结构10和盖绝缘层20的相对侧壁上提供侧壁间隔件30。在一些实施例中,位于侧壁间隔件的底部处的侧壁间隔件30的膜厚度在从约3nm至约15nm的范围内,并且在其他实施例中,该厚度在从约4nm至约10nm的范围内。金属栅极结构10、盖绝缘层20和侧壁间隔件30的组合可以统称为栅极结构。此外,源极/漏极(S/D)区50形成为与栅极结构相邻,并且在栅极结构和S/D区50上方形成接触蚀刻停止层(CESL)33。在一些实施例中,CESL33的膜厚度在从约1nm至约20nm的范围内。用第一层间介电(ILD)层40填充栅极结构之间的间隔。在一些实施例中,在S/D区50上进一步形成硅化物层55。在本发明中,可互换使用源极和漏极,并且结构上大致没有差异。术语“源极/漏极”(S/D)是指源极和漏极中的一个。此外,将硅化物层55处理为源极和漏极的部分。
硅化物层55包括硅化钴(例如,CoSi、CoSi2、Co2Si、Co3Si;统称为“Co的硅化物”)、硅化钛(例如,Ti5Si3、TiSi、TiSi2、TiSi3、Ti6Si4;统称为“Ti的硅化物”)、硅化镍(例如,Ni3Si、Ni31Si12、Ni2Si、Ni3Si2、NiSi、NiSi2;统称为“Ni的硅化物”)、硅化铜(例如,Cu17Si3、Cu56Si11、Cu5Si、Cu33Si7、Cu4Si、Cu19Si6、Cu3Si、Cu87Si13;统称为“Cu的硅化物”)、硅化钨(W5Si3、WSi2;统称为“W的硅化物”),和硅化钼(Mo3Si、Mo5Si3、MoSi2;统称为“Mo的硅化物”)的一种或多种或任何其他合适的硅化物材料。在其他实施例中,在制造工艺的薄点处不形成硅化物层。
图1C是栅极结构的放大图。金属栅极结构10包括诸如Al、Cu、W、Ti、Ta、TiN、TiAl、TiAlC、TiAlN、TaN、NiSi、CoSi的金属材料或任何其他合适的导电材料的一层或多层16。设置在沟道层5和金属栅极之间的栅极介电层12包括诸如高k金属氧化物的金属氧化物的一层或多层。用于高k电介质的金属氧化物的实例包括Li、Be、Mg、Ca、Sr、Sc、Y、Zr、Hf、Al、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、Yb、Lu的氧化物,和/或它们混合物,或任何其他合适的介电材料。在一些实施例中,在沟道层5和高k栅极介电层12之间形成具有1-3nm厚度的由SiO2制成的界面层。
在一些实施例中,在栅极介电层12和金属材料16之间插接一个或多个功函数调整层14。功函数调整层14由诸如TiN、TaN、TaAlC、TiC、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC的单层或这些材料的两种或多种的多层的导电材料,或任何其他合适的导电材料制成。对于n沟道FET,将TaN、TaAlC、TiN、TiC、Co、TiAl、HfTi、TiSi和TaSi中的一种或多种,或任何其他合适的导电材料用作功函数调整层,并且对于p沟道FET,将TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC和Co中的一种或多种,或者任何其他合适的导电材料用作功函数调整层。
盖绝缘层20包括诸如包括SiN、SiON、SiCN和SiOCN的氮化硅基材料的绝缘材料,或任何其他合适的介电材料的一层或多层。侧壁间隔件30由与盖绝缘层20相同或不同的材料制成,并且包括诸如包括SiN、SiON、SiCN和SiOCN的氮化硅基材料的绝缘材料或任何其他合适的介电材料的一层或多层。CESL 33由与盖绝缘层20和侧壁间隔件30相同或不同的材料制成,并且包括诸如包括SiN、SiON、SiCN和SiOCN的氮化硅基材料的绝缘材料或任何其他合适的介电材料的一层或多层。第一ILD层40包括氧化硅、SiOC、SiOCN或SiCN或其他低k材料,或多孔材料,或任何其他合适的介电材料的一层或多层。可以通过LPCVD(低压化学汽相沉积)、等离子体CVD或其他合适的成膜方法形成第一ILD层40。
CESL 33的材料、侧壁间隔件30的材料、盖绝缘层20的材料以及第一ILD层40的材料可以彼此不同,从而使得可以选择性地蚀刻这些层中的每个。在一个实施例中,CESL 33由SiN制成,侧壁间隔件30由SiOCN、SiCN或SiON制成,盖绝缘层20由SiN或SiON制成,以及第一ILD 40层由SiO2制成。
在该实施例中,采用由栅极替换工艺制造的鳍式场效应晶体管(FinFET)。然而,本文公开的技术可以应用于诸如平面FET、全栅极FET、多栅极FET、电容器、二极管和电阻器的其他电子器件。
图1D示出FinFET结构的透视图。可以通过以下操作来制造Fin FET结构。
首先,在衬底300上方制造鳍结构310。鳍结构包括底部区和作为沟道区315的上部区。例如,衬底是具有在从约1×1015cm-3至约1×1018cm-3的范围内的杂质浓度的p型硅衬底。在其他实施例中,衬底是具有在从约1×1015cm-3至约1×1018cm-3的范围内的杂质浓度的n型硅衬底。可选地,衬底可以包括诸如锗的另一元素半导体;包括诸如SiC和SiGe的IV-IV族化合物半导体,诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP的Ⅲ-V族化合物半导体的化合物半导体,或任何其他合适的半导体材料;或它们的组合。在一个实施例中,衬底是SOI(绝缘体上硅)衬底的硅层。
在形成鳍结构310之后,在鳍结构310上方形成隔离绝缘层320。隔离绝缘层320包括通过LPCVD、等离子体CVD或可流动CVD形成的诸如氧化硅、氮氧化硅或氮化硅的绝缘材料的一层或多层。隔离绝缘层可以由旋涂玻璃(SOG)、SiO2、SiON、SiOCN和/或氟掺杂的硅酸盐玻璃(FSG)或任何其他合适的介电材料的一层或多层形成。
在鳍结构上方形成隔离绝缘层320之后,实施平坦化操作以去除隔离绝缘层320的部分。平坦化操作可以包括化学机械抛光(CMP)和/或回蚀刻工艺。然后,进一步去除(凹进)隔离绝缘层320,从而暴露鳍结构的上部区。
在暴露的鳍结构上方形成伪栅极结构。伪栅极结构包括由多晶硅制成的伪栅电极层和伪栅极介电层。还在伪栅电极层的侧壁上形成包括一层或多层绝缘材料的侧壁间隔件350。在形成伪栅极结构之后,使未被伪栅极结构覆盖的鳍结构310凹进至隔离绝缘层320的上表面下方。然后,通过使用外延生长方法在凹进的鳍结构上方形成源极/漏极区360。源极/漏极区可以包括对沟道区315施加应力的应变材料。
然后,在伪栅极结构和源极/漏极区上方形成层间介电层(ILD)370。ILD层370包括氧化硅、SiOC、SiOCN或SiCN或其他低k材料、或多孔材料、或任何其他合适的介电材料的一层或多层。在平坦化操作之后,去除伪栅极结构,从而制造栅极间隔。然后,在栅极间隔中,形成包括金属栅电极和栅极介电层(诸如高k介电层)的金属栅极结构330。此外,在金属栅极结构330上方形成盖绝缘层340,从而获得图1D所示的FinFET结构。在图1D中,切割金属栅极结构330、盖绝缘层340、侧壁间隔件350和ILD 370的部分以示出下面的结构。在一些实施例中,相邻的源极/漏极外延区360彼此合并,并且在合并的源极/漏极区上形成硅化物层。在其他实施例中,相邻的源极/漏极外延区360彼此不合并,并且在相应的源极/漏极区上形成硅化物层。
图1D中的金属栅极结构330、盖绝缘层340、侧壁间隔件350、源极/漏极360和ILD370大致分别对应于图1A和图1B的金属栅极结构10、盖绝缘层20、侧壁间隔件30、源极/漏极区50和第一层间介电层(ILD)40。
图2至图8示出对应于图1A的线X1-X1的示例性截面图,其中图1A示出根据本发明的一些实施例的半导体器件的相继的制造工艺的各个阶段。应当理解,可以在图2至图8示出的工艺之前、期间和之后提供额外的操作,并且对于该方法的额外的实施例,可以替换或消除下文中描述的一些操作。可互换操作/工艺的顺序。
如图2所示,在图1B的结构上方形成第二ILD层60。材料和形成工艺类似于第一ILD层40的材料和形成工艺。在一些实施例中,在第一ILD层40和第二ILD层60之间形成由例如SiN、SiC或SiCN制成的接触蚀刻停止层(CESL)(未示出)。在一些实施例中,第二ILD层60的厚度在从约10nm至约150nm的范围内。
然后,如图3所示,在第一ILD层和第二ILD层中形成接触开口(孔)60A和60B,以至少部分地暴露S/D区的硅化物层55的上表面。通过使用一个或多个光刻操作和一个或多个蚀刻操作来形成接触开口60A和60B。在蚀刻操作中使用光刻胶图案和/或硬掩模图案。在一些实施例中,所蚀刻的接触开口的宽度W1在从约10nm至约30nm的范围内。
在一些实施例中,蚀刻(例如,干蚀刻)大致不蚀刻ESL层33,并且仅蚀刻第一ILD层和第二ILD层,然后实施额外的蚀刻工艺以去除硅化物层55上的ESL层33。在一些实施例中,接触开口60A和60B具有锥形形状,该锥形形状具有比底部宽度更宽的顶部宽度。
在形成接触开口60A和60B之后,如图4所示,在接触开口中且在第二ILD层60的上表面上共形地形成绝缘衬垫层70。可以通过LPCVD、包括溅射的物理汽相沉积(PVD)或原子层沉积(ALD)形成绝缘衬垫层70。在一些实施例中,绝缘衬垫层70的厚度在从约0.5nm至约10nm的范围内,并且在其他实施例中,该厚度在从约1nm至约5nm的范围内。
绝缘衬垫层70由SiN、SiON、SiCN、SiC、SiOCN或SiOC或任何其他合适的介电材料的一层或多层制成。在一些实施例中,绝缘衬垫层70由与第一ILD层和第二ILD层不同的介电材料制成。可以使用诸如AlO、AlON或AlN的其他介电材料作为绝缘材料层70。在一个实施例中,使用SiN作为绝缘衬垫层。在一些实施例中,通过绝缘衬垫层70覆盖硅化物层55的暴露的上表面。
如图4所示,由于蚀刻第一ILD以形成接触开口并未完全去除两个栅极结构之间的第一ILD,所以第一ILD层40的部分保留在侧壁间隔件30(或侧壁间隔件30上的ESL 33)和绝缘衬垫层70之间。
后续地,如图5所示,通过使用蚀刻操作来部分地去除接触开口中的绝缘衬垫层70的上部。在一些实施例中,去除形成在接触开口中的绝缘衬垫层70的高度的约10%或更多。
还去除形成在第二ILD层60的上表面上的绝缘衬垫层70。在一些实施例中,完全去除形成在第二ILD层60的上表面上的绝缘衬垫层70,并且在其他实施例中,部分地去除形成在第二ILD层60的上表面上的绝缘衬垫层70,并且厚度为约0.1nm至1nm的薄绝缘衬垫层保留在第二ILD层60的上表面上。此外,还去除覆盖硅化物层55的绝缘衬垫层70,从而暴露硅化物层55。
在一些实施例中,蚀刻操作包括使用包括氢(H2)气和一种或多种碳氟化合物气体的源气体的电感耦合等离子体(ICP)。碳氟化合物气体包括CF4、CHF3、CH2F2、CH3F、CH4F6和CH4F8中的一种或多种。在一些实施例中,等离子体蚀刻室中的压力为约3mTorr至约500mTorr。在一些实施例中,RF功率为约10W至约2000W,并且偏置电压为约50V至约600V。等离子体蚀刻可以包括具有不同蚀刻条件的两个或多个步骤。
后续地,如图6所示,在具有剩余的绝缘衬垫层70的接触开口60A和60B中且在第二ILD层60的上表面上形成导电材料层80。
在一些实施例中,导电材料层80包括粘合剂(胶)层和主体金属层的共形形成层。粘合剂层包括一层或多层导电材料。在一些实施例中,粘合剂层包括形成在Ti层上的TiN层。可以使用任何其他合适的导电材料。在一些实施例中,TiN和Ti层的每个的厚度在从约1nm至约5nm的范围内。可以通过CVD、PVD、ALD、电镀或它们的组合或其他合适的成膜方法形成粘合剂层。粘合剂层用于防止主体金属层剥落。在一些实施例中,不使用粘合剂层,并且在接触开口中直接形成主体金属层。在这种情况下,主体金属层直接接触硅化物层55。
主体金属层是Co、W、Mo和Cu中的一种,或任何其他合适的导电材料。在一个实施例中,Cu用作主体金属层。可以通过CVD、PVD、ALD、电镀或它们的组合或其他合适的成膜方法形成主体金属层。
如图7所示,在形成导电材料层80之后,实施诸如化学机械抛光(CMP)或回蚀刻操作的平坦化操作,从而去除沉积在第二ILD层60的上表面上的多余材料,从而形成接触件80A和80B。
后续地,如图8所示,布线图案90A和90B分别形成为与接触件80A和80B接触。布线图案由Co、W、Mo和Cu中的一种或任何其他合适的导电材料制成。在一个实施例中,Cu用作布线图案。在一些实施例中,通过双镶嵌工艺制成接触件和布线图案。布线图案可以包括连接至上导电层的通孔。
在一些实施例中,如图8所示,半导体器件包括具有第一栅极10A、第一源极(共享源极)50S和第一漏极50D1的第一FET(FinFET)FET1和具有第二栅极10B、第二源极(共享源极)50S和第二漏极50D2的第二FET(FinFET)FET2。第一接触件80A与共享源极50S(通过硅化物层55)接触,并且第二接触件80B与第二FET的漏极50D2(通过硅化物层55)接触。在一些实施例中,如图9所示,布线图案90形成为与接触件80A和80B两者接触。
如图8和图9所示,在一些实施例中,从硅化物层55的顶部测量的绝缘衬垫层70的高度H1小于在硅化物层55区域的顶部的水平面和界面的水平面之间测量的接触件80A或80B的高度H2的90%,该界面位于第二ILD层60和布线图案90、90A或90B之间。在其他实施例中,H1小于H2的75%。
绝缘衬垫层70用于在接触件80A、80B和金属栅电极10之间提供更好的隔离。因此,绝缘衬垫层70的顶部位于比金属栅电极10的顶部的水平面更高的位置处。在一些实施例中,绝缘衬垫层70的顶部位于比栅极盖绝缘层20和/或侧壁间隔件30的顶部的水平面更高的位置处。在特定实施例中,绝缘衬垫层70的顶部与栅极、栅极盖绝缘层20和/或侧壁间隔件30的顶部的水平面之间的差异为约5nm或更大。如图8和图9所示,在X(水平)方向上至少通过侧壁间隔件30、CESL 33、第一ILD 40和绝缘衬垫层70分离金属栅电极10和接触件80A。
如图8和图9所示,与第二ILD 60接触的接触件80A和80B的侧壁相对于平行于衬底表面的线在X方向截面上具有锥角θ1。在一些实施例中,锥角θ1等于或大于85度,且小于90度。可以将测量锥角θ1的线确定为沿着接触件的整个侧壁的最匹配的线。
图10至图16示出根据本发明的其他实施例的示例性截面图。在接下来的实施例中使用与先前相对于图1A至图9描述的实施例相同或相似的材料、配置、尺寸和/或工艺,并且可以省略其详细说明。
参考图10,在一些实施例中,在图3描述的接触开口蚀刻中,除了图3的情况之外,去除或大致完全去除接触开口60A、60B周围的第一ILD层40,因此暴露侧壁间隔件30或CESL33。因此,如图10所示,绝缘衬垫层70直接接触暴露的侧壁间隔件30和/或CESL 33,而不插接第一ILD层40的部分。如图10所示,在X(水平)方向上,通过至少侧壁间隔件30、CESL 33和绝缘衬垫层70分离金属栅电极10和接触件80A。
第一接触件80C与共享源极50S(通过硅化物层55)接触并连接至布线图案90A,并且第二接触件80D与第二FET的漏极50D2接触并连接至布线图案90B。在一些实施例中,布线图案90A和90B形成为一个(连接的)布线图案。
在图10中,测量接触件80C和80D的锥角θ2的线可以确定为沿着栅极盖绝缘层20之上的接触件80C和80D的侧壁的最匹配的线。在一些实施例中,锥角θ2等于或大于85度,且小于90度。
参见图11和图12,不像图1A至图10描述的实施例,在图11和图12的实施例中,栅极结构没有栅极盖绝缘层20。
在一些实施例中,绝缘衬垫层70的顶部位于比金属栅电极10和/或侧壁间隔件30的顶部的水平面更高的位置处。在特定实施例中,绝缘衬垫层70的顶部与金属栅电极和/或侧壁间隔件30的顶部的水平面之间的差异为约10nm或更大。在图11中,类似于图9,在X(水平)方向上至少通过侧壁间隔件30、CESL 33、第一ILD 40和绝缘衬垫层70分离金属栅电极10和接触件80A。在图12中,类似于图10,在X(水平)方向上,至少通过侧壁间隔件30、CESL33和绝缘衬垫层70分离金属栅电极10和接触件80D,在金属栅电极10和接触件80D之间没有插接第一ILD层40。
图13示出根据本发明的其他实施例的截面图。在该实施例中,如图13所示,一个接触件80A形成为与一个FET的源极(或漏极)接触,并且一个接触件80E形成为与FET的栅极接触。第一接触件80A与共享源极50S(通过硅化物层55)接触并连接至布线图案90A,并且第二接触件80E与第二FET的栅极10B接触并连接至布线图案90C。在一些实施例中,布线图案90A和90C形成为一个(连接的)布线图案。
在一些实施例中,如图13所示,相对于接触件80E(金属至栅极接触件),从金属栅电极10B的顶部测量的绝缘衬垫层70的高度H3小于在金属栅电极10B的顶部的水平面和界面的水平面之间测量的接触件80E的高度H4的90%,该界面位于第二ILD层60和布线图案90A或90C之间。在其他实施例中,H3小于H4的75%。
图14示出根据本发明的其他实施例的截面图。在该实施例中,如图14所示,一个接触件80E形成为与一个FET FET2的栅极接触,并且一个接触件80F形成为与另一FET FET1的栅极接触。第一接触件80F与栅极10A接触并连接至布线图案90D,并且第二接触件80E与FET2的栅极10B接触并连接至布线图案90C。在一些实施例中,布线图案90D和90C形成为一个(连接的)布线图案。
图15示出根据本发明的其他实施例的截面图。在该实施例中,不形成栅极盖绝缘层。如图15所示,一个接触件80E形成为与一个FET FET2的栅极接触,并且一个接触件80F形成为与另一FET FET1的栅极接触。第一接触件80F与栅极10A接触并连接至布线图案90D,并且第二接触件80E与FET2的栅极10B接触并连接至布线图案90C。在一些实施例中,布线图案90D和90C形成为一个(连接的)布线图案。
如图15所示,在一些实施例中,相对于接触件80F,从金属栅电极10B的顶部测量的绝缘衬垫层70的高度H5小于在金属栅电极10B的顶部的水平面和界面的水平面之间测量的接触件80F的高度H6的90%,该界面位于第二ILD层60和布线图案90C或90D之间。在其他实施例中,H5小于H6的75%。
图16示出根据本发明的另一实施例的截面图。在该实施例中,接触件80G连接布线图案90E和形成在衬底1中的扩散区52。布线图案90E和扩散区52用于为衬底1(例如,FET)提供电势。
如图16所示,在一些实施例中,相对于接触件80G(金属至S/D接触件),从扩散区52的顶部测量的绝缘衬垫层70的高度H7小于在扩散区52的顶部的水平面和界面的水平面之间测量的接触件80G的高度H8的90%,该界面位于第二ILD层60和布线图案90E之间。在其他实施例中,H7小于H8的75%。
图17A和17B示出根据本发明的一些实施例的示例性截面图。
在前述实施例中,绝缘衬垫层70具有从底部至顶部的大致均匀的厚度。在一些实施例中,如图17A所示,绝缘衬垫层70的厚度从底部向顶部逐渐减小。在其他实施例中,如图17B所示,绝缘衬垫层70的厚度从底部至水平面H8大致均匀,并且然后朝向顶部逐渐减小。在特定实施例中,H8为H1的约10%至约80%。
图18示出根据本发明的其他实施例的截面图。
在一些实施例中,由于蚀刻操作以去除绝缘衬垫层70的上部,还蚀刻第二ILD层60,从而使得接触开口60A和60B的上部(见图5)变得更宽。结果,如图18所示,接触件80A具有底部80AB和上部80AU。通过绝缘衬垫层70围绕底部80AB,而不围绕上部80AU。底部80AB的锥角θ3与锥角θ1和θ2大致相同(参见图8和图9)。在一些实施例中,上部80AU的锥角θ4大于锥角θ3,并且是75度或更大且小于88度。
图19示出根据本发明的其他实施例的截面图。
在一些实施例中,由于蚀刻操作去除了绝缘衬垫层70的上部,还蚀刻第二ILD层60,从而使得接触开口60A和60B的上部(见图5)变圆。结果,如图19所示,接触件80A和80B的上部具有漏斗形状。在这种情况下,在接触件80A/80B的底部的水平面和位于两个接触件80A和80B之间的第二ILD层60的最高部分之间测量高度H2。如图8和图9的情况那样,在一些实施例中,从硅化物层55的顶部测量的绝缘衬垫层70的高度H1小于高度H2的90%。在其他实施例中,H1小于H2的75%。
图20至图22示出截面图,该截面图示出根据本发明的其他实施例的相继的半导体器件制造工艺的各个阶段。在接下来的实施例中使用与先前相对于图1A至图19描述的实施例相同或类似的材料、配置、尺寸和/或工艺,并且可以省略其详细说明。
在形成图7所示的结构之后,在第二ILD层和接触件80A和80B上形成第三ILD层110。第三ILD层110的材料和形成工艺类似于第一ILD层40和第二ILD层60的材料和形成工艺。此外,通过使用光刻和蚀刻操作,在接触件80A和80B上方分别形成第二接触开口115A和115B。在一些实施例中,在接触件80A和80B的一个上仅形成一个第二接触开口。如图21所示,后续地,通过使用与相对于4和图5描述的操作类似的操作,在第二接触开口115A和115B中形成第二绝缘衬垫层120。第二绝缘衬垫层120的材料和形成工艺类似于绝缘衬垫层70的材料和形成工艺。然后,如图22所示,通过使用与图6和图8描述的操作类似的操作,形成第二接触件130A和130B以及上部布线图案135A和135B。
在一些实施例中,从接触件80A或80B的顶部测量的第二绝缘衬垫层120的高度H11小于在接触件80A或80B的顶部的水平面和界面的水平面之间测量的接触件130A或130B的高度H12的90%,该界面位于第三ILD层110和上部布线图案135A或135B之间。在其他实施例中,H11小于H12的75%。
图23示出根据本发明的其他实施例的截面图。在接下来的实施例中使用与先前相对于图1A至图122描述的实施例相同或类似的材料、配置、尺寸和/或工艺,并且可以省略其详细说明。
在形成类似于图21的结构之后,形成第二接触件130。然后,通过使用光刻和蚀刻操作,穿过第二ILD层60和第三ILD层110在栅电极10上方形成第三接触开口。如图23所示,通过使用与图4和图5所描述的操作类似的操作,在第三接触开口中形成第三绝缘衬垫层140,并且然后形成导电材料,从而形成第三接触件150。然后,如图23所示,上部布线图案155A和155B形成为与第二接触件130和第三接触件150接触。
在一些实施例中,从接触金属栅极10的顶部测量的第三绝缘衬垫层140的高度H21小于在金属栅极10的顶部的水平面和界面的水平面之间测量的接触件150的高度H12的90%,该界面位于第三ILD层110和布线图案155B之间。在其他实施例中,H21小于H22的75%。在一些实施例中,不在金属栅极10上方设置盖绝缘层20。
本文描述的各个实施例或实例提供优于现有技术的一些优势。例如,通过在接触件中使用额外的绝缘衬垫层,可以改善接触件和栅极或其他导电元件之间的电隔离。此外,通过去除绝缘衬垫层的上部,与不去除绝缘衬垫层的部分的情况相比,由于在接触开口中填充较多的导电材料,从而可以减小接触件的电阻。在一些实施例中,可以将接触件的电阻减小约10-30%。
应当理解,在此不必讨论所有优势,没有特定的优势是所有实施例或实例都必需的,并且其他实施例或实例可提供不同的优势。
根据本发明的一个方面,一种半导体器件包括提供有电子器件的衬底、形成在电子器件上方的层间介电(ILD)层、形成在ILD层上的布线图案和形成在ILD层中并且将布线图案物理地且电连接至电子器件的导电区的接触件。在位于接触件和ILD层之间的接触件的侧壁上提供绝缘衬垫层。从电子器件的导电区的顶部测量的绝缘衬垫层的高度小于在导电区的顶部和界面的水平面之间测量的接触件的高度的90%,该界面位于ILD层和布线图案之间。
在上述半导体器件中,其中,所述绝缘衬垫层由与所述层间介电层不同的材料制成,并且由SiN、SiC、SiOCN、SiCN、SiON和SiOC的一层或多层制成。
在上述半导体器件中,其中,所述电子器件是场效应晶体管(FET),并且所述导电区是所述场效应晶体管的源极或漏极。
在上述半导体器件中,其中,所述电子器件是场效应晶体管(FET),并且所述导电区是所述场效应晶体管的源极或漏极,所述源极和漏极两者包括外延形成的层。
在上述半导体器件中,其中,所述电子器件是场效应晶体管(FET),并且所述导电区是所述场效应晶体管的栅极。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),所述导电区是所述场效应晶体管的源极或漏极,以及所述层间介电层的部分位于设置在所述栅极上的侧壁间隔件和所述绝缘衬垫层之间。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),所述导电区是所述场效应晶体管的源极或漏极,以及所述绝缘衬垫层与设置在所述栅极的侧壁上方的绝缘层接触,而没有所述层间介电层插接在所述绝缘衬垫层和所述绝缘层之间。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),以及所述绝缘衬垫层的顶部位于比所述栅极的导电层的顶部更高的水平面处。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),在所述栅极的顶部上提供绝缘盖层,所述导电区是所述场效应晶体管的所述源极或所述漏极,以及所述层间介电层的部分位于设置在所述栅极上的侧壁间隔件和所述绝缘衬垫层之间。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),在所述栅极的顶部上提供绝缘盖层,所述导电区是所述场效应晶体管的所述源极或所述漏极,以及所述绝缘衬垫层与设置在所述栅极的侧壁和所述绝缘盖层上方的绝缘层接触,而没有所述层间介电层插接在所述绝缘衬垫层和所述绝缘层之间。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),在所述栅极的顶部上提供绝缘盖层,以及所述绝缘衬垫层的顶部位于比所述绝缘盖层的顶部更高的水平面处。
在上述半导体器件中,其中,所述绝缘衬垫层的厚度在从1nm至5nm的范围内。
在上述半导体器件中,其中,所述绝缘衬垫层具有随着与所述导电区的顶部的距离增加而厚度减小的部分。
在上述半导体器件中,其中,所述导电区是用于向所述电子器件提供电势的所述衬底的扩散区。
根据本发明的另一方面,半导体器件包括提供有电子器件的衬底、形成在电子器件上方的层间介电(ILD)层、形成在ILD层上的第一布线图案、形成在ILD层上的第二布线图案、形成在ILD层中并且将第一布线图案物理地且电连接至电子器件的第一导电区的第一接触件以及形成在与第一接触件相邻的ILD层中并且将第二布线图案物理地且电连接至电子器件的第二导电区的第二接触件。在位于接触件和ILD层之间的第一接触件的侧壁上提供第一绝缘衬垫层,在位于接触件和ILD层之间的第二接触件的侧壁上提供第二绝缘衬垫层。从电子器件的第一导电区的顶部测量的第一绝缘衬垫层的高度小于在第一导电区的顶部和界面的水平面之间测量的第一接触件的高度的90%,该界面位于ILD层和第一布线图案之间。从电子器件的第二导电区的顶部测量的第二绝缘衬垫层的高度小于在第二导电区的顶部和界面的水平面之间测量的第二接触件的高度的90%,该界面位于ILD层和第二布线图案之间。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),以及所述第一导电区是所述源级,并且所述第二导电区是所述漏极。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),以及所述第一导电区是所述源极或所述漏极,并且所述第二导电区是所述栅极。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),在所述栅极的顶部上提供绝缘盖层,以及所述第一导电区是所述源级,并且所述第二导电区是所述漏极。
在上述半导体器件中,其中:所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),在所述栅极的顶部上提供绝缘盖层,以及所述第一导电区是所述源极或所述漏极,并且所述第二导电区是所述栅极。
还根据本发明的另一方面,在制造半导体器件的方法中,在提供有电子器件的衬底上方形成层间介电(ILD)层,从而覆盖电子器件。在ILD层中形成接触开口。在接触开口中形成绝缘衬垫层。部分地去除形成在接触开口中的绝缘衬垫层的上部。在去除绝缘衬垫层的上部之后,在开口中形成导电材料,从而使得所形成的导电材料与剩余的绝缘衬垫层接触。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (20)
1.一种半导体器件,包括:
衬底,提供有电子器件;
层间介电(ILD)层,形成在所述电子器件上方;
布线图案,形成在所述层间介电层上或中;以及
接触件,形成在所述层间介电层中并且将所述布线图案物理地且电连接至所述电子器件的导电区;以及
绝缘衬垫层,提供在位于所述接触件和所述层间介电层之间的所述接触件的侧壁上,
其中,从所述电子器件的所述导电区的顶部测量的所述绝缘衬垫层的高度小于在所述导电区的所述顶部和界面的水平面之间测量的所述接触件的高度的90%,所述界面位于所述层间介电层和所述布线图案之间,从所述绝缘衬垫层的顶部至所述界面,所述接触件接触所述层间介电层。
2.根据权利要求1所述的半导体器件,其中,所述绝缘衬垫层由与所述层间介电层不同的材料制成,并且由SiN、SiC、SiOCN、SiCN、SiON和SiOC的一层或多层制成。
3.根据权利要求1所述的半导体器件,其中,所述电子器件是场效应晶体管(FET),并且所述导电区是所述场效应晶体管的源极或漏极。
4.根据权利要求3所述的半导体器件,其中,所述源极和漏极两者包括外延形成的层。
5.根据权利要求1所述的半导体器件,其中,所述电子器件是场效应晶体管(FET),并且所述导电区是所述场效应晶体管的栅极。
6.根据权利要求1所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),
所述导电区是所述场效应晶体管的源极或漏极,以及
所述层间介电层的部分位于设置在所述栅极上的侧壁间隔件和所述绝缘衬垫层之间。
7.根据权利要求1所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),
所述导电区是所述场效应晶体管的源极或漏极,以及
所述绝缘衬垫层与设置在所述栅极的侧壁上方的绝缘层接触或与所述栅极的侧壁接触,而没有所述层间介电层插接在所述绝缘衬垫层和所述绝缘层之间或所述绝缘衬垫层和所述栅极的侧壁之间。
8.根据权利要求1所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),以及
所述绝缘衬垫层的顶部位于比所述栅极的导电层的顶部更高的水平面处。
9.根据权利要求1所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),
在所述栅极的顶部上提供绝缘盖层,
所述导电区是所述场效应晶体管的所述源极或所述漏极,以及
所述层间介电层的部分位于设置在所述栅极上的侧壁间隔件和所述绝缘衬垫层之间。
10.根据权利要求1所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),
在所述栅极的顶部上提供绝缘盖层,
所述导电区是所述场效应晶体管的所述源极或所述漏极,以及
所述绝缘衬垫层与设置在所述栅极的侧壁和所述绝缘盖层上方的绝缘层接触或与所述栅极的侧壁接触,而没有所述层间介电层插接在所述绝缘衬垫层和所述绝缘层之间或所述绝缘衬垫层和所述栅极的侧壁之间。
11.根据权利要求1所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),
在所述栅极的顶部上提供绝缘盖层,以及
所述绝缘衬垫层的顶部位于比所述绝缘盖层的顶部更高的水平面处。
12.根据权利要求1所述的半导体器件,其中,所述绝缘衬垫层的厚度在从1nm至5nm的范围内。
13.根据权利要求1所述的半导体器件,其中,所述绝缘衬垫层具有随着与所述导电区的顶部的距离增加而厚度减小的部分。
14.根据权利要求1所述的半导体器件,其中,所述导电区是用于向所述电子器件提供电势的所述衬底的扩散区。
15.一种半导体器件,包括:
衬底,提供有电子器件;
层间介电(ILD)层,形成在所述电子器件上方;
第一布线图案,形成在所述层间介电层上;
第二布线图案,形成在所述层间介电层上;
第一接触件,形成在所述层间介电层中并且将所述第一布线图案物理地且电连接至所述电子器件的第一导电区;以及
第二接触件,形成在与所述第一接触件相邻的所述层间介电层中并且将所述第二布线图案物理地且电连接至所述电子器件的第二导电区;
第一绝缘衬垫层,提供在位于所述第一接触件和所述层间介电层之间的所述第一接触件的侧壁上;以及
第二绝缘衬垫层,提供在位于所述第二接触件和所述层间介电层之间的所述第二接触件的侧壁上,其中:
从所述电子器件的所述第一导电区的顶部测量的所述第一绝缘衬垫层的高度小于在所述第一导电区的所述顶部和所述层间介电层与所述第一布线图案之间的界面的水平面之间测量的所述第一接触件的高度的90%,从所述第一绝缘衬垫层的顶部至所述层间介电层与所述第一布线图案之间的界面,所述第一接触件接触所述层间介电层,以及
从所述电子器件的所述第二导电区的顶部测量的所述第二绝缘衬垫层的高度小于在所述第二导电区的所述顶部和所述层间介电层与所述第二布线图案之间的界面的水平面之间测量的所述第二接触件的高度的90%,从所述第二绝缘衬垫层的顶部至所述层间介电层与所述第二布线图案之间的界面,所述第二接触件接触所述层间介电层。
16.根据权利要求15所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),以及
所述第一导电区是所述源极,并且所述第二导电区是所述漏极。
17.根据权利要求15所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),以及
所述第一导电区是所述源极或所述漏极,并且所述第二导电区是所述栅极。
18.根据权利要求15所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),
在所述栅极的顶部上提供绝缘盖层,以及
所述第一导电区是所述源极,并且所述第二导电区是所述漏极。
19.根据权利要求15所述的半导体器件,其中:
所述电子器件是具有栅极、源极和漏极的场效应晶体管(FET),
在所述栅极的顶部上提供绝缘盖层,以及
所述第一导电区是所述源极或所述漏极,并且所述第二导电区是所述栅极。
20.一种制造半导体器件的方法,所述方法包括:
在提供有电子器件的衬底上方形成层间介电层,从而覆盖所述电子器件;
在所述层间介电层中形成接触开口;
在所述接触开口中形成绝缘衬垫层;
部分地去除形成在所述接触开口中的所述绝缘衬垫层的上部;以及
在去除所述绝缘衬垫层的所述上部之后,在所述接触开口中形成导电材料,从而使得所形成的所述导电材料与剩余的所述绝缘衬垫层接触,在被去除的所述上部的位置处,所述导电材料接触所述层间介电层。
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