KR100576630B1 - 반도체 집적회로장치의 제조방법 - Google Patents

반도체 집적회로장치의 제조방법 Download PDF

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Publication number
KR100576630B1
KR100576630B1 KR1019990029445A KR19990029445A KR100576630B1 KR 100576630 B1 KR100576630 B1 KR 100576630B1 KR 1019990029445 A KR1019990029445 A KR 1019990029445A KR 19990029445 A KR19990029445 A KR 19990029445A KR 100576630 B1 KR100576630 B1 KR 100576630B1
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South Korea
Prior art keywords
delete delete
cleaning
wafer
integrated circuit
semiconductor integrated
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Expired - Lifetime
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KR1019990029445A
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Korean (ko)
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KR20000011853A (ko
Inventor
오하시나오후미
노구치준지
이마이토시노리
야마구치히즈루
오와다노부오
히노데켄지
혼마요시오
콘도세이치
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가부시키가이샤 히타치세이사쿠쇼
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Application filed by 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가부시키가이샤 히타치세이사쿠쇼
Publication of KR20000011853A publication Critical patent/KR20000011853A/ko
Priority to KR1020040029620A priority Critical patent/KR100683028B1/ko
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Publication of KR100576630B1 publication Critical patent/KR100576630B1/ko
Assigned to 가부시끼가이샤 르네사스 테크놀로지 reassignment 가부시끼가이샤 르네사스 테크놀로지 권리의 전부이전등록 Assignors: 가부시키가이샤 히타치세이사쿠쇼
Assigned to 르네사스 일렉트로닉스 가부시키가이샤 reassignment 르네사스 일렉트로닉스 가부시키가이샤 권리의 전부이전등록 Assignors: 가부시끼가이샤 르네사스 테크놀로지
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/50—Cleaning of wafers, substrates or parts of devices characterised by the part to be cleaned
    • H10P70/56—Cleaning of wafer backside
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/277—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a planarisation of conductive layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
KR1019990029445A 1998-07-24 1999-07-21 반도체 집적회로장치의 제조방법 Expired - Lifetime KR100576630B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020040029620A KR100683028B1 (ko) 1998-07-24 2004-04-28 반도체 집적회로장치의 제조방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10209857A JP2000040679A (ja) 1998-07-24 1998-07-24 半導体集積回路装置の製造方法
JP98-209857 1998-07-24

Related Child Applications (1)

Application Number Title Priority Date Filing Date
KR1020040029620A Division KR100683028B1 (ko) 1998-07-24 2004-04-28 반도체 집적회로장치의 제조방법

Publications (2)

Publication Number Publication Date
KR20000011853A KR20000011853A (ko) 2000-02-25
KR100576630B1 true KR100576630B1 (ko) 2006-05-04

Family

ID=16579782

Family Applications (2)

Application Number Title Priority Date Filing Date
KR1019990029445A Expired - Lifetime KR100576630B1 (ko) 1998-07-24 1999-07-21 반도체 집적회로장치의 제조방법
KR1020040029620A Expired - Lifetime KR100683028B1 (ko) 1998-07-24 2004-04-28 반도체 집적회로장치의 제조방법

Family Applications After (1)

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KR1020040029620A Expired - Lifetime KR100683028B1 (ko) 1998-07-24 2004-04-28 반도체 집적회로장치의 제조방법

Country Status (4)

Country Link
US (8) US6376345B1 (https=)
JP (1) JP2000040679A (https=)
KR (2) KR100576630B1 (https=)
TW (1) TW445534B (https=)

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JP3693847B2 (ja) 1999-03-26 2005-09-14 Ｎｅｃエレクトロニクス株式会社 研磨後ウェハの保管方法および装置
JP2000311876A (ja) * 1999-04-27 2000-11-07 Hitachi Ltd 配線基板の製造方法および製造装置
KR20020019056A (ko) * 1999-06-01 2002-03-09 히가시 데쓰로 반도체 장치의 제조 방법 및 제조 장치
JP4554011B2 (ja) * 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP4513145B2 (ja) * 1999-09-07 2010-07-28 ソニー株式会社 半導体装置の製造方法および研磨方法
EP1093161A1 (en) * 1999-10-12 2001-04-18 Applied Materials, Inc. Method and composite arrangement inhibiting corrosion of a metal layer following chemical mechanical polishing
JP3705724B2 (ja) 1999-11-19 2005-10-12 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
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US6787470B2 (en) * 2002-05-17 2004-09-07 Taiwan Semiconductor Manufacturing Co., Ltd Sacrificial feature for corrosion prevention during CMP
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US8159478B2 (en) * 2004-09-27 2012-04-17 Semiconductor Energy Laboratory Co., Ltd. Display device and electronic device using the same
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US20080233736A1 (en) 2008-09-25
US6800557B2 (en) 2004-10-05
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US6458674B1 (en) 2002-10-01
US20100136786A1 (en) 2010-06-03
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US20040152298A1 (en) 2004-08-05
US7510970B2 (en) 2009-03-31
US20060141792A1 (en) 2006-06-29
US7659201B2 (en) 2010-02-09
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