JPH08264794A - 亜酸化銅等の金属酸化物半導体による薄膜トランジスタとｐｎ接合を形成した金属酸化物半導体装置およびそれらの製造方法 - Google Patents
亜酸化銅等の金属酸化物半導体による薄膜トランジスタとｐｎ接合を形成した金属酸化物半導体装置およびそれらの製造方法Info
- Publication number
- JPH08264794A JPH08264794A JP7068270A JP6827095A JPH08264794A JP H08264794 A JPH08264794 A JP H08264794A JP 7068270 A JP7068270 A JP 7068270A JP 6827095 A JP6827095 A JP 6827095A JP H08264794 A JPH08264794 A JP H08264794A
- Authority
- JP
- Japan
- Prior art keywords
- oxide semiconductor
- metal oxide
- thin film
- metal
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 134
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 103
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 102
- 239000010409 thin film Substances 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- LBJNMUFDOHXDFG-UHFFFAOYSA-N copper;hydrate Chemical compound O.[Cu].[Cu] LBJNMUFDOHXDFG-UHFFFAOYSA-N 0.000 title abstract 2
- 239000010408 film Substances 0.000 claims abstract description 84
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 30
- 239000001301 oxygen Substances 0.000 claims abstract description 30
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 29
- 230000007547 defect Effects 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 239000001257 hydrogen Substances 0.000 claims abstract description 12
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 12
- 230000001590 oxidative effect Effects 0.000 claims abstract description 10
- 239000010949 copper Substances 0.000 claims description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 26
- 229910052802 copper Inorganic materials 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 26
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 7
- 239000011701 zinc Substances 0.000 claims description 7
- 229910052725 zinc Inorganic materials 0.000 claims description 7
- 239000000460 chlorine Substances 0.000 claims description 5
- 229910052801 chlorine Inorganic materials 0.000 claims description 5
- 229910052700 potassium Inorganic materials 0.000 claims description 5
- 229910052708 sodium Inorganic materials 0.000 claims description 5
- 239000011734 sodium Substances 0.000 claims description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 claims description 4
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 229910052744 lithium Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011591 potassium Substances 0.000 claims description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 3
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052711 selenium Inorganic materials 0.000 claims description 2
- 229910052717 sulfur Inorganic materials 0.000 claims description 2
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims 1
- 230000000737 periodic effect Effects 0.000 claims 1
- 239000011669 selenium Substances 0.000 claims 1
- 239000011593 sulfur Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 6
- 230000001681 protective effect Effects 0.000 abstract description 5
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 description 40
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical compound [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 description 40
- 229940112669 cuprous oxide Drugs 0.000 description 40
- 230000003647 oxidation Effects 0.000 description 18
- 238000007254 oxidation reaction Methods 0.000 description 18
- 238000010586 diagram Methods 0.000 description 15
- 239000011521 glass Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000000137 annealing Methods 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 239000008186 active pharmaceutical agent Substances 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- 239000000370 acceptor Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- -1 cuprous oxide Chemical class 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 230000005355 Hall effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
(57)【要約】 （修正有）
【目的】 低温処理により高移動度の金属酸化物半導体
の薄膜トランジスタと、ｐｎ接合を形成した金属酸化物
薄膜半導体装置及びその安価な製造方法を提供する。 【構成】 ガラス基板２１にＡｌ等のゲート電極２２を
形成しＳｉ酸化膜か窒化膜のゲート絶縁膜２３を堆積し
た上に、銅等の金属膜２４，２４′を堆積しパターニン
グしてソース・ドレイン電極を形成する。次にＳｉＮの
絶縁膜２６を全体に堆積し、ガラス基板の裏面から露光
し、ゲート電極パターンをマスクとして絶縁膜２６に開
孔し、ＴＦＴのチャネル部とゲート電極２２を自己整合
させる。次いで２００〜４００℃の低温で熱酸化やプラ
ズマ酸化等により、金属膜２４の露出した一部領域は酸
化して金属酸化物半導体２５に変わる。全体を絶縁膜２
７で被覆し電極取出し部に開孔する。また酸素過剰によ
る欠陥は水素やＬｉ，Ｎａ等の導入でキャリア密度及び
導電型を制御できる。
の薄膜トランジスタと、ｐｎ接合を形成した金属酸化物
薄膜半導体装置及びその安価な製造方法を提供する。 【構成】 ガラス基板２１にＡｌ等のゲート電極２２を
形成しＳｉ酸化膜か窒化膜のゲート絶縁膜２３を堆積し
た上に、銅等の金属膜２４，２４′を堆積しパターニン
グしてソース・ドレイン電極を形成する。次にＳｉＮの
絶縁膜２６を全体に堆積し、ガラス基板の裏面から露光
し、ゲート電極パターンをマスクとして絶縁膜２６に開
孔し、ＴＦＴのチャネル部とゲート電極２２を自己整合
させる。次いで２００〜４００℃の低温で熱酸化やプラ
ズマ酸化等により、金属膜２４の露出した一部領域は酸
化して金属酸化物半導体２５に変わる。全体を絶縁膜２
７で被覆し電極取出し部に開孔する。また酸素過剰によ
る欠陥は水素やＬｉ，Ｎａ等の導入でキャリア密度及び
導電型を制御できる。
Description
【０００１】
【産業上の利用分野】本発明は，亜酸化銅等の金属酸化
物半導体による薄膜トランジスタとｐｎ接合を形成した
金属酸化物半導体装置およびそれらの製造方法に関する
ものである。
物半導体による薄膜トランジスタとｐｎ接合を形成した
金属酸化物半導体装置およびそれらの製造方法に関する
ものである。
【０００２】薄膜トランジスタは液晶ディスプレイ，集
積回路，ファクシミリ制御回路等の半導体エレクトロニ
クスの分野において広く使用されている。本発明は，こ
のような薄膜トランジスタおよびｐｎ接合を有する薄膜
半導体装置を金属酸化物半導体により構成したものであ
る。
積回路，ファクシミリ制御回路等の半導体エレクトロニ
クスの分野において広く使用されている。本発明は，こ
のような薄膜トランジスタおよびｐｎ接合を有する薄膜
半導体装置を金属酸化物半導体により構成したものであ
る。
【０００３】
【従来の技術】液晶ディスプレイ等に使用されるトラン
ジスタは，画素毎に付けられたスイッチング用の薄膜ト
ランジスタと画面全体を制御する高移動度のトランジス
タの２種類のトランジスタを必要とする。従来は，この
ようなトランジスタを得るためにアモルファスシリコン
に形成した画素スイッチ用薄膜トランジスタと単結晶シ
リコンに形成した画面制御用のトランジスタ集積回路を
同一基板に貼り合わせるという方法が取られていた。そ
のため配線が複雑になり，液晶ディスプレイのコストを
押し上げる要因になっていた。
ジスタは，画素毎に付けられたスイッチング用の薄膜ト
ランジスタと画面全体を制御する高移動度のトランジス
タの２種類のトランジスタを必要とする。従来は，この
ようなトランジスタを得るためにアモルファスシリコン
に形成した画素スイッチ用薄膜トランジスタと単結晶シ
リコンに形成した画面制御用のトランジスタ集積回路を
同一基板に貼り合わせるという方法が取られていた。そ
のため配線が複雑になり，液晶ディスプレイのコストを
押し上げる要因になっていた。
【０００４】そこで，画素スイッチ用薄膜トランジスタ
の製造時に，ディスプレイ用のガラス基板に画面制御用
のトランジスタを形成するための様々な方法が開発され
てきた。例えば，レーザ熱処理を用いてポリシリコンを
作り，それを用いて高移動度の薄膜トランジスタを作る
方法等である。しかし，この方法は大面積化に必ずしも
有効ではなく安価なガラス基板を使用して低温で作成で
きる薄膜トランジスタの製造方法の開発が望まれてい
る。
の製造時に，ディスプレイ用のガラス基板に画面制御用
のトランジスタを形成するための様々な方法が開発され
てきた。例えば，レーザ熱処理を用いてポリシリコンを
作り，それを用いて高移動度の薄膜トランジスタを作る
方法等である。しかし，この方法は大面積化に必ずしも
有効ではなく安価なガラス基板を使用して低温で作成で
きる薄膜トランジスタの製造方法の開発が望まれてい
る。
【０００５】
【発明が解決しようとする課題】従来のシリコン半導体
薄膜を使用した薄膜トランジスタは上記のように，安価
なガラス基板を使用して大面積にわたって低温で形成す
ることは困難であった。また，半導体集積回路の微細化
は年々進み，新しい構造のデバイスの開発が必要とされ
ている。
薄膜を使用した薄膜トランジスタは上記のように，安価
なガラス基板を使用して大面積にわたって低温で形成す
ることは困難であった。また，半導体集積回路の微細化
は年々進み，新しい構造のデバイスの開発が必要とされ
ている。
【０００６】本発明は，このような課題を解決すること
のできる新しい構造の金属酸化物半導体による薄膜トラ
ンジスタと金属酸化物半導体にｐｎ接合を形成した薄膜
半導体装置およびそれら製造方法を提供する。そして，
従来はあまり省みられなかった亜酸化銅等の金属酸化物
半導体に新しい観点を見出し，半導体集積回路に新しい
技術をもたらすものである。
のできる新しい構造の金属酸化物半導体による薄膜トラ
ンジスタと金属酸化物半導体にｐｎ接合を形成した薄膜
半導体装置およびそれら製造方法を提供する。そして，
従来はあまり省みられなかった亜酸化銅等の金属酸化物
半導体に新しい観点を見出し，半導体集積回路に新しい
技術をもたらすものである。
【０００７】
【課題を解決するための手段】亜酸化銅，酸化亜鉛，酸
化アルミニム等の金属酸化物が半導体であることは周知
のことである。そして，例えば，亜酸化銅の場合，銅板
をアルゴンと酸素ガスを用いてスパッタすることや，銅
板を単純に熱酸化することなどによって得ることができ
る。金属酸化物半導体は，このように簡単に作れ，か
つ，大面積化も容易であることから太陽電池への応用が
考えられてきたが，亜酸化銅などでは金属酸化物中の過
剰酸素による欠陥の作るアクセプタの密度の制御が少な
くとも従来はできなかったので，ｐｎ接合ができず，そ
のため，亜酸化銅等の金属酸化物半導体は半導体研究の
主流から忘れさられ，半導体装置として実用化をされて
いなかった。
化アルミニム等の金属酸化物が半導体であることは周知
のことである。そして，例えば，亜酸化銅の場合，銅板
をアルゴンと酸素ガスを用いてスパッタすることや，銅
板を単純に熱酸化することなどによって得ることができ
る。金属酸化物半導体は，このように簡単に作れ，か
つ，大面積化も容易であることから太陽電池への応用が
考えられてきたが，亜酸化銅などでは金属酸化物中の過
剰酸素による欠陥の作るアクセプタの密度の制御が少な
くとも従来はできなかったので，ｐｎ接合ができず，そ
のため，亜酸化銅等の金属酸化物半導体は半導体研究の
主流から忘れさられ，半導体装置として実用化をされて
いなかった。
【０００８】ところで，この金属酸化物半導体にも注目
すべき長所があり，亜酸化銅の場合，低温で作成したに
もかかわらずそのキャリヤ移動度は数１０ｃｍ2 ／Ｖｓ
と比較的に大きいものである。さらに，このような金属
酸化物半導体は，金属膜を後から低温酸化しても得るこ
とができる。つまり，金属薄膜の一部を局所的に金属酸
化物半導体に変えることかできる。このことは，亜酸化
銅等の金属酸化物を用いた薄膜トランジスタ等の電子デ
バイスの製作工程を簡略することができるばかりか，新
しい超微細構造のデバイスの製作を容易ならしめるもの
で，シリコン等の金属酸化物半導体以外の半導体を用い
たのでは 実現できないことである。
すべき長所があり，亜酸化銅の場合，低温で作成したに
もかかわらずそのキャリヤ移動度は数１０ｃｍ2 ／Ｖｓ
と比較的に大きいものである。さらに，このような金属
酸化物半導体は，金属膜を後から低温酸化しても得るこ
とができる。つまり，金属薄膜の一部を局所的に金属酸
化物半導体に変えることかできる。このことは，亜酸化
銅等の金属酸化物を用いた薄膜トランジスタ等の電子デ
バイスの製作工程を簡略することができるばかりか，新
しい超微細構造のデバイスの製作を容易ならしめるもの
で，シリコン等の金属酸化物半導体以外の半導体を用い
たのでは 実現できないことである。
【０００９】本発明は，このような金属酸化物半導体に
より薄膜トランジスタを作成するようにした。また，亜
酸化銅等の金属酸化物半導体の一部で知られている過剰
な酸素による欠陥に対して水素等を導入することで欠陥
を制御して，キャリヤ密度および導電型を制御するよう
にし，そのように制御された金属酸化物半導体に対し
て，不純物をドープし良好なｐｎ接合が得られるように
した。さらに逆に酸素が不足することで欠陥が生じてい
る酸化亜鉛等の金属酸化物半導体に対しては酸素，水素
等を導入することにより欠陥を制御して，キャリヤ密度
および導電型を制御するようにし，そのように制御され
た金属酸化物半導体に対して，不純物をドープし良好な
ｐｎ接合が得られるようにした。
より薄膜トランジスタを作成するようにした。また，亜
酸化銅等の金属酸化物半導体の一部で知られている過剰
な酸素による欠陥に対して水素等を導入することで欠陥
を制御して，キャリヤ密度および導電型を制御するよう
にし，そのように制御された金属酸化物半導体に対し
て，不純物をドープし良好なｐｎ接合が得られるように
した。さらに逆に酸素が不足することで欠陥が生じてい
る酸化亜鉛等の金属酸化物半導体に対しては酸素，水素
等を導入することにより欠陥を制御して，キャリヤ密度
および導電型を制御するようにし，そのように制御され
た金属酸化物半導体に対して，不純物をドープし良好な
ｐｎ接合が得られるようにした。
【００１０】図１は本発明の基本構成(1) を薄膜トラン
ジスタをゲート電極を持つ構造の場合について例示的に
示し，その製造方法の原理を説明するものである。図１
(a)， (b)において，１は基板である。
ジスタをゲート電極を持つ構造の場合について例示的に
示し，その製造方法の原理を説明するものである。図１
(a)， (b)において，１は基板である。
【００１１】２は電極金属である。３は絶縁膜である。
４は金属膜であって，銅，亜鉛等の酸化処理をすること
により半導体となるものである。金属膜の膜厚は，例え
ば，０．３μｍ程度であり，酸化処理後は０．６μｍ程
度の薄膜である。
４は金属膜であって，銅，亜鉛等の酸化処理をすること
により半導体となるものである。金属膜の膜厚は，例え
ば，０．３μｍ程度であり，酸化処理後は０．６μｍ程
度の薄膜である。
【００１２】５は金属膜４を酸化処理することにより生
成した金属酸化物半導体である。図１ (a)の構造に対し
て，保護膜（図示せず）を形成して引き出し電極を形成
することにより，例えば電極金属２をゲート電極とする
薄膜トランジスタを作成することができる。
成した金属酸化物半導体である。図１ (a)の構造に対し
て，保護膜（図示せず）を形成して引き出し電極を形成
することにより，例えば電極金属２をゲート電極とする
薄膜トランジスタを作成することができる。
【００１３】図１ (b)は図１ (a)の構造の製造方法を示
す。図示の番号の順に製造方法を説明する。 (1) 絶縁物，シリコン半導体等の基板１に電極金属２
を形成し，絶縁膜３で被覆する。
す。図示の番号の順に製造方法を説明する。 (1) 絶縁物，シリコン半導体等の基板１に電極金属２
を形成し，絶縁膜３で被覆する。
【００１４】(2) 絶縁膜３の上に，例えば，銅，亜鉛
等の金属膜４を形成する。 (3) 金属膜４の一部の領域をイオン注入，熱酸化，プ
ラズマ酸化等で酸化処理する。
等の金属膜４を形成する。 (3) 金属膜４の一部の領域をイオン注入，熱酸化，プ
ラズマ酸化等で酸化処理する。
【００１５】さらに，必要ならば，金属酸化物半導体領
域に対して，水素を導入する等で金属酸化物半導体の過
剰な酸素による欠陥を制御して，キャリヤ密度および導
電型を制御するようにする。あるいは，酸素が不足した
ことにより欠陥を生じている場合には，酸素もしくは水
素等を導入することにより欠陥を制御して，キャリヤ密
度および導電型を制御するようにする。
域に対して，水素を導入する等で金属酸化物半導体の過
剰な酸素による欠陥を制御して，キャリヤ密度および導
電型を制御するようにする。あるいは，酸素が不足した
ことにより欠陥を生じている場合には，酸素もしくは水
素等を導入することにより欠陥を制御して，キャリヤ密
度および導電型を制御するようにする。
【００１６】図２は本発明の基本構成(2) であり，ｐｎ
接合を持つ金属酸化物半導体についての原理的構造と製
造方法を説明するものである。図２ (a)は原理的構造で
あり，図２ (b)はその製造方法の原理を示す。
接合を持つ金属酸化物半導体についての原理的構造と製
造方法を説明するものである。図２ (a)は原理的構造で
あり，図２ (b)はその製造方法の原理を示す。
【００１７】図２ (a)において，１１は基板である１３
は金属酸化物半導体であって，第１の導電型の半導体で
ある。
は金属酸化物半導体であって，第１の導電型の半導体で
ある。
【００１８】１５は接合部である。１６は金属酸化物半
導体であって，第２の導電型の半導体である。図２ (a)
に対して，保護膜，電極を形成することによりダイオー
ドとし，あるいは接合の数を増やしてトランジスタとす
る等で半導体装置とすることができる。
導体であって，第２の導電型の半導体である。図２ (a)
に対して，保護膜，電極を形成することによりダイオー
ドとし，あるいは接合の数を増やしてトランジスタとす
る等で半導体装置とすることができる。
【００１９】図２ (b)は図２ (a)の原理的構造の製造方
法である。図２(b) において，１１は基板である。
法である。図２(b) において，１１は基板である。
【００２０】１２は金属膜であって，銅，亜鉛等の酸化
処理することにより半導体となるものである。１３は金
属酸化物半導体（第１の導電体）である。
処理することにより半導体となるものである。１３は金
属酸化物半導体（第１の導電体）である。
【００２１】１４は真性半導体化領域であって，金属酸
化物半導体１３に水素等を照射し，金属酸化物半導体
（第１の導電体）１３の過剰な酸素に対して欠陥を除去
し，真性半導体化した領域である。あるいは酸素が不足
して欠陥を生じている場合には酸素もしくは水素等を導
入して欠陥を除去し，真性半導体化したものである。
化物半導体１３に水素等を照射し，金属酸化物半導体
（第１の導電体）１３の過剰な酸素に対して欠陥を除去
し，真性半導体化した領域である。あるいは酸素が不足
して欠陥を生じている場合には酸素もしくは水素等を導
入して欠陥を除去し，真性半導体化したものである。
【００２２】１５は接合部である。１６は第２の導電型
の金属酸化物半導体であって，真性半導体化領域１４に
第２導電型とする不純物（例えば，塩素等）をドープし
た金属酸化物半導体装置である。
の金属酸化物半導体であって，真性半導体化領域１４に
第２導電型とする不純物（例えば，塩素等）をドープし
た金属酸化物半導体装置である。
【００２３】図２ (b)により，図２ (a)の薄膜半導体装
置の製造方法について説明する。 (1) 基板１１に金属膜１２を形成する（例えば，厚さ
０．３μｍ）。 (2) 金属膜１２を酸化処理し，第１の導電体型の金属
酸化物半導体１３とする。
置の製造方法について説明する。 (1) 基板１１に金属膜１２を形成する（例えば，厚さ
０．３μｍ）。 (2) 金属膜１２を酸化処理し，第１の導電体型の金属
酸化物半導体１３とする。
【００２４】(3) 金属酸化物半導体１３の酸素の過不
足による欠陥を除去する等で真性半導体化する。 (4) 真性半導体化領域１４に第２の導電型の不純物を
ドープし，第１の導電型の金属酸化物半導体１３とｐｎ
接合を形成する。
足による欠陥を除去する等で真性半導体化する。 (4) 真性半導体化領域１４に第２の導電型の不純物を
ドープし，第１の導電型の金属酸化物半導体１３とｐｎ
接合を形成する。
【００２５】
【作用】本発明によれば，低温処理により高移動度の薄
膜トランジスタおよびｐｎ接合を持つ金属酸化物薄膜半
導体を低コストで製造することができる。また，後述す
るが，金属化酸化物半導体は高温の熱処理にも耐えると
ともに高温アニールにより移動度も高くなるので，高温
熱処理する集積回路技術に対しても新しい適用を可能と
するものである。
膜トランジスタおよびｐｎ接合を持つ金属酸化物薄膜半
導体を低コストで製造することができる。また，後述す
るが，金属化酸化物半導体は高温の熱処理にも耐えると
ともに高温アニールにより移動度も高くなるので，高温
熱処理する集積回路技術に対しても新しい適用を可能と
するものである。
【００２６】なお，図１の本発明の基本構成(1) では，
ゲート電極を持つ構造の薄膜トランジスタについて説明
したが，メタルベーストランジスタ等の他の構造の薄膜
トランジスタに対しても適用できるものである。また，
図１の本発明の基本構成によれば金属酸化物半導体の幅
をトンネル電流が流れる程度にすることができるので，
この点からも本発明によれば，微小電流で高速動作する
新しい集積回路技術を切り開くことができるものであ
る。
ゲート電極を持つ構造の薄膜トランジスタについて説明
したが，メタルベーストランジスタ等の他の構造の薄膜
トランジスタに対しても適用できるものである。また，
図１の本発明の基本構成によれば金属酸化物半導体の幅
をトンネル電流が流れる程度にすることができるので，
この点からも本発明によれば，微小電流で高速動作する
新しい集積回路技術を切り開くことができるものであ
る。
【００２７】
【実施例】本発明の金属酸化物半導体として亜酸化銅を
使用する場合について実施例を説明する。
使用する場合について実施例を説明する。
【００２８】図３は本発明で使用する酸化物半導体の特
性の例を示す図である。図３は，アルゴン中で，銅薄膜
を室温でスパッタ法により堆積した後，その銅薄膜を２
５０°Ｃ前後の温度で熱酸化して得られた亜酸化銅半導
体のキャリヤ密度をホール効果により求まる移動度の関
係を実測した結果を示したものである。
性の例を示す図である。図３は，アルゴン中で，銅薄膜
を室温でスパッタ法により堆積した後，その銅薄膜を２
５０°Ｃ前後の温度で熱酸化して得られた亜酸化銅半導
体のキャリヤ密度をホール効果により求まる移動度の関
係を実測した結果を示したものである。
【００２９】この時，亜酸化銅の極性は，ｐ型である。
キャリヤ密度は１０16ｃｍ-3以下と小さく，移動度は数
１０ｃｍ2 ／Ｖ・ｓである。このキャリヤは過剰酸素に
よる欠陥が作るアクセプタから供給されているものであ
るが，この方法で作られた亜酸化銅のキャリヤ密度は低
いので，酸素に作用して過剰酸素の欠陥を除去できる水
素，ナトリウム，カリウム，銅，亜鉛などを１０11から
１０12ｃｍ-2ほどイオン注入することで容易にキャリヤ
密度の制御が可能である。イオン注入のドープ量がこの
ように低いので，イオン注入によって発生する欠陥も少
なく抑えることができ，４００°Ｃ程度の以下の低温の
熱処理でも，十分にイオン注入による欠陥を除去するこ
とができる。
キャリヤ密度は１０16ｃｍ-3以下と小さく，移動度は数
１０ｃｍ2 ／Ｖ・ｓである。このキャリヤは過剰酸素に
よる欠陥が作るアクセプタから供給されているものであ
るが，この方法で作られた亜酸化銅のキャリヤ密度は低
いので，酸素に作用して過剰酸素の欠陥を除去できる水
素，ナトリウム，カリウム，銅，亜鉛などを１０11から
１０12ｃｍ-2ほどイオン注入することで容易にキャリヤ
密度の制御が可能である。イオン注入のドープ量がこの
ように低いので，イオン注入によって発生する欠陥も少
なく抑えることができ，４００°Ｃ程度の以下の低温の
熱処理でも，十分にイオン注入による欠陥を除去するこ
とができる。
【００３０】本発明は，このような亜酸化銅等の酸化物
半導体の持つ性質に着目し，これを用いて低温で薄膜ト
ランジスタを製造するようにしたものである。なお，本
発明は，亜酸化銅のみならず，酸化亜鉛，酸化アルミニ
ウム，酸化タンタル等の他の金属酸化物半導体に対して
も適用できるものである。
半導体の持つ性質に着目し，これを用いて低温で薄膜ト
ランジスタを製造するようにしたものである。なお，本
発明は，亜酸化銅のみならず，酸化亜鉛，酸化アルミニ
ウム，酸化タンタル等の他の金属酸化物半導体に対して
も適用できるものである。
【００３１】図４は本発明の実施例１であって，薄膜ト
ランジスタである。図４において，２１はガラス基板で
ある（図１ (a)の基板１に相当する）。
ランジスタである。図４において，２１はガラス基板で
ある（図１ (a)の基板１に相当する）。
【００３２】２２はゲート電極である（図１ (a)の電極
金属２に相当する）。２３はゲート絶縁膜である（図１
(a)の絶縁膜３に相当する）。２４，２４’は金属膜で
あって，ソース，ドレイン電極である。
金属２に相当する）。２３はゲート絶縁膜である（図１
(a)の絶縁膜３に相当する）。２４，２４’は金属膜で
あって，ソース，ドレイン電極である。
【００３３】２５は金属酸化物半導体であって，金属膜
２４，２４’を酸化処理して得られた金属半導体であ
る。２６は絶縁膜である。
２４，２４’を酸化処理して得られた金属半導体であ
る。２６は絶縁膜である。
【００３４】図４において，絶縁膜２６，金属酸化物半
導体２５の表面にさらに絶縁保護膜（図５工程(6) 参
照）を形成し，ソース，ドレイン電極２４，２４’に接
続する電極を引き出すことによりゲート電極２２を持つ
薄膜トランジスタとする。
導体２５の表面にさらに絶縁保護膜（図５工程(6) 参
照）を形成し，ソース，ドレイン電極２４，２４’に接
続する電極を引き出すことによりゲート電極２２を持つ
薄膜トランジスタとする。
【００３５】図５は図４の薄膜トランジスタの製造方法
を示す。 工程(1) ガラス基板２１にクロムあるいはアルミニュ
ーム等の金属を堆積し，それをフォトレジスト加工によ
り，ゲート電極となるように成型する。この工程で，ま
ず，第１のパターンマスクを用いる。また，本発明で
は，全て低温度で処理するのでここに使用するガラスは
高価格の高融点ガラスである必要はない。
を示す。 工程(1) ガラス基板２１にクロムあるいはアルミニュ
ーム等の金属を堆積し，それをフォトレジスト加工によ
り，ゲート電極となるように成型する。この工程で，ま
ず，第１のパターンマスクを用いる。また，本発明で
は，全て低温度で処理するのでここに使用するガラスは
高価格の高融点ガラスである必要はない。
【００３６】工程(2) 全体にシリコン酸化膜あるいは
シリコン窒化膜等のゲート絶縁膜を堆積する。 工程(3) 銅等の金属酸化物半導体となる薄膜の金属膜
２４，２４’を堆積し，フォトレジスト加工により，ソ
ース，ドレイン部を含めたトランジスタのパターン，お
よびソース，ドレインからの接続配線部のパターン（図
示せず）も含めて成型する。この時，第２のパターンマ
スクを用いる。
シリコン窒化膜等のゲート絶縁膜を堆積する。 工程(3) 銅等の金属酸化物半導体となる薄膜の金属膜
２４，２４’を堆積し，フォトレジスト加工により，ソ
ース，ドレイン部を含めたトランジスタのパターン，お
よびソース，ドレインからの接続配線部のパターン（図
示せず）も含めて成型する。この時，第２のパターンマ
スクを用いる。
【００３７】工程(4) 次の酸化工程のマスクとなる
膜，例えばシリコン窒化膜などを全体に堆積する。この
時，フォトレジスト膜を用いることもできる。そして，
これらの膜を堆積した後に，ガラス基板２１の裏面より
露光し，工程(1) で作成したゲート電極のパターンをマ
スクとしてフォトレジスト膜を露光し，その膜にフォト
レジスト加工により孔を開ける。この工程で，薄膜トラ
ンジスタのチャネル部とゲート電極２２を自己整合させ
る。
膜，例えばシリコン窒化膜などを全体に堆積する。この
時，フォトレジスト膜を用いることもできる。そして，
これらの膜を堆積した後に，ガラス基板２１の裏面より
露光し，工程(1) で作成したゲート電極のパターンをマ
スクとしてフォトレジスト膜を露光し，その膜にフォト
レジスト加工により孔を開ける。この工程で，薄膜トラ
ンジスタのチャネル部とゲート電極２２を自己整合させ
る。
【００３８】工程(5) では，２００°Ｃから４００°Ｃ
程度の間の低温で全体を熱酸化，もしくはプラズマ酸化
などをすることにより，開口から露出した金属膜２４を
酸化し，金属酸化物半導体に変化させる（工程(4) で絶
縁膜２６には孔を開けられている）。
程度の間の低温で全体を熱酸化，もしくはプラズマ酸化
などをすることにより，開口から露出した金属膜２４を
酸化し，金属酸化物半導体に変化させる（工程(4) で絶
縁膜２６には孔を開けられている）。
【００３９】工程(6) 形成されたトランジスタの全体
をシリコン窒化膜等の絶縁膜で被覆し，かつフォトレジ
スト加工により電極取り出し部に孔を開ける。この時，
第３のマスクパターンを用いる。
をシリコン窒化膜等の絶縁膜で被覆し，かつフォトレジ
スト加工により電極取り出し部に孔を開ける。この時，
第３のマスクパターンを用いる。
【００４０】上記のように，本実施例によればマスクパ
ターンを３枚で薄膜トランジスタを製造することができ
る。なお，上記の工程において，工程(5) の金属膜の酸
化は，酸素イオン注入の他，熱酸化，プラズマ酸化，酸
素イオン照射，レーザ 酸素ドーピング等の手段により
行うことができる。
ターンを３枚で薄膜トランジスタを製造することができ
る。なお，上記の工程において，工程(5) の金属膜の酸
化は，酸素イオン注入の他，熱酸化，プラズマ酸化，酸
素イオン照射，レーザ 酸素ドーピング等の手段により
行うことができる。
【００４１】また，酸素欠陥を除去することによりキャ
リヤ密度，導電型を制御したり，あるいは不純物ドーピ
ングによりｐ，ｎ型の導電型の制御，抵抗率等の制御を
する必要がある場合には，工程（５）と工程（６）の間
で，イオン注入法，イオンドーピング法，熱拡散法，プ
ラズマ熱酸化法，あるいはレーザドーピング法等の手段
で行うことができる。
リヤ密度，導電型を制御したり，あるいは不純物ドーピ
ングによりｐ，ｎ型の導電型の制御，抵抗率等の制御を
する必要がある場合には，工程（５）と工程（６）の間
で，イオン注入法，イオンドーピング法，熱拡散法，プ
ラズマ熱酸化法，あるいはレーザドーピング法等の手段
で行うことができる。
【００４２】このとき，酸素過剰による欠陥（亜酸化銅
の場合）を補償する目的で水素，リチウム，ナトリウ
ム，カリウム，銅，インジウム，亜鉛等の１種もしくは
複数種の不純物を金属酸化物半導体に導入し，その導体
のキャリヤ密度および導電型を制御することができる。
酸素を照射した場合には欠陥が増え抵抗を増加させる。
の場合）を補償する目的で水素，リチウム，ナトリウ
ム，カリウム，銅，インジウム，亜鉛等の１種もしくは
複数種の不純物を金属酸化物半導体に導入し，その導体
のキャリヤ密度および導電型を制御することができる。
酸素を照射した場合には欠陥が増え抵抗を増加させる。
【００４３】さらに，上記のようにキャリヤ密度および
導電型が制御された金属酸化物半導体に弗素，塩素，リ
ン，砒素，アンチモン等の元素を導入することで導電型
を制御することもできる。
導電型が制御された金属酸化物半導体に弗素，塩素，リ
ン，砒素，アンチモン等の元素を導入することで導電型
を制御することもできる。
【００４４】図６は本実施例１の方法で作成された薄膜
トランジスタの特性の例である。図６の特性の薄膜トラ
ンジスタは次のようなものである。金属酸化物半導体は
亜酸化銅である。ゲート絶縁膜はシリコン酸化膜であ
り，ゲート電極は低抵抗の結晶シリコンである。
トランジスタの特性の例である。図６の特性の薄膜トラ
ンジスタは次のようなものである。金属酸化物半導体は
亜酸化銅である。ゲート絶縁膜はシリコン酸化膜であ
り，ゲート電極は低抵抗の結晶シリコンである。
【００４５】亜酸化銅は，銅薄膜を室温でアルゴンガス
を用いたスパッタ法により約８０秒ほどの時間で堆積し
た銅薄膜を３５０°Ｃで約１８分間，熱酸化することに
より作られている。この薄膜トランジスタにおいては，
チャネル長Ｌ＝５０μｍ，チャネル幅１７５μｍであ
る。図６は薄膜トランジスタのソース・ドレイン間電流
ＩDSの平方根をゲート・ソース間電圧ＶGSの関数として
その特性を示している。この傾きから移動度を求めるこ
とができる。図６の例は移動度が約１００ｃｍ2／Ｖｓ
である。
を用いたスパッタ法により約８０秒ほどの時間で堆積し
た銅薄膜を３５０°Ｃで約１８分間，熱酸化することに
より作られている。この薄膜トランジスタにおいては，
チャネル長Ｌ＝５０μｍ，チャネル幅１７５μｍであ
る。図６は薄膜トランジスタのソース・ドレイン間電流
ＩDSの平方根をゲート・ソース間電圧ＶGSの関数として
その特性を示している。この傾きから移動度を求めるこ
とができる。図６の例は移動度が約１００ｃｍ2／Ｖｓ
である。
【００４６】本発明によれば，移動度が数１０ｃｍ2 ／
Ｖｓから１００ｃｍ2 ／Ｖｓ近くまでの大きなものが得
られる。図７は本発明の実施例２であり，メタルベース
トランジスタに本発明を適用したものである。
Ｖｓから１００ｃｍ2 ／Ｖｓ近くまでの大きなものが得
られる。図７は本発明の実施例２であり，メタルベース
トランジスタに本発明を適用したものである。
【００４７】図７ (a)はメタルベーストランジスタの構
造であり，図７ (b)，図７ (c)はその製造方法を説明す
るものである。図７ (a)において，３０は基板である。
造であり，図７ (b)，図７ (c)はその製造方法を説明す
るものである。図７ (a)において，３０は基板である。
【００４８】３０’は金属膜（亜酸化銅）である。３１
は金属酸化物半導体であって，亜酸化銅（ｐ型）であり
エミッタである。３２は金属ベースであって，銅である
（厚さ約１０Å〜５０Å）。
は金属酸化物半導体であって，亜酸化銅（ｐ型）であり
エミッタである。３２は金属ベースであって，銅である
（厚さ約１０Å〜５０Å）。
【００４９】３３は金属酸化物半導体であって，亜酸化
銅（ｐ型）でありコレクタである。図７ (a)において，
電極配線は図示を省略されている。図７ (b)により，図
７ (a)のメタルベーストランジスタの製造方法を説明す
る。金属膜として銅を使用するものとする。 (1) 基板（ガラス，石英，シリコン等）３０に銅を厚
さ約０．３μｍ程度にスパッタ法により形成する。
銅（ｐ型）でありコレクタである。図７ (a)において，
電極配線は図示を省略されている。図７ (b)により，図
７ (a)のメタルベーストランジスタの製造方法を説明す
る。金属膜として銅を使用するものとする。 (1) 基板（ガラス，石英，シリコン等）３０に銅を厚
さ約０．３μｍ程度にスパッタ法により形成する。
【００５０】(2) 電気炉中で銅３０”の表面を熱酸化
し，厚さ０．１μｍだけ銅３０”を消費して約０．２μ
ｍの厚さの亜酸化銅の膜３１’を形成する。このとき，
２５０°Ｃで約１５分ぐらい乾燥酸素中で熱酸化する。
し，厚さ０．１μｍだけ銅３０”を消費して約０．２μ
ｍの厚さの亜酸化銅の膜３１’を形成する。このとき，
２５０°Ｃで約１５分ぐらい乾燥酸素中で熱酸化する。
【００５１】(3) これに再度，銅を室温で堆積する。
膜厚は約０．１μｍである。 (4) 再び，電気炉中で，新たに堆積した銅の表面のう
ちのほとんど全ての部分を熱酸化して亜酸化銅に変え
る。このとき，酸化時間を微妙に制御して極く薄い銅の
膜３２’（厚さ０．００１〜０．００５μｍ）を残して
メタルベーストランジスタのベースとする。この時の熱
酸化条件は，２００°Ｃ，１６０分前後である。
膜厚は約０．１μｍである。 (4) 再び，電気炉中で，新たに堆積した銅の表面のう
ちのほとんど全ての部分を熱酸化して亜酸化銅に変え
る。このとき，酸化時間を微妙に制御して極く薄い銅の
膜３２’（厚さ０．００１〜０．００５μｍ）を残して
メタルベーストランジスタのベースとする。この時の熱
酸化条件は，２００°Ｃ，１６０分前後である。
【００５２】図７ (b)における酸化の過程において，図
７ (c)(2) に示すように，亜酸化銅３３’の表面を窒化
シリコン膜で被覆すると，図７ (c)(3) のようにベース
電極の取り出し口を容易にすることができる。
７ (c)(2) に示すように，亜酸化銅３３’の表面を窒化
シリコン膜で被覆すると，図７ (c)(3) のようにベース
電極の取り出し口を容易にすることができる。
【００５３】図８は本発明の実施例３である。図８は，
ゲート電極を備える薄膜トランジスタにおいてソース・
ドレイン電極間の金属絶縁体半導体の幅をトンネル電流
が流れる程度に狭くし，ゲート電圧によってトンネル電
流を制御するようにしたものである。
ゲート電極を備える薄膜トランジスタにおいてソース・
ドレイン電極間の金属絶縁体半導体の幅をトンネル電流
が流れる程度に狭くし，ゲート電圧によってトンネル電
流を制御するようにしたものである。
【００５４】図８ (a)は構造であり，図８ (b)はその特
性の例である。 図８ (a) １２１は基板であって，ガラス，シリコン等である。
性の例である。 図８ (a) １２１は基板であって，ガラス，シリコン等である。
【００５５】１２２はゲート電極である。１２３はゲー
ト絶縁膜である。１２４，１２４’は金属膜であって，
ソース電極，ドレイン電極となるものである。
ト絶縁膜である。１２４，１２４’は金属膜であって，
ソース電極，ドレイン電極となるものである。
【００５６】１２５は金属酸化物半導体である。１２６
はギャップであって，金属酸化物半導体の１２５の最小
幅（金属膜１２４と金属膜１２４’の間の最小幅）であ
って，金属膜（ドレイン電極）１２４と金属膜（ソース
電極）１２４’間の金属酸化物半導体１２５にトンネル
電流が流れる程度のものである。例えば，約０．００５
〜０．０１μｍ程度である。
はギャップであって，金属酸化物半導体の１２５の最小
幅（金属膜１２４と金属膜１２４’の間の最小幅）であ
って，金属膜（ドレイン電極）１２４と金属膜（ソース
電極）１２４’間の金属酸化物半導体１２５にトンネル
電流が流れる程度のものである。例えば，約０．００５
〜０．０１μｍ程度である。
【００５７】このようにすることにより，ゲート電極１
２２の電圧によるソース・ドレイン間電流ＩDSの急峻な
立ち上がり特性を得ることができる。そのため，動作が
高速化し，微小電流で動作することができる。
２２の電圧によるソース・ドレイン間電流ＩDSの急峻な
立ち上がり特性を得ることができる。そのため，動作が
高速化し，微小電流で動作することができる。
【００５８】図８ (b)は図８ (a)の薄膜トランジスタの
特性の例である。横軸はソース電極１２４’とドレイン
電極１２４間の電圧ＶDSであり, 縦軸はソース電極１２
４’とドレイン電極１２４間の電流ＩDSである。パラメ
ータはゲート電圧ＶGS（ソース電極１２４’とゲート電
極１２４間電圧）である。
特性の例である。横軸はソース電極１２４’とドレイン
電極１２４間の電圧ＶDSであり, 縦軸はソース電極１２
４’とドレイン電極１２４間の電流ＩDSである。パラメ
ータはゲート電圧ＶGS（ソース電極１２４’とゲート電
極１２４間電圧）である。
【００５９】例えば，ゲート電圧をＶGS’としておいて
ＶDSをしだいに大きくするとＶDS’の電圧でソース電極
１２４’とドレイン電極１２４の間にトンネル電流が流
れ，図８ (b)のように立ち上がり特性の急峻な特性が得
られる（ＶGSで制御することもできる）。
ＶDSをしだいに大きくするとＶDS’の電圧でソース電極
１２４’とドレイン電極１２４の間にトンネル電流が流
れ，図８ (b)のように立ち上がり特性の急峻な特性が得
られる（ＶGSで制御することもできる）。
【００６０】図９ (a)は図９の本発明の実施例３の製造
方法を示す図である。図９ (a)，図９ (b)，図９ (c)に
おいて，１２１は基板である。
方法を示す図である。図９ (a)，図９ (b)，図９ (c)に
おいて，１２１は基板である。
【００６１】１２２はゲート電極である。１２３はゲー
ト絶縁膜である。１２４，１２４’は金属膜であって，
ソース電極，ドレイン電極となるものである。
ト絶縁膜である。１２４，１２４’は金属膜であって，
ソース電極，ドレイン電極となるものである。
【００６２】１２５は金属酸化物半導体である。１２８
はマスク用絶縁膜であって，窒化シリコン等の膜であ
る。図９ (a)の(2) は，エッチングによりマスク用絶縁
膜１２８に開口を設けた後の状態を示す。
はマスク用絶縁膜であって，窒化シリコン等の膜であ
る。図９ (a)の(2) は，エッチングによりマスク用絶縁
膜１２８に開口を設けた後の状態を示す。
【００６３】１３０はフォトレジストマスクである。図
９ (a)において， (1) 基板１２１にゲート電極を形成し，さらにその全
面をゲート絶縁膜１２３で被覆する（厚さ約０．０２μ
ｍ）。その上に，銅，亜鉛，アルミニュウム等の金属膜
１２４をスパッタ法等で形成する（厚さ約０．０５μ
ｍ）。 (2) 金属膜１２４の全面にマスク用絶縁膜１２８形成
する。その上にフォトレジストを塗布しマスクを使用し
て露光し，フォトレジストマスク１３０を作る。そし
て，フォトレジストマスク１３０によりマスク用絶縁膜
をエッチングし，図９ (a)の(2) のような開口部を持つ
マスク用絶縁膜１２８を作成する。このとき，エッチン
グ特性により図８ (b)のように上部で広く，下部で狭い
開口が得られるので，エッチング時間を調整することに
より，マスク用絶縁膜１２８の開口の下部をリソグラフ
ィの限界より狭くすることができる。
９ (a)において， (1) 基板１２１にゲート電極を形成し，さらにその全
面をゲート絶縁膜１２３で被覆する（厚さ約０．０２μ
ｍ）。その上に，銅，亜鉛，アルミニュウム等の金属膜
１２４をスパッタ法等で形成する（厚さ約０．０５μ
ｍ）。 (2) 金属膜１２４の全面にマスク用絶縁膜１２８形成
する。その上にフォトレジストを塗布しマスクを使用し
て露光し，フォトレジストマスク１３０を作る。そし
て，フォトレジストマスク１３０によりマスク用絶縁膜
をエッチングし，図９ (a)の(2) のような開口部を持つ
マスク用絶縁膜１２８を作成する。このとき，エッチン
グ特性により図８ (b)のように上部で広く，下部で狭い
開口が得られるので，エッチング時間を調整することに
より，マスク用絶縁膜１２８の開口の下部をリソグラフ
ィの限界より狭くすることができる。
【００６４】(3) (2) の状態において，マスク用絶縁
膜１２８をマスクとして金属膜１２４を酸化し，マスク
用絶縁膜を除去する。このとき，酸化の形状は，図９
(c)に示すように開口部の上部で広く，下部で狭い形状
となる。この性質を利用して，金属酸化物半導体１２５
の最小幅をトンネル電流が流れる程度の狭いものとする
ことができる。
膜１２８をマスクとして金属膜１２４を酸化し，マスク
用絶縁膜を除去する。このとき，酸化の形状は，図９
(c)に示すように開口部の上部で広く，下部で狭い形状
となる。この性質を利用して，金属酸化物半導体１２５
の最小幅をトンネル電流が流れる程度の狭いものとする
ことができる。
【００６５】図１０は本発明の実施例４であって，金属
酸化物半導体によりバイポーラトランジスタを構成した
別の実施例である。本発明は，金属絶縁物半導体の酸素
の過不足による欠陥を補償する目的で金属絶縁物半導体
に不純物を導入することにより，キャリヤ密度および導
電型を制御し，半導体装置へ適用できるようにしたもの
である。例えば，不純物として水素，リチウム，ナトリ
ウム，カリウム，銅，インジウム等を金属酸化物半導体
に導入することにより亜酸化銅等の金属酸化物半導体の
過剰な酸素による結果を除去し，キャリヤ密度，導電型
を制御することができる。そのようにキャリヤ密度およ
び導電型を制御した金属半導体に対して，さらに，弗
素，塩素，リン，砒素，アンチモン等の元素を導入する
ことで導電型を制御することにより良好なｐｎ接合を作
成することができる。
酸化物半導体によりバイポーラトランジスタを構成した
別の実施例である。本発明は，金属絶縁物半導体の酸素
の過不足による欠陥を補償する目的で金属絶縁物半導体
に不純物を導入することにより，キャリヤ密度および導
電型を制御し，半導体装置へ適用できるようにしたもの
である。例えば，不純物として水素，リチウム，ナトリ
ウム，カリウム，銅，インジウム等を金属酸化物半導体
に導入することにより亜酸化銅等の金属酸化物半導体の
過剰な酸素による結果を除去し，キャリヤ密度，導電型
を制御することができる。そのようにキャリヤ密度およ
び導電型を制御した金属半導体に対して，さらに，弗
素，塩素，リン，砒素，アンチモン等の元素を導入する
ことで導電型を制御することにより良好なｐｎ接合を作
成することができる。
【００６６】図１０において，６０は基板であって，ガ
ラス，石英，シリコン等である。６０’は金属膜（銅）
である。
ラス，石英，シリコン等である。６０’は金属膜（銅）
である。
【００６７】６１は金属酸化物半導体（ｐ型）であっ
て，亜酸化銅でありコレクタである。６２は金属酸化物
半導体（ｎ型）であって，亜酸化銅でありベースであ
る。６３は金属酸化物半導体（ｐ型）であって，亜酸化
銅でありエミッタである。
て，亜酸化銅でありコレクタである。６２は金属酸化物
半導体（ｎ型）であって，亜酸化銅でありベースであ
る。６３は金属酸化物半導体（ｐ型）であって，亜酸化
銅でありエミッタである。
【００６８】図１０において，電極の引き出し線は省略
されている。図１０のバイポーラトランジスタの製造方
法について説明する。 (1) 基板（ガラス，シリコン等）６０に室温で銅をス
パッタ法により堆積する。膜厚は下部に電極として０．
２μｍの銅を残したまま，全て厚さ０．８μｍの亜酸化
銅とするため，０．６μｍ程度である。
されている。図１０のバイポーラトランジスタの製造方
法について説明する。 (1) 基板（ガラス，シリコン等）６０に室温で銅をス
パッタ法により堆積する。膜厚は下部に電極として０．
２μｍの銅を残したまま，全て厚さ０．８μｍの亜酸化
銅とするため，０．６μｍ程度である。
【００６９】(2) ２５０°Ｃ，６時間程度乾燥酸素中
で熱酸化し，０．８μｍの亜酸化銅の膜を作る。２５０
°Ｃでは絶縁体である酸化銅（本発明者等の研究により
ＣｕＯ）が亜酸化銅（Ｃｕ2 Ｏ）の代わりに作られてし
まうことはないことが明きらかにされている。３５０°
Ｃ以上の熱酸化では絶縁性の酸化銅が表面に生じる）。
で熱酸化し，０．８μｍの亜酸化銅の膜を作る。２５０
°Ｃでは絶縁体である酸化銅（本発明者等の研究により
ＣｕＯ）が亜酸化銅（Ｃｕ2 Ｏ）の代わりに作られてし
まうことはないことが明きらかにされている。３５０°
Ｃ以上の熱酸化では絶縁性の酸化銅が表面に生じる）。
【００７０】(3) この亜酸化銅をアルゴンの雰囲気中
で８００°Ｃ，３０分の熱処理をすることにより特性を
向上させる（本発明者等の研究により，２５０°Ｃの熱
酸化で作られた亜酸化銅は８００°Ｃの熱処理にも耐え
られ，さらにモビリティ等の特性も向上することが明ら
かにされている（図１１参照））。
で８００°Ｃ，３０分の熱処理をすることにより特性を
向上させる（本発明者等の研究により，２５０°Ｃの熱
酸化で作られた亜酸化銅は８００°Ｃの熱処理にも耐え
られ，さらにモビリティ等の特性も向上することが明ら
かにされている（図１１参照））。
【００７１】(4) Ｌｉ，Ｎａ，Ｋなどの金属，Ｉｎな
どの銅サイトに入って不足銅成分を補う元素をイオン注
入し，その後のアルゴン雰囲気中８００°Ｃ，３０分の
熱処理により，ｎ型亜酸化銅を形成する。この時，ｎ型
を形成する不純物としては他に，Ｓｅ，Ｓ，Ｆ，Ｃｌ，
Ｂｒ，Ｉ等が考えられる。また，Ｐ，Ｓｉ，Ａｓ等も考
えられる。
どの銅サイトに入って不足銅成分を補う元素をイオン注
入し，その後のアルゴン雰囲気中８００°Ｃ，３０分の
熱処理により，ｎ型亜酸化銅を形成する。この時，ｎ型
を形成する不純物としては他に，Ｓｅ，Ｓ，Ｆ，Ｃｌ，
Ｂｒ，Ｉ等が考えられる。また，Ｐ，Ｓｉ，Ａｓ等も考
えられる。
【００７２】(5) さらに(4) で作られたｎ型層の表面
部を再度ｐ型に反転する目的でイオン注入を行う。その
後，８００°Ｃ，３０分の熱処理を行う。 ・なお，上記において，(3) ，(4) ，(5) は，図１０
(b)のようにイオン注入しておき１回の熱処理で行うこ
とができる。
部を再度ｐ型に反転する目的でイオン注入を行う。その
後，８００°Ｃ，３０分の熱処理を行う。 ・なお，上記において，(3) ，(4) ，(5) は，図１０
(b)のようにイオン注入しておき１回の熱処理で行うこ
とができる。
【００７３】また，工程(4) までとしてダイオードとし
ても良い。図１１は本発明で使用する亜酸化銅のアニー
ル温度による亜酸化銅の特性変化を示す図である。
ても良い。図１１は本発明で使用する亜酸化銅のアニー
ル温度による亜酸化銅の特性変化を示す図である。
【００７４】図１１は，アニール時間３０分として，ア
ニール温度により亜酸化銅のホール移動度，キャリヤ密
度，抵抗の変化をアニール前とアニール後により比較し
たものである。横軸はアニール温度である。
ニール温度により亜酸化銅のホール移動度，キャリヤ密
度，抵抗の変化をアニール前とアニール後により比較し
たものである。横軸はアニール温度である。
【００７５】図１１に示すように，亜酸化銅はアニール
温度によりアニール前に比較して良好な特性に変化する
ことが示されている。特に，８００°Ｃ程度の高温でも
アニールに耐え，移動度も高くなることから，高温処理
の半導集積回路としても利用できることが示されてい
る。
温度によりアニール前に比較して良好な特性に変化する
ことが示されている。特に，８００°Ｃ程度の高温でも
アニールに耐え，移動度も高くなることから，高温処理
の半導集積回路としても利用できることが示されてい
る。
【００７６】図１２は本発明の実施例５であって，その
ようにして，金属酸化物半導体により，バイポーラトラ
ンジスタを構成したものである。図１２において，４１
は基板である。
ようにして，金属酸化物半導体により，バイポーラトラ
ンジスタを構成したものである。図１２において，４１
は基板である。
【００７７】４２は金属酸化物半導体（ｐ型）であっ
て，コレクタである。４３は絶縁膜１である。４４は金
属酸化物半導体であって，ｎ型のベースである。
て，コレクタである。４３は絶縁膜１である。４４は金
属酸化物半導体であって，ｎ型のベースである。
【００７８】４５は電極線１であって，金属酸化物半導
体（ｎ型）（ベース）４４の引き出し線である。４６は
絶縁膜２である。
体（ｎ型）（ベース）４４の引き出し線である。４６は
絶縁膜２である。
【００７９】４７は金属酸化物半導体（ｐ型）であっ
て，エミッタである。４８は電極配線２であって，エミ
ッタ４７の引き出し線である。図１２の実施例５のバイ
ポーラトランジスタの製造方法について説明する。
て，エミッタである。４８は電極配線２であって，エミ
ッタ４７の引き出し線である。図１２の実施例５のバイ
ポーラトランジスタの製造方法について説明する。
【００８０】(1) 基板４１上に金属酸化物半導体（ｐ
型）４２を形成する。さらに，金属酸化物半導体４２上
に絶縁膜１（４３）を形成する。 (2) 絶縁膜１（４３）をエッチングしてベース領域形
成用の開口５０を設け，前述した方法により金属酸化物
半導体層４２の表面に不純物をドープし，導電型をｎ型
としてｐｎ接合を形成する。さらに，ベース引き出し電
極線４５を配線する。
型）４２を形成する。さらに，金属酸化物半導体４２上
に絶縁膜１（４３）を形成する。 (2) 絶縁膜１（４３）をエッチングしてベース領域形
成用の開口５０を設け，前述した方法により金属酸化物
半導体層４２の表面に不純物をドープし，導電型をｎ型
としてｐｎ接合を形成する。さらに，ベース引き出し電
極線４５を配線する。
【００８１】(3) (2) の状態で全面に絶縁膜１（４
３）を設け，エッチングによりエミッタ領域形成用の開
口５１を設け，前述の導電型の制御方法によりベース領
域の一部の導電型をｐ型にすることによりｐｎ接合を形
成する。その後，エミッタ引き出し電極４７を設ける。
３）を設け，エッチングによりエミッタ領域形成用の開
口５１を設け，前述の導電型の制御方法によりベース領
域の一部の導電型をｐ型にすることによりｐｎ接合を形
成する。その後，エミッタ引き出し電極４７を設ける。
【００８２】以後，表面保護膜（図示せず）等を形成し
てバイポーラトランジスタとする。なお，上記におい
て，亜酸化銅等の金属酸化物半導体が，もともと内部に
含む元素またはある種の物質を，中性子照射による核反
応，もしくは水素原子照射による核反応など，結果的に
元素またはある種の物質が酸素に変化する反応により，
金属の一部または全部が反応して形成されるようにして
も良い。
てバイポーラトランジスタとする。なお，上記におい
て，亜酸化銅等の金属酸化物半導体が，もともと内部に
含む元素またはある種の物質を，中性子照射による核反
応，もしくは水素原子照射による核反応など，結果的に
元素またはある種の物質が酸素に変化する反応により，
金属の一部または全部が反応して形成されるようにして
も良い。
【００８３】
【発明の効果】本発明によれば，低温処理により高移動
度の薄膜トランジスタを大面積に作成することができ
る。また製造コストも低くすることができる。
度の薄膜トランジスタを大面積に作成することができ
る。また製造コストも低くすることができる。
【００８４】さらに，本発明によれば金属酸化物半導体
にｐｎ接合を良好に作成することができ，ｐｎ接合を持
つ金属酸化物薄膜半導体を低コストで製造することがで
きる。
にｐｎ接合を良好に作成することができ，ｐｎ接合を持
つ金属酸化物薄膜半導体を低コストで製造することがで
きる。
【００８５】また，本発明によれば，金属薄膜の一部を
トンネル電流が流せるほどの微小な幅の金属酸化物半導
体を得ることが可能なので，全く新しい原理で動作する
超微細トランジスタを製作し，超ＬＳＩの集積度を飛躍
的に高めかつ信号処理時間も飛躍的に速めた超ＬＳＩを
製作することができる。
トンネル電流が流せるほどの微小な幅の金属酸化物半導
体を得ることが可能なので，全く新しい原理で動作する
超微細トランジスタを製作し，超ＬＳＩの集積度を飛躍
的に高めかつ信号処理時間も飛躍的に速めた超ＬＳＩを
製作することができる。
【図１】本発明の基本構成(1) を示す図である。
【図２】本発明の基本構成(2) を示す図である。
【図３】本発明で使用する金属酸化物半導体の特性の例
を示す図である。
を示す図である。
【図４】本発明の実施例１を示す図である。
【図５】本発明の実施例１の製造方法を示す図である。
【図６】本発明の実施例１の特性の例を示す図である。
【図７】本発明の実施例２を示す図である。
【図８】本発明の実施例３を示す図である。
【図９】本発明の実施例３の製造方法を示す図である。
【図１０】本発明の実施例４を示す図である。
【図１１】本発明実施例のアニール温度による亜酸化銅
の変化を示す図である。
の変化を示す図である。
【図１２】本発明の実施例５を示す図である。
１：基板 ２：電極金属 ３：絶縁膜 ４：金属膜 ５：金属酸化物半導体 １１：基板 １２：金属膜 １３：金属酸化物半導体（第１の導電型） １４：真性半導体化領域 １５：接合部（ｐｎ接合） １６：金属酸化物半導体（第２の導電型）
Claims (8)
- 【請求項１】 基板上に，形成した金属薄膜を酸化処理
することにより半導体化した金属酸化物半導体とを備え
ることを特徴とする金属酸化物半導体による薄膜トラン
ジスタ。 - 【請求項２】 基板上に備えられたゲート電極と，該ゲ
ート電極上に絶縁膜を介して設けられた金属酸化物半導
体の薄膜と，該金属酸化物半導体薄膜に接続された電極
とを備えることを特徴とする請求項１に記載の金属酸化
物半導体による薄膜トランジスタ。 - 【請求項３】 該絶縁膜上に設けた金属膜の一部を酸化
して得た金属酸化物半導体の最小幅をトンネル電流が流
れる程度の幅とすることを特徴とする請求項２に記載の
金属酸化物半導体による薄膜トランジスタ。 - 【請求項４】 金属酸化物半導体−金属−金属酸化物半
導体構造であることを特徴とする請求項１に記載の金属
酸化物半導体による薄膜トランジスタ。 - 【請求項５】 基板上に金属薄膜を設け，該金属薄膜を
酸化処理することにより第１の導電型を持つ金属酸化物
半導体とし，該金属酸化物半導体に第２の導電型不純物
を導入して第１の導電型と第２の導電型の接合を形成
し，半導体装置とすることを特徴とするｐｎ接合を形成
した金属酸化物半導体装置。 - 【請求項６】 酸素過剰による欠陥を補償する目的で，
水素，リチウム，ナトリウム，カリウム，銅，亜鉛，イ
ンジウム等の１種もしくは複数種の不純物を金属酸化物
半導体に導入し，その金属酸化物半導体のキャリヤ密度
および導電型を制御することを特徴とする請求項１，
２，３，４に記載の金属酸化物半導体による薄膜トラン
ジスタもしくは請求項５に記載のｐｎ接合を形成した金
属酸化物半導体装置の製造方法。 - 【請求項７】 酸素不足による欠陥を補償する目的で，
酸素，水素もしくは周期律表における酸素と同じ族の元
素等の１種もしくは複数種の不純物を金属酸化物半導体
に導入し，その金属酸化物半導体のキャリヤ密度および
導電型を制御することを特徴とする請求項１，２，３，
４に記載の金属酸化物半導体による薄膜トランジスタも
しくは請求項５に記載のｐｎ接合を形成した金属酸化物
半導体装置の製造方法。 - 【請求項８】 キャリヤ密度および導電型が制御された
金属酸化物半導体にイオウ、セレン，弗素，塩素，リ
ン，砒素，アンチモン等の元素を導入することで導電型
を制御することを特徴とする請求項６もしくは７に記載
の金属酸化物半導体による薄膜トランジスタもしくはｐ
ｎ接合を形成した金属酸化物半導体装置の製造方法。
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| JP06827095A JP3479375B2 (ja) | 1995-03-27 | 1995-03-27 | 亜酸化銅等の金属酸化物半導体による薄膜トランジスタとｐｎ接合を形成した金属酸化物半導体装置およびそれらの製造方法 |
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| JP06827095A JP3479375B2 (ja) | 1995-03-27 | 1995-03-27 | 亜酸化銅等の金属酸化物半導体による薄膜トランジスタとｐｎ接合を形成した金属酸化物半導体装置およびそれらの製造方法 |
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| Publication Number | Publication Date |
|---|---|
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