JP5419913B2 - 多層拡張ドレイン構造を有する高電圧トランジスタを作製する方法 - Google Patents
多層拡張ドレイン構造を有する高電圧トランジスタを作製する方法 Download PDFInfo
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- JP5419913B2 JP5419913B2 JP2011067774A JP2011067774A JP5419913B2 JP 5419913 B2 JP5419913 B2 JP 5419913B2 JP 2011067774 A JP2011067774 A JP 2011067774A JP 2011067774 A JP2011067774 A JP 2011067774A JP 5419913 B2 JP5419913 B2 JP 5419913B2
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- 238000000034 method Methods 0.000 title claims description 47
- 239000000758 substrate Substances 0.000 claims description 72
- 210000000746 body region Anatomy 0.000 claims description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims description 13
- 239000000377 silicon dioxide Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 6
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 118
- 239000000463 material Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
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- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
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- 239000003989 dielectric material Substances 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JCALBVZBIRXHMQ-UHFFFAOYSA-N [[hydroxy-(phosphonoamino)phosphoryl]amino]phosphonic acid Chemical compound OP(O)(=O)NP(O)(=O)NP(O)(O)=O JCALBVZBIRXHMQ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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Description
基板上に第一の導電型で上面を有するエピタキシャル層を形成し、
前記エピタキシャル層をエッチングして、第一及び第二の側壁部があるメサを規定する一対の離間した溝部を形成し、
各溝部を部分的に充填するとともに第一及び第二の側壁部をカバーする誘電体層を各溝部に形成し、
溝部の残りの部分を導電材料で充填して、基板及びエピタキシャル層から絶縁された第一及び第二のフィールドプレート部材を形成する、
ことを具備することを特徴とする。
基板上に第一の導電型で上面を有するエピタキシャル層を形成し、
エピタキシャル層内に第一の導電型でエピタキシャル層の上面に配置されたソース領域、および第一の導電型とは異なる第二の導電型のボディ領域を形成し、
エピタキシャル層に第一及び第二の側壁部を有するメサを規定する離間した一対の溝部を形成し、
第一及び第二の側壁部をカバーする誘電体層を各溝部に形成し、
メサから絶縁された導電材料からなるフィールドプレート部材を溝部に形成し、そして、
メサ内で絶縁ゲート部材の近傍でボディ領域を通るチャネルが規定されるように、各フィールドプレート部材とメサとの間に絶縁ゲート部材を形成する、
ことを具備することを特徴とする。
第一の方向とされた複数の平行に配列されたドリフト領域を形成することを含み、当該ドリフト領域のそれぞれは、絶縁層と導電層が交互に配置された第一の導電型にドーピングされた半導体層を含み、当該導電層は前記ドーピングされた半導体層から前記絶縁層によって絶縁されており、前記導電層は高電圧トランジスタのフィールドプレート部材を含んでおり、
第一の導電型であるソース領域、第一の導電型とは異なる第二の導電型で、ソース領域をドリフト領域から分離するボディ領域を形成することを含み、そして、
ボディ領域内のソース領域とドリフト領域の間にチャネルを規定する絶縁ゲートをボディ領域近傍に形成する、
ことを含むことを特徴とする。
ソース領域に接続されたソース電極を形成する、
ことを含むことができる。
Claims (26)
- 高電圧金属酸化物半導体フィールド効果トランジスタ及び該トランジスタの拡張ドレイン領域を作製する方法であって、
基板上に、上面を有する第一の導電型のエピタキシャル層を形成し、
前記エピタキシャル層をエッチングして、第一及び第二の側壁部を有するメサを規定する一対の離間した第一の溝部を、前記メサが前記第一の溝部の深さの20%未満の横方向の幅を有するようにして、形成し、
各第一の溝部を部分的に充填するとともに第一及び第二の側壁部を被覆する誘電体層であって、該誘電体層の横方向の幅が、前記メサの横方向の幅よりも広い前記誘電体層を各第一の溝部に形成し、
前記第一の溝部の残りの部分を導電材料で充填して、前記基板及び前記エピタキシャル層から絶縁された第一及び第二のフィールドプレート部材を形成し、
前記第一の導電型のソース領域及び前記第二の導電型のボディ領域を、前記エピタキシャル層の上面に形成して、前記拡張ドレイン領域を、前記ソース領域と前記基板との間に、定め、
前記エピタキシャル層の互いに向かい合う面に接する各誘電体層に第二の溝部を形成し、そして
前記第二の溝部内にゲート誘電体層及びゲートを形成する、前記方法。 - 前記ソース領域に接続されたソース電極及び前記基板に接続されたドレイン電極を形成することを更に含む請求項1記載の方法。
- 前記第一の導電型はn型である、請求項1又は2記載の方法。
- 前記メサが、0.4μm乃至1.2μmの幅を有し、前記誘電体層が2μm乃至5μmの横方向の幅を有しており、前記第二の溝部の前記深さが、1μm乃至5μmである請求項1記載の方法。
- 前記エピタキシャル層のドーピング濃度が、前記基板近くに比べ前記上面近くの方が低い、請求項1乃至4何れか一項記載の方法。
- 前記エピタキシャル層が、線形的に変化するドーピング・プロファイルを有するよう形成される請求項5記載の方法。
- 前記誘電体層が二酸化ケイ素からなる請求項1乃至6何れか一項記載の方法。
- 前記フィールドプレート部材が、ドープしたポリシリコンからなる請求項1乃至7何れか一項記載の方法。
- 前記ドレイン電極の形成の前に、前記基板を薄くすることを更に含む請求項2記載の方法。
- 前記基板が前記第一の導電型である請求項1乃至9何れか一項記載の方法。
- 前記第一の溝部が前記エピタキシャル層を通って基板へ延びている請求項1乃至10何れか一項記載の方法。
- 前記第二の溝部の深さが、前記ソース領域の表面から、前記ボディ領域の側面に沿った導通状態のチャネルの長さに対応する深さまで延びる請求項1乃至11何れか一項記載の方法。
- 前記ゲート誘電体層が、前記積層されたソース領域、ボディ領域、及びエピタキシャル領域の側壁に接して形成される請求項1乃至12何れか一項記載の方法。
- 基板上に、上面を有する第一の導電型のエピタキシャル層を形成し、
前記エピタキシャル層をエッチングして、第一及び第二の側壁部を有するメサを規定する一対の離間した溝部を、前記メサが前記溝部の深さの20%未満の横方向の幅を有するようにして、形成し、
前記溝部を部分的に充填するとともに第一及び第二の側壁部を被覆する誘電体層であって、該誘電体層の横方向の幅が、前記メサの横方向の幅よりも広い前記誘電体層を、前記誘電体層が前記メサの横方向の幅よりも広い横方向の幅を有して、各溝部に形成し、
前記溝部の残りの部分を導電材料で充填して、前記基板及び前記エピタキシャル層から絶縁された第一及び第二のフィールドプレート部材を形成する、ことから成る高電圧トランジスタの拡張ドレイン領域を作製する方法。 - 前記エピタキシャル層の上面に第一導電型のソース領域及び第二導電型のボディ領域を形成することを更に含み、前記拡張ドレイン領域が、前記ソース領域と前記基板との間に規定されている、請求項14記載の方法。
- 前記ソース領域に接続されたソース電極及び前記基板に接続されたドレイン電極を形成することを更に含む請求項15記載の方法。
- 前記誘電体層及び前記フィールドプレード部材が、前記フィールドプレート部材と前記メサとの間隔が基板近くに比べてメサの上面近くの方が狭くなるように形成される、請求項14乃至16何れか一項記載の方法。
- 前記第一の導電型がn型である、請求項14乃至17何れか一項記載の方法。
- 前記エピタキシャル層のドーピング濃度を、基板近くに比べて上面近くの方が低くなるよう形成する、請求項14乃至18何れか一項記載の方法。
- 前記エピタキシャル層を、線形的に変化するドーピング・プロファイルを有するよう形成する、請求項19に記載の方法。
- 前記誘電体層は二酸化ケイ素からなる請求項14乃至20何れか一項記載の方法。
- 前記フィールドプレート部材がドープしたポリシリコンからなる請求項14乃至21何れか一項記載の方法。
- 前記ドレイン電極の形成の前に、前記基板を薄くすることを更に含む請求項16記載の方法。
- 前記基板が第一の導電型を有する請求項14乃至23何れか一項記載の方法。
- 前記溝部が前記エピタキシャル層を通って前記基板へ延びている請求項14乃至24何れか一項記載の方法。
- 前記拡張ドレイン領域が、ドリフト領域からなり、
前記溝部の内の前記誘電体層が、酸化物層からなり、
前記ドリフト領域、誘電体層、フィールドプレート部材が、一体となって、横方向に延びる平行な層構造を構成している請求項14乃至25何れか一項記載の方法。
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2001
- 2001-09-07 US US09/948,879 patent/US6635544B2/en not_active Expired - Lifetime
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US6750105B2 (en) | 2004-06-15 |
EP1291907A3 (en) | 2004-02-04 |
US7253042B2 (en) | 2007-08-07 |
JP4744101B2 (ja) | 2011-08-10 |
US20120015491A1 (en) | 2012-01-19 |
EP2264747A3 (en) | 2011-02-02 |
EP2264747A2 (en) | 2010-12-22 |
US6667213B2 (en) | 2003-12-23 |
US20050104121A1 (en) | 2005-05-19 |
EP1291907A2 (en) | 2003-03-12 |
US8940605B2 (en) | 2015-01-27 |
EP2270843A2 (en) | 2011-01-05 |
US20040082122A1 (en) | 2004-04-29 |
US20030049930A1 (en) | 2003-03-13 |
US6635544B2 (en) | 2003-10-21 |
EP2270843A3 (en) | 2011-01-26 |
US6838346B2 (en) | 2005-01-04 |
US7998817B2 (en) | 2011-08-16 |
US20090233407A1 (en) | 2009-09-17 |
US20070293002A1 (en) | 2007-12-20 |
US7745291B2 (en) | 2010-06-29 |
EP1536464A3 (en) | 2008-08-06 |
JP4284428B2 (ja) | 2009-06-24 |
EP2264746A2 (en) | 2010-12-22 |
US20030060001A1 (en) | 2003-03-27 |
EP1536464A2 (en) | 2005-06-01 |
JP2004312037A (ja) | 2004-11-04 |
JP2011159987A (ja) | 2011-08-18 |
US20030057524A1 (en) | 2003-03-27 |
JP2003204064A (ja) | 2003-07-18 |
EP2264746A3 (en) | 2011-01-26 |
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