JP5378321B2 - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JP5378321B2 JP5378321B2 JP2010175297A JP2010175297A JP5378321B2 JP 5378321 B2 JP5378321 B2 JP 5378321B2 JP 2010175297 A JP2010175297 A JP 2010175297A JP 2010175297 A JP2010175297 A JP 2010175297A JP 5378321 B2 JP5378321 B2 JP 5378321B2
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- JP
- Japan
- Prior art keywords
- layer
- light
- conductive layer
- conductive
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Description
本実施の形態では、本発明の一態様である半導体装置について説明する。
本発明の一態様によって薄膜トランジスタを作製し、該薄膜トランジスタを画素部、さらには駆動回路に用いて表示機能を有する半導体装置(表示装置ともいう)を作製することができる。また、薄膜トランジスタを形成した駆動回路の一部または全体と、薄膜トランジスタを形成した画素部とを同一基板上に一体形成し、システムオンパネルを形成することができる。
半導体装置の一形態として電子ペーパーの例を示す。
本実施の形態では、半導体装置として発光表示装置の例を示す。表示装置の有する表示素子としては、ここではエレクトロルミネッセンスを利用する発光素子を用いて示す。エレクトロルミネッセンスを利用する発光素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、一般的に、前者は有機EL素子、後者は無機EL素子と呼ばれている。
半導体装置は、電子ペーパーとして適用することができる。電子ペーパーは、情報を表示する、あらゆる分野の電子機器に用いることが可能である。例えば、電子ペーパーを、電子書籍(電子ブック)、ポスター、電車などの乗り物の車内広告、クレジットカード等の各種カードにおける表示部分などに適用することができる。電子機器の一例を図23、図24に示す。
本実施の形態においては、液晶表示装置に適用できる画素の構成及び画素の動作について説明する。なお、本実施の形態における液晶素子の動作モードとして、TN(Twisted Nematic)モード、IPS(In−Plane−Switching)モード、FFS(Fringe Field Switching)モード、MVA(Multi−domain Vertical Alignment)モード、PVA(Patterned Vertical Alignment)モード、ASM(Axially Symmetric aligned Micro−cell)モード、OCB(Optically Compensated Birefringence)モード、FLC(Ferroelectric Liquid Crystal)モード、AFLC(AntiFerroelectric Liquid Crystal)モードなどを用いることができる。
次に、表示装置の別の構成例およびその駆動方法について説明する。本実施の形態においては、信号書込みに対する輝度の応答が遅い(応答時間が長い)表示素子を用いた表示装置の場合について述べる。本実施の形態においては、応答時間が長い表示素子として液晶素子を例として説明するが、本実施の形態における表示素子はこれに限定されず、信号書込みに対する輝度の応答が遅い様々な表示素子を用いることができる。
次に、表示装置の別の構成例およびその駆動方法について説明する。本実施の形態においては、表示装置の外部から入力される画像(入力画像)の動きを補間する画像を、複数の入力画像を基にして表示装置の内部で生成し、当該生成された画像(生成画像)と、入力画像とを順次表示させる方法について説明する。なお、生成画像を、入力画像の動きを補間するような画像とすることで、動画の動きを滑らかにすることができ、さらに、ホールド駆動による残像等によって動画の品質が低下する問題を改善できる。ここで、動画の補間について、以下に説明する。動画の表示は、理想的には、個々の画素の輝度をリアルタイムに制御することで実現されるものであるが、画素のリアルタイム個別制御は、制御回路の数が膨大なものとなる問題、配線スペースの問題、および入力画像のデータ量が膨大なものとなる問題等が存在し、実現が困難である。したがって、表示装置による動画の表示は、複数の静止画を一定の周期で順次表示することで、表示が動画に見えるようにして行なわれている。この周期(本実施の形態においては入力画像信号周期と呼び、Tinと表す)は規格化されており、例として、NTSC規格では1/60秒、PAL規格では1/50秒である。この程度の周期でも、インパルス型表示装置であるCRTにおいては動画表示に問題は起こらなかった。しかし、ホールド型表示装置においては、これらの規格に準じた動画をそのまま表示すると、ホールド型であることに起因する残像等により表示が不鮮明となる不具合(ホールドぼけ:hold blur)が発生してしまう。ホールドぼけは、人間の目の追従による無意識的な動きの補間と、ホールド型の表示との不一致(discrepancy)で認識されるものであるので、従来の規格よりも入力画像信号周期を短くする(画素のリアルタイム個別制御に近づける)ことで低減させることができるが、入力画像信号周期を短くすることは規格の変更を伴い、さらに、データ量も増大することになるので、困難である。しかしながら、規格化された入力画像信号を基にして、入力画像の動きを補間するような画像を表示装置内部で生成し、当該生成画像によって入力画像を補間して表示することで、規格の変更またはデータ量の増大なしに、ホールドぼけを低減できる。このように、入力画像信号を基にして表示装置内部で画像信号を生成し、入力画像の動きを補間することを、動画の補間と呼ぶこととする。
半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラなどのカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
102 導電膜
103 導電膜
108 導電層
111 絶縁膜
112 半導体膜
114 導電膜
115 導電膜
117 コンタクトホール
123 絶縁層
124 画素電極
131 容量素子
180 グレートーンマスク
181 基板
182 遮光部
183 回折格子部
185 ハーフトーンマスク
187 半透光部
188 遮光部
201 導電膜
206 導電膜
207 導電膜
208 絶縁層
300 室温以上
301 ソース配線部
302 薄膜トランジスタ部
303 ゲート配線部
331 ソース配線部
332 薄膜トランジスタ部
333 ゲート配線部
334 保持容量部
454 平坦化絶縁層
580 基板
596 基板
581 薄膜トランジスタ
585 絶縁膜
586 絶縁膜
587 電極層
588 電極層
589 球形粒子
594 キャビティ
595 充填材
701 駆動用TFT
702 発光素子
703 陰極
704 発光層
705 陽極
707 導電層
711 駆動用TFT
712 発光素子
713 陰極
714 発光層
715 陽極
716 遮光膜
717 導電層
721 駆動用TFT
722 発光素子
723 陰極
724 発光層
725 陽極
727 導電層
1000 携帯電話機
1001 筐体
1002 表示部
1003 操作ボタン
1004 外部接続ポート
1005 スピーカ
1006 マイク
104a 導電層
104b 導電層
105a 導電層
105e 導電層
106a レジストマスク
106e レジストマスク
107a 導電層
107b 導電層
107e 導電層
107f 導電層
107g 導電層
108a 導電層
108b 導電層
108e 導電層
108f 導電層
108g 導電層
109a レジストマスク
110a 導電層
110b 導電層
113a 半導体層
113e 半導体層
116a レジストマスク
118a レジストマスク
118e レジストマスク
119a 導電層
119b 導電層
119e 導電層
119g 導電層
119h 導電層
120a 導電層
120b 導電層
120e 導電層
120g 導電層
120h 導電層
121a レジストマスク
124e 導電層
130A 薄膜トランジスタ
130B 薄膜トランジスタ
131A 容量素子
2600 TFT基板
2601 対向基板
2602 シール材
2603 画素部
2604 表示素子
2605 着色層
2606 偏光板
2607 偏光板
2608 配線回路部
2609 フレキシブル配線基板
2610 冷陰極管
2611 反射板
2612 回路基板
2613 拡散板
2631 ポスター
2632 車内広告
2700 電子書籍
2701 筐体
2703 筐体
2705 表示部
2707 表示部
2711 軸部
2721 電源
2723 操作キー
2725 スピーカ
300a レジストマスク
300e レジストマスク
4001 基板
4002 画素部
4003 信号線駆動回路
4004 走査線駆動回路
4005 シール材
4006 基板
4008 液晶
4010 薄膜トランジスタ
400a 導電層
400e 導電層
4011 薄膜トランジスタ
4013 液晶素子
4014 配線
4015 配線
4016 接続端子電極
4018 FPC
4019 異方性導電膜
401a 導電層
4021 絶縁層
4030 画素電極
4031 対向電極
4040 配線
4050 導電層
4060 導電層
4501 基板
4502 画素部
4505 シール材
4506 基板
4507 充填材
4509 薄膜トランジスタ
4510 薄膜トランジスタ
4511 発光素子
4512 電極
4513 電界発光層
4514 電極層
4515 接続端子電極
4516 端子電極
4517 電極層
4519 異方性導電膜
4520 隔壁
5080 画素
5081 薄膜トランジスタ
5082 液晶素子
5083 容量素子
5084 配線
5085 配線
5086 配線
5087 配線
5088 画素電極
5101 破線
5102 実線
5103 破線
5104 実線
5105 実線
5106 実線
5107 実線
5108 実線
5121 画像
5122 画像
5123 画像
5124 領域
5125 領域
5126 領域
5127 ベクトル
5128 画像生成用ベクトル
5129 領域
5130 物体
5131 領域
590a 黒色領域
590b 白色領域
6400 画素
6401 スイッチング用薄膜トランジスタ
6402 駆動用薄膜トランジスタ
6403 容量素子
6404 発光素子
6405 信号線
6406 走査線
6407 電源線
6408 共通電極
9400 通信装置
9401 筐体
9402 操作ボタン
9403 外部入力端子
9404 マイク
9405 スピーカ
9406 発光部
9410 表示装置
9411 筐体
9412 表示部
9413 操作ボタン
9600 テレビジョン装置
9601 筐体
9603 表示部
9605 スタンド
9607 表示部
9609 操作キー
9610 リモコン操作機
9700 デジタルフォトフレーム
9701 筐体
9703 表示部
9881 筐体
9882 表示部
9883 表示部
9884 スピーカ部
9885 入力手段(操作キー
9886 記録媒体挿入部
9887 接続端子
9888 センサ
9889 マイクロフォン
9890 LEDランプ
9891 筐体
9893 連結部
9900 スロットマシン
9901 筐体
9903 表示部
4503a 信号線駆動回路
4503b 信号線駆動回路
4504a 走査線駆動回路
4504b 走査線駆動回路
4518a FPC
4518b FPC
5121a 画像
5121b 画像
5122a 画像
5122b 画像
5123a 画像
5123b 画像
Claims (3)
- 第1の導電層と、
前記第1の導電層の上方の第1の絶縁層と、
前記第1の絶縁層の上方の酸化物半導体層と、
前記酸化物半導体層の上方の第2の絶縁層と、
前記第2の絶縁層の上方の第2の導電層と、
前記酸化物半導体層に電気的に接続された第3の導電層と、
前記酸化物半導体層に電気的に接続された第4の導電層と、を有し、
前記第1の導電層は、トランジスタの第1のゲート電極として機能する領域を有し、
前記第2の導電層は、前記トランジスタの第2のゲート電極として機能する領域を有し、
前記第3の導電層は、前記トランジスタのソース電極又はドレイン電極の一方として機能する領域を有し、
前記第4の導電層は、前記トランジスタのソース電極又はドレイン電極の他方として機能する領域を有し、
前記第1の導電層は、第1の層と、前記第1の層の上方の第2の層とが、積層された領域を有し、
前記第1の層の端部は、前記第2の層の端部より突出している領域を有することを特徴とする半導体装置。 - 第1の導電層と、
前記第1の導電層の上方の第1の絶縁層と、
前記第1の絶縁層の上方の酸化物半導体層と、
前記酸化物半導体層の上方の第2の絶縁層と、
前記第2の絶縁層の上方の第2の導電層と、
前記酸化物半導体層に電気的に接続された第3の導電層と、
前記酸化物半導体層に電気的に接続された第4の導電層と、を有し、
前記第1の導電層は、トランジスタの第1のゲート電極として機能する領域を有し、
前記第2の導電層は、前記トランジスタの第2のゲート電極として機能する領域を有し、
前記第3の導電層は、前記トランジスタのソース電極又はドレイン電極の一方として機能する領域を有し、
前記第4の導電層は、前記トランジスタのソース電極又はドレイン電極の他方として機能する領域を有し、
前記第1の導電層は、第1の層と、前記第1の層の上方の第2の層とが、積層された領域を有し、
前記第3の導電層は、第3の層と、前記第3の層の上方の第4の層とが、積層された領域を有し、
前記第4の導電層は、第5の層と、前記第5の層の上方の第6の層とが、積層された領域を有し、
前記第1の層の端部は、前記第2の層の端部より突出している領域を有し、
前記第3の層の端部は、前記第4の層の端部より突出している領域を有し、
前記第5の層の端部は、前記第6の層の端部より突出している領域を有することを特徴とする半導体装置。 - 第1の導電層と、
前記第1の導電層の上方の第1の絶縁層と、
前記第1の絶縁層の上方の酸化物半導体層と、
前記酸化物半導体層の上方の第2の絶縁層と、
前記第2の絶縁層の上方の第2の導電層と、
前記酸化物半導体層に電気的に接続された第3の導電層と、
前記酸化物半導体層に電気的に接続された第4の導電層と、を有し、
前記第1の導電層は、トランジスタの第1のゲート電極として機能する領域を有し、
前記第2の導電層は、前記トランジスタの第2のゲート電極として機能する領域を有し、
前記第3の導電層は、前記トランジスタのソース電極又はドレイン電極の一方として機能する領域を有し、
前記第4の導電層は、前記トランジスタのソース電極又はドレイン電極の他方として機能する領域を有し、
前記第1の導電層は、第1の層と、前記第1の層の上方の第2の層とが、積層された領域を有し、
前記第2の導電層は、第7の層と、前記第7の層の上方の第8の層とが、積層された領域を有し、
前記第3の導電層は、第3の層と、前記第3の層の上方の第4の層とが、積層された領域を有し、
前記第4の導電層は、第5の層と、前記第5の層の上方の第6の層とが、積層された領域を有し、
前記第1の層の端部は、前記第2の層の端部より突出している領域を有し、
前記第7の層の端部は、前記第8の層の端部より突出している領域を有し、
前記第3の層の端部は、前記第4の層の端部より突出している領域を有し、
前記第5の層の端部は、前記第6の層の端部より突出している領域を有することを特徴とする半導体装置。
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