JP4812512B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4812512B2
JP4812512B2 JP2006139693A JP2006139693A JP4812512B2 JP 4812512 B2 JP4812512 B2 JP 4812512B2 JP 2006139693 A JP2006139693 A JP 2006139693A JP 2006139693 A JP2006139693 A JP 2006139693A JP 4812512 B2 JP4812512 B2 JP 4812512B2
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semiconductor substrate
layer
opening
insulating film
via hole
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Japanese (ja)
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JP2007311584A (ja
JP2007311584A5 (https=
Inventor
彰 鈴木
克行 関
工次郎 亀山
貴弘 及川
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On Semiconductor Trading Ltd
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Priority to JP2006139693A priority Critical patent/JP4812512B2/ja
Priority to TW096116589A priority patent/TWI365508B/zh
Priority to US11/802,107 priority patent/US8669183B2/en
Priority to KR1020070048736A priority patent/KR100864777B1/ko
Priority to EP07010073A priority patent/EP1858063A3/en
Priority to CN200710104155XA priority patent/CN101075554B/zh
Publication of JP2007311584A publication Critical patent/JP2007311584A/ja
Publication of JP2007311584A5 publication Critical patent/JP2007311584A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H10P50/244—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials comprising alternated and repeated etching and passivation steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP2006139693A 2006-05-19 2006-05-19 半導体装置の製造方法 Expired - Fee Related JP4812512B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2006139693A JP4812512B2 (ja) 2006-05-19 2006-05-19 半導体装置の製造方法
TW096116589A TWI365508B (en) 2006-05-19 2007-05-10 Manufacturing method of semiconductor device
KR1020070048736A KR100864777B1 (ko) 2006-05-19 2007-05-18 반도체 장치의 제조 방법
US11/802,107 US8669183B2 (en) 2006-05-19 2007-05-18 Manufacturing method of semiconductor device
EP07010073A EP1858063A3 (en) 2006-05-19 2007-05-21 Manufacturing method of semiconductor device
CN200710104155XA CN101075554B (zh) 2006-05-19 2007-05-21 半导体装置的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006139693A JP4812512B2 (ja) 2006-05-19 2006-05-19 半導体装置の製造方法

Publications (3)

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JP2007311584A JP2007311584A (ja) 2007-11-29
JP2007311584A5 JP2007311584A5 (https=) 2009-06-25
JP4812512B2 true JP4812512B2 (ja) 2011-11-09

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JP2006139693A Expired - Fee Related JP4812512B2 (ja) 2006-05-19 2006-05-19 半導体装置の製造方法

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US (1) US8669183B2 (https=)
EP (1) EP1858063A3 (https=)
JP (1) JP4812512B2 (https=)
KR (1) KR100864777B1 (https=)
CN (1) CN101075554B (https=)
TW (1) TWI365508B (https=)

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EP1858063A2 (en) 2007-11-21
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EP1858063A3 (en) 2010-04-28
US8669183B2 (en) 2014-03-11
US20070281474A1 (en) 2007-12-06
KR100864777B1 (ko) 2008-10-22
TWI365508B (en) 2012-06-01
CN101075554B (zh) 2010-06-16
TW200802713A (en) 2008-01-01
KR20070112059A (ko) 2007-11-22

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