CN101911257B - 在阻挡层上具有钌电镀层的ulsi微细配线构件 - Google Patents

在阻挡层上具有钌电镀层的ulsi微细配线构件 Download PDF

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CN101911257B
CN101911257B CN2009801015815A CN200980101581A CN101911257B CN 101911257 B CN101911257 B CN 101911257B CN 2009801015815 A CN2009801015815 A CN 2009801015815A CN 200980101581 A CN200980101581 A CN 200980101581A CN 101911257 B CN101911257 B CN 101911257B
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关口淳之辅
伊森彻
木名濑隆
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JX Nippon Mining and Metals Corp
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Abstract

本发明的目的是提供具有尤其是通孔和沟槽内侧壁的可达范围充分，与表面部的膜厚也均匀，并且杂质浓度少的种子层的ULSI微细配线构件。另外本发明的目的是还提供利用该种子层并通过接下来的电镀铜来形成没有空隙发生的微细配线的ULSI微细配线构件、其形成方法和形成有该ULSI微细配线的半导体晶片。本发明的ULSI微细配线构件具有基材和在基材上形成的ULSI微细配线，该ULSI微细配线具有在基材上形成的阻挡层和在该阻挡层上形成的钌电镀层。本发明提供将该钌层作为种子层形成了铜电镀层的ULSI微细配线构件及其形成方法。

Description

在阻挡层上具有钌电镀层的ULSI微细配线构件
技术领域
本发明涉及在基材上形成的ULSI微细配线的阻挡层上具有采用电镀法成膜的用作为种子层的钌层的ULSI微细配线构件、其形成方法和形成有ULSI微细配线的半导体晶片。
背景技术
作为ULSI(超大规模集成电路；ultra-large scale integration)微细铜配线(大马士革铜配线；damascene copper wiring)的铜的成膜方法，已知通过无电解镀铜设置种子层(籽晶层；seed layer)，通过电镀铜来形成铜膜的方法。
然而，在如半导体晶片那样的镜面上进行无电解镀铜的场合，析出的镀膜难以获得充分的粘附性。并且，镀层的反应性低，也难以在基板整个面上进行均匀的镀覆。过去，在采用例如无电解镀法在氮化钽等的阻挡金属层上形成铜种子层的场合，存在难以均匀地形成镀层且粘附力不充分的问题。
本发明者们已发现：在无电解镀铜液中加入作为添加剂的重均分子量(Mw)小的水溶性含氮聚合物，另一方面在镀液浸渍前使催化剂金属附着在被镀物的基板上，或者预先在最表面上将催化剂金属进行成膜后，通过浸渍在镀液中借助于氮原子使聚合物吸附在该催化剂金属上可抑制镀层的析出速度，并且晶体非常微细化，能够在如晶片那样的镜面上形成膜厚15nm以下的均匀薄膜(专利文献1)。
另外，本发明者在上述发明的实施例中还公开了：预先在最表面上将催化剂金属进行成膜后，通过浸渍在镀液中借助于氮原子使聚合物吸附在该催化剂金属上可抑制镀层的析出速度，并且晶体非常微细化，能够在如晶片那样的镜面上形成膜厚6nm以下的均匀的薄膜。
在这样的方法中，即在大马士革铜配线形成中，在将催化剂金属进行成膜后通过无电解镀设置铜种子层的场合，需要与催化剂金属层不同地预先形成用于防止铜扩散的阻挡层，因此，在成膜出铜种子层前将形成阻挡层和催化剂金属层这两层的层，所以判明对于不能够增厚膜厚的超微细配线而言存在难以适用于实际工序的问题。
另外，对于电子构件而言希望降低膜中的杂质浓度，但在采用CVD(化学气相沉积)法、尤其是ALD(原子层沉积)法、无电解镀法形成的膜中有机物的杂质浓度高，碳浓度超过100重量ppm。该杂质产生提高电阻、阻碍电镀铜时电的均匀流动、发生镀覆不均匀等的不良情况。
专利文献1：日本特开2008-223100号报公报
发明内容
本发明是解决这样的问题的发明，其目的在于提供能够膜厚均匀地形成种子层，尤其是通孔和沟槽内侧壁的可达范围也能够充分地成膜，与表面部的膜厚均匀，并且杂质浓度少的种子层。另外，其目的在于提供利用该种子层并通过接下来的电镀铜以均匀的膜厚形成没有空隙(voids)发生的微细配线的ULSI微细配线构件、其形成方法和形成有该ULSI微细配线的半导体晶片。
本发明者们潜心进行研究的结果发现，采用电镀法在ULSI微细配线的阻挡层上形成的钌镀层具有均匀的膜厚，并且杂质少，还发现通过使用其本身作为种子层能够解决上述课题，从而完成了本发明。
即，本发明涉及以下的发明。
(1)一种ULSI微细配线构件，具有基材和在基材上形成的ULSI微细配线，其特征在于，该ULSI微细配线至少具有在基材上形成的阻挡层和在该阻挡层上形成的钌电镀层。
(2)根据(1)所述的ULSI微细配线构件，其特征在于，将上述钌电镀层作为种子层，在其上形成了铜电镀层。
(3)根据(1)或(2)所述的ULSI微细配线构件，其特征在于，上述ULSI微细配线的阻挡层包含选自钨、钼和铌中的1种或2种以上的金属元素。
(4)根据(1)～(3)的任一项所述的ULSI微细配线构件，其特征在于，上述钌电镀层的作为杂质含有的碳是100重量ppm以下。
(5)根据(1)～(4)的任一项所述的ULSI微细配线构件，其特征在于，上述基材是硅基板。
(6)根据(1)～(5)的任一项所述的ULSI微细配线构件，其特征在于，上述ULSI微细配线是大马士革铜配线。
(7)一种ULSI微细配线的形成方法，其特征在于，至少在基材上形成阻挡层并在其上形成钌电镀层。
(8)根据(7)所述的ULSI微细配线的形成方法，其特征在于，将上述钌电镀层作为种子层，在其上形成铜电镀层。
(9)根据(7)或(8)所述的ULSI微细配线的形成方法，其特征在于，上述ULSI微细配线的阻挡层包含选自钨、钼和铌中的1种或2种以上的金属元素。
(10)根据(7)～(9)的任一项所述的ULSI微细配线的形成方法，其特征在于，上述钌电镀层的作为杂质含有的碳是100重量ppm以下。
(11)根据(7)～(10)的任一项所述的ULSI微细配线的形成方法，其特征在于，上述基材是硅基板。
(12)根据(7)～(11)的任一项所述的ULSI微细配线的形成方法，其特征在于，上述ULSI微细配线是大马士革铜配线。
(13)一种采用(7)～(12)的任一项所述的方法形成了ULSI微细配线的半导体晶片。
采用电镀法在本发明的阻挡层上形成的镀钌层，杂质少能够使碳浓度为100重量ppm以下，并且能够使膜厚均匀，尤其是通孔和沟槽内侧壁的可达范围也能够充分地成膜，与表面部的膜厚均匀。并且，将该钌层作为种子层使用的大马士革铜配线能够形成没有空隙的铜微细配线。
此外，由于钌具有阻挡性，因此通过设置镀钌层能够强化阻挡能力。另外，由于采用电镀法形成钌层并能够作为种子层使用，因此在通过无电解镀形成种子层时不需要形成催化剂层，能够减少该部分膜厚。
具体实施方式
本发明中使用的阻挡层，优选包含选自钨、钼和铌中的1种或2种以上的金属元素。特别优选为钨。
该阻挡层的形成，可以采用溅射、CVD、ALD等公知的方法进行，没有特别的限定，但优选溅射成膜。另外，在通孔和沟槽内侧壁优选膜厚为1～10nm。
本发明中重要的是采用电镀法在该阻挡层上形成钌层。该钌层膜厚均匀性优异。该钌层在大马士革配线中线宽100nm以下的微细配线时即使是通孔和沟槽内侧壁也能够在充分的可达范围成膜，表面部与通孔和沟槽内侧壁的膜厚的均匀性优异，能够使其间的偏差降到小于20％。
再者，由于钌层采用电镀法形成，因此沟槽侧壁与沟槽底部的钌层的膜厚大致相同。所以，关于膜厚均匀性，求出了表面部与通孔和沟槽内侧壁的膜厚的偏差，但表面部与沟槽底部的钌层的膜厚也均匀，因此偏差也同样。
上述阻挡层和钌层的表面部以及通孔和沟槽内侧壁的膜厚可以通过剖面FIB加工-TEM观察来进行测定。钌层的表面部与通孔和沟槽内侧壁之间的膜厚的偏差，是通过表面部膜厚与通孔和沟槽内侧壁的膜厚之差除以表面部膜厚而得到的值，表面部膜厚、通孔和沟槽内侧壁的膜厚，是测定表面部、通孔和沟槽内侧壁的各自的任意的3点的膜厚而求出的平均值。
即使代替电镀法通过溅射来形成上述钌层，也与采用电镀法形成的钌层不同，不能够均匀地形成膜厚，通孔和沟槽内侧壁可达范围不够，其结果具有下述缺陷：表面部与内侧壁的膜厚的偏差超过20％，或整体上膜厚不均匀，或者在其后的电镀时产生空隙等等。
另外，当要增厚通孔和沟槽内侧壁的膜厚时，表面部的膜厚变得非常厚，通孔和沟槽入口附近引起缩颈而变窄，在其后的电镀时会产生空隙。
另外，本发明的利用电镀法形成的钌层，杂质浓度低，作为碳含有的量是100重量ppm以下。与此相对，利用无电解镀法或ALD法形成的钌层，其杂质多，碳含量超过100重量ppm，因此在电镀铜时不能够使电均匀地流动，在整体上产生不均。
再者，在本发明中，钌层中的碳含量使用二次离子质量分析计(SIMS)进行测定。
另外，由于钌也具有阻挡性，因此钌层也有增强阻挡能力的效果。
此外，由于通过电镀形成钌层，因此在通过无电解镀形成种子层时不需要形成催化剂层，也能够减少该部分膜厚。
作为采用电镀法形成钌层时所使用的镀液、镀覆条件，可以是公知的一般的电镀钌液、镀覆条件，例如，作为镀钌液，使用钌络盐的镀液、使用氯化钌的镀液、使用硫酸钌的镀液中的任一种都可使用。作为镀液，可以优选使用W-Ru·2(使用硫酸钌，日矿商事公司制)等，在电流密度0.1～10A/dm2下进行镀覆，优选在表面部以及通孔和沟槽内侧壁形成膜厚5～15nm的钌层。
另外，本发明中使用的基材也可以使用公知的基材，没有特别的限制，但优选硅基板。通过对基材实施酸处理、碱处理、表面活性剂处理、超声波清洗或将这些处理组合了的处理，能够谋求基材的清洁、润湿性提高。
在本发明中如以上所述，在采用电镀法形成的钌层上，再通过电镀设置ULSI微细铜配线，能够制成为ULSI微细配线构件。钌层镀膜薄、膜厚均匀。因此，作为大马士革铜配线用种子层使用的场合，能够得到不发生空隙和缝等缺陷的半导体晶片。
配线部优选是铜或以铜为主成分的合金，更优选为铜。电镀铜液一般地只要是在埋入大马士革铜配线用途中使用的组成即可，没有特别的限定，例如可以使用含有作为主成分的硫酸铜以及硫酸、作为微量成分的氯、聚乙二醇、二硫化双(3-磺丙基)二钠、烟鲁绿等的液体。
实施例
以下通过实施例说明本发明，但本发明不受这些实施例限定。
关于在以下的实施例1～3和比较例1～4中成膜的铜，通过沟槽部剖面TEM观察来分别实施埋入沟槽内后的空隙确认，另外通过AES深度分布测定来实施了在400℃下进行30分钟真空退火后的阻挡性确认。
实施例1
采用溅射在带有线宽90nm、深度300nm的沟槽的硅基板上形成钨膜(沟槽内侧壁膜厚5nm)，在其上面实施电镀钌(沟槽内侧壁膜厚10nm)，再在其上面实施埋入用电镀铜(表面部膜厚450nm)。
钨溅射是在氩气压力0.8Pa、50W的输出功率下发生等离子体，预溅射15分钟后进行实施。
电镀钌液使用日矿商事(株)制的W-Ru·2，镀覆条件为：钌浓度5g/L、pH1.2、浴温60℃、电流密度0.2A/dm2，实施17秒钟。另外，电镀铜液的组成是：硫酸铜0.25mol/L，硫酸1.8mol/L、盐酸1.4mmol/L、微量添加剂(二硫化双(3-磺丙基)二钠、聚乙二醇、烟鲁绿)，镀覆条件是：浴温25℃，在电流密度0.2A/dm2下实施20秒钟，然后在1A/dm2下实施120秒钟。
对于钌电镀层，表面部与沟槽内侧壁之间的膜厚偏差为15％，没有空隙，析出也均匀，也没有发现其后的通过电镀铜进行的沟槽内埋入后的空隙发生。另外，沟槽内侧壁的阻挡性通过形成钌膜而被强化，阻挡性也没有问题。钌层中的碳含量是30重量ppm。
实施例2
采用溅射在带有线宽90nm、深度300nm的沟槽的硅基板上形成钼膜(沟槽内侧壁膜厚5nm)，在其上面实施电镀钌(沟槽内侧壁膜厚10nm)，再在其上面实施埋入用电镀铜(表面部膜厚450nm)。
钼溅射是在氩气压力0.8Pa、50W的输出功率下发生等离子体，预溅射15分钟后进行实施。
电镀钌液和电镀铜液的组成、镀覆条件与实施例1相同。
对于钌电镀层，表面部与沟槽内侧壁之间的膜厚偏差为17％，没有空隙，析出也均匀，也没有发现其后的通过电镀铜进行的沟槽内埋入后的空隙发生。
另外，沟槽内侧壁的阻挡性通过形成钌膜而被强化，阻挡性也没有问题。钌层中的碳含量是20重量ppm。
实施例3
采用溅射在带有线宽90nm、深度300nm的沟槽的硅基板上形成铌膜(沟槽内侧壁膜厚5nm)，在其上面实施电镀钌(沟槽内侧壁膜厚10nm)，再在其上面实施埋入用电镀铜(表面部膜厚450nm)。
铌溅射是在氩气压力0.8Pa、50W的输出功率下发生等离子体，预溅射15分钟后进行实施。
电镀钌液和电镀铜液的组成、镀覆条件与实施例1相同。
对于钌电镀层，表面部与沟槽内侧壁之间的膜厚偏差为18％，没有空隙，析出也均匀。也没有发现其后的通过电镀铜进行的沟槽内埋入后的空隙发生。
另外，沟槽内侧壁的阻挡性通过形成钌膜而被强化，阻挡性也没有问题。钌层中的碳含量是25重量ppm。
比较例1
采用溅射在带有线宽90nm。深度300nm的沟槽硅基板上将钨成膜(沟槽内侧壁膜厚5nm)，在其上面直接实施电镀铜(表面部膜厚450nm)。钨溅射在氩气压0.8Pa、50W的输出功率下发生等离子体，加压溅射15分钟后进行实施。电镀铜液的组成、电镀条件与实施例1相同。没有种子层而直接实施电镀铜的场合，初期电镀铜的析出均匀，即使原样不动地直接埋置沟槽内也没有空隙发生，但沟槽内侧壁的阻挡层只是钨且非常薄，因此不能够充分地确保阻挡性。
比较例2
采用溅射在带有线宽90nm、深度300nm的沟槽的硅基板上形成钨膜(沟槽内侧壁膜厚5nm)，在该钨膜上采用溅射形成钌膜(沟槽内侧壁膜厚10nm)，再在该钌膜上实施埋入用电镀铜(表面部膜厚450nm)。钨溅射和钌溅射，是在氩气压力0.8Pa、50W的输出功率下发生等离子体，预溅射15分钟后进行实施。电镀铜液的组成、镀覆条件与实施例1相同。以沟槽内侧壁膜厚10nm为目标实施了钌溅射，表面部膜厚变成数十nm，沟槽入口附近引起缩颈，变得非常窄。在该状态下实施了电镀铜，沟槽内在被埋入前入口堵塞，发生空隙。
比较例3
采用溅射在带有线宽90nm、深度300nm的沟槽的硅基板上形成铌膜(沟槽内侧壁膜厚5nm)，在该铌膜上采用ALD法形成钌膜(沟槽内侧壁膜厚10nm)，再在该钌膜上实施埋入用电镀铜(表面部膜厚450nm)。钨溅射是在氩气压力0.8Pa、50W的输出功率下发生等离子体，预溅射15分钟后进行实施。对于钌的ALD，使用乙基环戊二烯基钌和氨气作为原料，实施了等离子体ALD成膜。电镀铜液的组成、镀覆条件与实施例1相同。对于钌的ALD膜，杂质浓度高，尤其是碳高为200重量ppm，因此电阻高，其结果在电镀铜时电不均匀地流动，在整体上镀膜变得不均匀。并且沟槽内也发生了空隙。
比较例4
采用溅射在带有线宽90nm、深度300nm的沟槽的硅基板上形成钨膜(沟槽内侧壁膜厚5nm)，在该钨膜上实施无电解镀钌(沟槽内侧壁膜厚10nm)，进而在该钌膜上实施埋入用电镀铜(表面部膜厚450nm)。钨溅射是在氩气压力0.8Pa、50W的输出功率下发生等离子体，预溅射15分钟后进行实施。对于无电解镀钌，使用钌的亚硝酰氨配位化合物基础的肼还原镀液进行实施。电镀铜液的组成、镀覆条件与实施例1相同。无电解镀钌膜其杂质浓度高，尤其是碳高为150重量ppm，因此电阻高，其结果在电镀铜时电不均匀地流动，在整体上镀膜变得不均匀。并且沟槽内也发生了空隙。
本发明中表示数值范围的“以上”和“以下”均包括本数。

Claims (13)

1.一种ULSI微细配线构件，具有基材和在基材上形成的ULSI微细配线，其特征在于，该ULSI微细配线至少具有在基材上形成的阻挡层和在该阻挡层上作为种子层形成的钌电镀层。
2.根据权利要求1所述的ULSI微细配线构件，其特征在于，在所述钌电镀层上形成了铜电镀层。
3.根据权利要求1或2所述的ULSI微细配线构件，其特征在于，所述ULSI微细配线的阻挡层包含选自钨、钼和铌中的1种或2种以上的金属元素。
4.根据权利要求1或2所述的ULSI微细配线构件，其特征在于，所述钌电镀层的作为杂质而含有的碳为100重量ppm以下。
5.根据权利要求1或2所述的ULSI微细配线构件，其特征在于，所述基材是硅基板。
6.根据权利要求1或2所述的ULSI微细配线构件，其特征在于，所述ULSI微细配线为大马士革铜配线。
7.一种ULSI微细配线的形成方法，其特征在于，至少在基材上形成阻挡层并在该阻挡层上作为种子层形成钌电镀层。
8.根据权利要求7所述的ULSI微细配线的形成方法，其特征在于，在所述钌电镀层上形成铜电镀层。
9.根据权利要求7或8所述的ULSI微细配线的形成方法，其特征在于，所述ULSI微细配线的阻挡层包含选自钨、钼和铌中的1种或2种以上的金属元素。
10.根据权利要求7或8所述的ULSI微细配线的形成方法，其特征在于，所述钌电镀层的作为杂质而含有的碳为100重量ppm以下。
11.根据权利要求7或8所述的ULSI微细配线的形成方法，其特征在于，所述基材是硅基板。
12.根据权利要求7或8所述的ULSI微细配线的形成方法，其特征在于，所述ULSI微细配线是大马士革铜配线。
13.一种半导体晶片，采用权利要求7～12的任一项所述的方法形成了ULSI微细配线。
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