TWI384553B - 在阻障層上具有釕（Ｒｕ）電鍍層之ＵＬＳＩ微細配線構件 - Google Patents

在阻障層上具有釕（Ｒｕ）電鍍層之ＵＬＳＩ微細配線構件 Download PDF

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TWI384553B
TWI384553B TW098101008A TW98101008A TWI384553B TW I384553 B TWI384553 B TW I384553B TW 098101008 A TW098101008 A TW 098101008A TW 98101008 A TW98101008 A TW 98101008A TW I384553 B TWI384553 B TW I384553B
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fine wiring
layer
ulsi fine
plating
ulsi
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Junnosuke Sekiguchi
Toru Imori
Takashi Kinase
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Nippon Mining Co
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Description

在阻障層上具有釕(Ru)電鍍層之ULSI微細配線構件
本發明是有關形成在基材上之ULSI微細配線的阻障層上，具有藉由電鍍法形成釕層薄膜作為晶種層使用之ULSI微細配線構件，其形成方法，及形成ULSI微細配線之半導體晶圓。
ULSI微細銅配線(鑲嵌(Damascene)銅配線)之銅的成膜方法，已知有由銅之無電解電鍍來設置晶種層、再藉由銅電鍍之銅成膜方法。
然而，在如半導體晶圓那種鏡面上進行銅之無電解電鍍時，析出之電鍍膜很難得到有充分之密著性。同時，電鍍之反應性低，很難在基板全面進行均勻的電鍍。以往，例如在氮化鉭等阻障金屬層上以無電解電鍍法形成銅晶種層時，有很難形成均勻之電鍍、密著力不充分之問題。
本案發明人等，發現在銅之無電解電鍍液中加入重量平均分子量(Mw)小的水溶性含氮聚合物作為添加劑，另一方面，在被電鍍物之基板上於浸漬電鍍液前使附著觸媒金屬，或將觸媒金屬預先在最表面成膜後浸漬於電鍍液，使該觸媒金屬上經由氮原子吸附聚合物，可以抑制電鍍之析出速度，並且使結晶非常微細化，在如晶圓般之鏡面上可以形成膜厚15nm以下之均勻薄膜(專利文獻1)。同時，本案發明人等，於前述發明之實施例中，將觸媒金屬預先成膜在最表面後，浸漬於電鍍液，使該觸媒金屬上隔著氮原子吸著聚合物，結果顯示可抑制電鍍之析出速度，並且使結晶非常微細化，可以在如晶圓般之鏡面上形成膜厚6nm以下之均勻薄膜。
如此之方法，亦即在鑲嵌(Damascene)銅配線形成中，於觸媒金屬成膜後藉由無電解電鍍設置銅晶種層時，用以防止銅擴散的阻障層必需與觸媒金屬層分別預先形成，因此，在銅晶種層成膜前，為了需要形成阻障層與觸媒金屬層等二層，故可知對膜厚不可太厚的超微細配線而言，對實際工程之應用上有其困難之問題。
又，在電子構件中，雖期望膜中之雜質濃度降低，但藉由CVD(化學氣相成長)法，尤其是由ALD(原子層沈積)法或無電解電鍍法所形成之膜中，有機物的雜質濃度高，碳濃度超過100wtppm。此雜質會提高電阻阻礙銅電鍍時電流的均勻流通，而會產生電鍍斑駁不均等不良情形。
專利文獻1：日本特開2008-223100號公報
本發明是用以解決如此問題者，其目的在提供可以形成均勻之晶種層膜厚，尤其是在介層孔/溝槽內側壁之也可以充分覆蓋成膜，而且與表面部之膜厚可以一致，並且雜質濃度低之晶種層。同時，以提供利用該晶種層藉由繼續進行銅電鍍而以均勻膜厚形成不會發生孔洞的微細配線之ULSI微細配線構件、其形成方法、以及形成該ULSI微細配線之半導體晶圓作為目的。
本案發明人等，經過努力研究檢討結果發現，在ULSI微細配線之阻障層上藉由電鍍法形成之釕(Ru)電鍍層具有均勻之膜厚、並且雜質少，再者將其作為薄片層利用可以解決前述之課題，遂而完成本發明。
亦即，本發明是有關：
(1)一種ULSI微細配線構件，其特徵為：在具有基材以及形成在基材上之ULSI微細配線之ULSI微細配線構件中，該ULSI微細配線至少具有形成在基材上的阻障層及形成在其上之釕(Ru)電鍍層。
(2)如前述(1)之ULSI微細配線構件，其中，將前述釕電鍍層作為晶種層，且在其上形成銅電鍍層者。
(3)如前述(1)或(2)之ULSI微細配線構件，其中，前述ULS1微細配線之阻障層為選自鎢、鉬、以及鈮中之1種或2種以上金屬元素所構成者。
(4)如前述(1)至(3)中任一項之ULSI微細配線構件，其中，作為前述釕電鍍層之雜質而含有之碳量係在100wtppm以下。
(5)如前述(1)至(4)中任一項之ULSI微細配線構件，其中，前述基材為矽基板者。
(6)如前述(1)至(5)中任一項之ULSI微細配線構件，其中，前述ULSI微細配線為鑲嵌銅配線者。
(7)一種ULSI微細配線之形成方法，其特徵為：至少在基材上形成阻障層，且在其上形成釕電鍍層。
(8)如前述(7)之ULSI微細配線之形成方法，其中，將前述釕電鍍層作為晶種層，再在其上形成銅電鍍層者。
(9)如前述(7)或(8)之ULSI微細配線之形成方法，其中，前述ULSI微細配線之阻障層為選自鎢、鉬、以及鈮中之1種或2種以上金屬元素所構成者。
(10)如前述(7)至(9)中任一項之ULSI微細配線之形成方法，其中，作為前述釕電鍍層之雜質而含有之碳量係在100wtppm以下。
(11)如前述(7)至(10)中任一項之ULSI微細配線形成方法，其中，前述基材為矽基板者。
(12)如前述(7)至(11)中任一項之ULSI微細配線形成方法，其中，前述ULSI微細配線為鑲嵌銅配線者。
(13)一種半導體晶圓，係藉由前述(7)至(12)中任一項之方法形成ULSI微細配線者。
在本發明之阻障層上，藉由電鍍法形成之釕電鍍層，係雜質少、可使碳量濃度在100wtppm以下、膜厚均勻、尤其介層孔/溝槽內側壁也可充分覆蓋成膜、而且可與表面部之膜厚一致。因此，將此釕層作為晶種層使用之鑲嵌銅配線中，可形成無孔洞之銅微細配線。
再者，因為釕有阻隔性，藉由設置釕電鍍層可以強化阻障能力。同時，可藉由電鍍法形成釕層，當作晶種層使用，故以無電解電鍍形成晶種層時，沒有必要形成觸媒層，可以減薄該部分之膜厚。
 (發明之最佳實施形態)
在本發明中使用之阻障層，最好是由選自鎢、鉬、及鈮中之1種或2種以上金屬元素所構成，尤其以鎢為佳。
此阻障層之形成，可以藉由濺鍍、CVD、ALD等習知之手段進行，並無特別限制，而以藉由濺鍍成膜為佳。同時，膜厚在介層孔/溝槽內側壁以1至10nm為佳。
在本發明中，於此阻障層上藉由電鍍法形成釕層至為重要。此釕層的膜厚均勻性優異。此釕層在鑲嵌配線上，線幅100nm以下之微細配線，在介層孔/溝槽內側壁也可以充分覆蓋成膜，表面部與介層孔/溝槽內側壁之膜厚均勻性優異，其間之偏差可以降低到20%以下。
尚且，釕層因是藉由電鍍法形成，故溝槽側壁與溝槽底部之釕層膜厚幾乎相同。因此，有關膜厚均勻性方面，經調查表面部與介層孔/溝槽內側壁之膜厚偏差的結果，表面部與溝槽底部之釕層膜厚是均勻的，偏差也相同。
在上述阻障層及釕層之表面部及介層孔/溝槽內側壁的膜厚，可以藉由剖面FIB加工/TEM觀察來測定。釕層之表面部及介層孔/溝槽內側壁之膜厚偏差，係由表面部膜厚與介層孔/溝槽內側壁之膜厚的差除以表面部膜厚而求得之值，表面部膜厚、介層孔/溝槽內側壁之膜厚，係分別測定表面部、介層孔/溝槽內側壁各任意3點之膜厚而求得之平均值。
即使藉由濺鍍法取代形成前述釕層之電鍍法形成與電鍍法不同膜厚之釕層，也不可能形成均勻之膜厚，介層孔/溝槽內側壁之覆蓋變成不足，結果表面部與內側壁之膜厚偏差會超過20%，形成具有整體之膜厚不均勻、或是在後續的電鍍時產生孔洞等缺陷之產品。
同時，擬增加介層孔/溝槽內側壁之膜厚時，表面部之膜厚會變得非常厚，介層孔/溝槽入口附近會產生縮頸(necking)而變狹窄，後續電鍍時還是會產生孔洞。
本發明藉由電鍍法形成之釕層的雜質濃度低，碳含量在100wtppm以下。相對於此，藉由無電解電鍍法或ALD法形成之釕層的雜質多，碳量超過100wtppm，因此進行銅電鍍時電流無法均勻流動而使全體產生斑駁不均。
此外，本發明之釕層中的碳原子量，是藉由二次離子質量分析計(SIMS)來測定。
又，因為釕有阻隔性，故釕層也有補強阻障功能之效果。
再者，因藉由電鍍形成釕層，故無必要形成藉無電解電鍍形成晶種層時的觸媒層，使此部分之膜厚可以變薄。
在藉由電鍍法形成釕層時使用之電鍍液、電鍍條件，可以是習知之一般釕電鍍液、電鍍條件，例如，以釕電鍍液而言，可以是使用釕錯鹽、使用氯化釕、使用硫酸釕中之任何一種電鍍液。可以使用W-Ru‧2(使用硫酸釕，日礦商事製造)等作為電鍍液為佳，以電流密度0.1至10A/dm2 來進行電鍍，在表面部與介層孔/溝槽內側壁以形成膜厚5至15nm之釕層為佳。
使用在本發明之基材也可以使用習知者，而無特別限制，但以矽基板為佳。將其經過酸處理、鹼處理、界面活性劑處理、超音波洗淨或此等之組合處理，可望提高基材之清潔性、濕濡性。
在本發明中，如上述，可於藉由電鍍法形成之釕層上，再由電鍍法設置ULSI微細銅配線，作為ULSI微細配線構件。釕層之電鍍膜很薄、膜厚均勻。因此，作為鑲嵌銅配線用晶種層使用時，可以得到不會產生孔洞/隙縫等缺陷之半導體晶圓。
配線部以銅或以銅作為主成分之合金為佳，以銅為更佳。銅電鍍液，只要是一般在鑲嵌銅配線埋入中所使用之組成即可，無特別限定，例如，可以使用含有作為主成分的硫酸銅及硫酸、作為微量成分的氯氣、聚乙二醇、二硫化雙(3-磺丙基)二鈉、耶奴斯綠(Janus green)等之液體。
[實施例]
其次，藉由實施例說明本發明，但本發明並不侷限於此等實施例。
關於在以下之實施例1至3及比較例1至4成膜之銅，各個溝槽內埋入後之孔洞確認係藉由TEM觀察溝槽部剖面來進行，同時在400℃30分鐘真空退火後之阻隔性確認是藉由AES縱深分佈分析(depth profile)來測定。
[實施例1]
在線寬90nm、深度300nm之附有溝槽之矽基板上，以濺鍍使鎢成膜(溝槽內側壁厚5nm)，再在其上進行釕之電鍍(溝槽內側壁膜厚10nm)，進一步在其上進行埋入用銅之電鍍(表面部膜厚450nm)。
鎢濺鍍是在氬氣壓0.8Pa、50W輸出下使發生電漿，先經15分鐘預濺鍍後，再進行鎢濺鍍。
釕電鍍液是使用日礦商事(股)公司製造之W-Ru‧2，電鍍條件為釕濃度5g/L、pH 1.2、浴溫60℃、電流密度0.2A/dm2 進行17秒鐘。同時，銅電鍍液之組成是硫酸銅0.25mol/L、硫酸1.8mol/L、鹽酸1.4mmol/L、以及微量添加劑(二硫化雙(3-磺丙基)二鈉、聚乙二醇、耶奴斯綠)，電鍍條件為浴溫25℃、電流密度0.2A/dm2 進行20秒鐘，然後再以1A/dm2 進行120秒鐘。
釕電鍍層之表面部與溝槽內側壁間的膜厚斑駁不均為15%，無孔洞而析出均勻，藉由隨後之銅電鍍進行溝槽內埋入後也未發現孔洞。同時，溝槽內側壁之阻隔性因釕之成膜而被強化，阻隔性也沒有問題。釕層中之碳量為30wtppm。
[實施例2]
在線寬90nm、深度300nm之附有溝槽之矽基板上，使鉬濺鍍成膜(溝槽內側壁膜厚5nm)，再在其上進行釕之電鍍(溝槽內側壁膜厚10nm)，進一步在其上進行埋入用銅之電鍍(表面部膜厚450nm)。
鉬濺鍍是在氬氣壓0.8Pa、50W輸出下使發生電漿，先經15分鐘之預濺鍍後，再進行鉬濺鍍。
釕電鍍液及銅電鍍液之組成、電鍍條件都與實施例1相同。
釕電鍍層之表面部與溝槽內側壁間的膜厚偏差為17%，無孔洞而析出也均勻，藉由隨後之銅電鍍進行溝槽內埋入後也未發現孔洞。
同時，溝槽內側壁之阻隔性因釕之成膜而被強化，阻隔性也沒有問題。釕層中之碳量為20wtppm。
[實施例3]
在線寬90nm、深度300nm之附有溝槽之矽基板上，使鈮濺鍍成膜(溝槽內側壁膜厚5nm)，再在其上進行釕之電鍍(溝槽內側壁膜厚10nm)，進一步在其上進行埋入用銅之電鍍(表面部膜厚450nm)。
鈮濺鍍是在氬氣壓0.8Pa、50W輸出下使發生電漿，先經15分鐘之預濺鍍後，再進行鈮濺鍍。
釕電鍍液及銅電鍍液之組成、電鍍條件都與實施例1相同。
釕電鍍層之表面部與溝槽內側壁間的膜厚偏差為18%，無孔洞而析出均勻，藉由隨後之銅電鍍進行溝槽內埋入後也未發現孔洞。
同時，溝槽內側壁之阻隔性因釕之成膜而被強化，阻隔性也沒有問題。釕層中之碳量為25wtppm。
[比較例1]
在線寬90nm、深度300nm之附有溝槽之矽基板上，使鎢濺鍍成膜(溝槽內側壁膜厚5nm)，再在其上直接進行銅之電鍍(表面部膜厚450nm)。鎢濺鍍是在氬氣壓0.8Pa、50W輸出下使發生電漿，先經15分鐘之預濺鍍後，再進行鎢濺鍍。
銅電鍍液之組成、電鍍條件都與實施例1相同。沒有晶種層而直接實施銅之電鍍時，初期之電鍍銅的析出均勻，將其直接埋入溝槽內也未見孔洞產生，但溝槽內側壁之阻隔層因只有鎢，非常薄，故阻隔性不能充分確保。
[比較例2]
在線寬90nm、深度300nm之附有溝槽之矽基板上，使鎢濺鍍成膜(溝槽內側壁膜厚5nm)，再在其上進行釕之濺鍍成膜(溝槽內側壁膜厚10nm)，進一步在其上進行埋入用銅之電鍍(表面部膜厚450nm)。
鎢濺鍍及釕濺鍍是在氬氣壓0.8Pa、50W之輸出下使發生電漿，先經15分鐘之預濺鍍後，再進行鎢及釕之濺鍍。銅電鍍液之組成、電鍍條件都與實施例1相同。以溝槽內側壁之膜厚10nm為目標進行釕濺鍍時，表面部膜厚變成數十nm，溝槽入口附近產生縮頸而變得非常狹窄。在此狀態下進行銅電鍍時，在埋入溝槽內前，入口已被堵塞，因而產生孔洞。
[比較例3]
在線寬90nm、深度300nm之附有溝槽之矽基板上，使鎢濺鍍成膜(溝槽內側壁膜厚5nm)，再在其上使釕以ALD法成膜(溝槽內側壁膜厚10nm)，進一步在其上進行埋入用銅之電鍍(表面部膜厚450nm)。鎢濺鍍是在氬氣壓0.8Pa、50W輸出下使發生電漿，先經15分鐘之預濺鍍後，再進行鎢濺鍍。釕之ALD是使用釕-乙基環戊二烯與氨氣作為原料，進行電漿ALD成膜。銅電鍍液之組成、電鍍條件都與實施例1相同。釕ALD膜之雜質濃度高，尤其因為碳量高達200wtppm，故電阻高，結果進行銅電鍍時電流流動不均勻，全體電鍍變成斑駁不均。同時在溝槽內也產生孔洞。
[比較例4]
在線寬90nm、深度300nm之附有溝槽之矽基板上，使鎢濺鍍成膜(溝槽內側壁膜厚5nm)，再在其上進行釕之無電解電鍍(溝槽內側壁膜厚10nm)，進一步在其上進行埋入用銅之電鍍(表面部膜厚450nm)。鎢濺鍍是在氬氣壓0.8Pa、50W輸出下使發生電漿，先經15分鐘之預濺鍍後，再進行鎢濺鍍。釕之無電解電鍍是使用釕之亞硝基氨錯體基材之聯胺還原電鍍液進行。銅電鍍液之組成、電鍍條件都與實施例1相同。釕之無電解電鍍膜之雜質濃度高，尤其因為碳量高達150wtppm，故電阻高，結果進行銅電鍍時電流流動不均勻，全體電鍍變成斑駁不均。同時在溝槽內也產生孔洞。

Claims (13)

  1. 一種ULSI微細配線構件，其特徵為：在具有基材以及形成在基材上之ULSI微細配線之ULSI微細配線構件中，該ULSI微細配線至少具有形成在基材上的阻障層及形成在其上之釕電鍍層。
  2. 如申請專利範圍第1項之ULSI微細配線構件，其中，將前述釕電鍍層作為晶種層，且在其上形成銅電鍍層者。
  3. 如申請專利範圍第1或2項之ULSI微細配線構件，其中，前述ULSI微細配線之阻障層為由選自鎢、鉬、以及鈮中之1種或2種以上金屬元素所構成者。
  4. 如申請專利範圍第1或2項之ULSI微細配線構件，其中，作為前述釕電鍍層之雜質而含有之碳量係在100wtppm以下者。
  5. 如申請專利範圍第1或2項之ULSI微細配線構件，其中，前述基材為矽基板者。
  6. 如申請專利範圍第1或2項之ULSI微細配線構件，其中，前述ULSI微細配線為鑲嵌銅配線者。
  7. 一種ULSI微細配線之形成方法，其特徵為：至少在基材上形成阻障層，且在其上形成釕電鍍層。
  8. 如申請專利範圍第7項之ULSI微細配線形成方法，其中，將前述釕電鍍層作為晶種層，再在其上形成銅電鍍層者。
  9. 如申請專利範圍第7項或第8項之ULSI微細配線形成 方法，其中，前述ULSI微細配線之阻障層為選自鎢、鉬、以及鈮中之1種或2種以上金屬元素所構成者。
  10. 如申請專利範圍第7或8項之ULSI微細配線形成方法，其中，作為前述釕電鍍層之雜質而含有之碳量係在100wtppm以下者。
  11. 如申請專利範圍第7或8項之ULSI微細配線形成方法，其中，前述基材為矽基板者。
  12. 如申請專利範圍第7或8項之ULSI微細配線形成方法，其中，前述ULSI微細配線為鑲嵌銅配線者。
  13. 一種半導體晶圓，係藉由申請專利範圍第7至12項中任一項之方法形成ULSI微細配線者。
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