JP4377816B2 - 相変化メモリ装置 - Google Patents
相変化メモリ装置 Download PDFInfo
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- JP4377816B2 JP4377816B2 JP2004569564A JP2004569564A JP4377816B2 JP 4377816 B2 JP4377816 B2 JP 4377816B2 JP 2004569564 A JP2004569564 A JP 2004569564A JP 2004569564 A JP2004569564 A JP 2004569564A JP 4377816 B2 JP4377816 B2 JP 4377816B2
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- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/36—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
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- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
- G11C13/0028—Word-line or row circuits
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- G11C13/004—Reading or sensing circuits or methods
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- G11C2013/009—Write using potential difference applied between cell electrodes
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- G11C2213/70—Resistive array aspects
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
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- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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Description
(1)ワード線を共有して上下に隣接するセルアレイの上下に隣接する二つのメモリセル、
(2)ビット線を共有して上下に隣接するセルアレイの上下に隣接する二つのメモリセル、
(3)一つのセルアレイ内でワード線を共有して隣接する二つのメモリセル。
[産業上の利用可能性]
この発明によれば、3次元セルアレイ構成を用いて、大きなマージンをもってデータの読み/書きを可能とした相変化メモリ装置を提供することができる。
Claims (3)
- 基板と、
前記基板上に積層されて、それぞれに相変化により決まる抵抗値をデータとして記憶する複数のメモリセルがマトリクス配列された複数のセルアレイと、
前記複数のセルアレイ内の近接する二つメモリセルにより構成されるペアセルに、その一方を高抵抗値、他方を低抵抗値状態に書き込む書き込み回路と、
前記ペアセルの相補的な抵抗値状態を1ビットデータとして読み出す読み出し回路とを有し、
前記各セルアレイは、互いに平行な複数の第1の配線と、前記第1の配線とは絶縁分離されて第1の配線と交差して配設された複数の第2の配線とを有し、
上下に隣接するセルアレイの間で前記第1の配線と第2の配線の少なくとも一方が共有され、
前記各メモリセルは、前記第1の配線と第2の配線の各交差部に積層されたカルコゲナイドとダイオードを有し、
前記書き込み回路は、前記複数のセルアレイから選択される隣接する複数のメモリセルに対して、選択された第1の配線に負論理書き込みパルスを、選択された第2の配線に正論理書き込みパルスを、書き込むべきデータに応じてそれらのパルスの重なり時間を調整して供給するものである
ことを特徴とする相変化メモリ装置。 - 基板と、
前記基板上に積層されて、それぞれに相変化により決まる抵抗値をデータとして記憶する複数のメモリセルがマトリクス配列された複数のセルアレイと、
前記複数のセルアレイ内の近接する二つメモリセルにより構成されるペアセルに、その一方を高抵抗値、他方を低抵抗値状態に書き込む書き込み回路と、
前記ペアセルの相補的な抵抗値状態を1ビットデータとして読み出す読み出し回路とを有し、
前記複数のセルアレイは、
前記基板上に形成された、互いに平行な複数の第1のビット線、各第1のビット線上に所定ピッチで配列された複数のメモリセル、及びそのメモリセル上に前記第1のビット線と交差する方向に並ぶ複数のメモリセルを共通接続するように配設された複数の第1のワード線を有する第1のセルアレイと、
前記第1のセルアレイと前記第1のワード線を共有して前記第1のセルアレイ上に形成された、前記第1のセルアレイと同じレイアウトで配列された複数のメモリセル、及びそのメモリセル上に前記第1のワード線と交差する方向に並ぶ複数のメモリセルを共通接続するように配設された複数の第2のビット線を有する第2のセルアレイと、
前記第2のセルアレイと前記第2のビット線を共有して前記第2のセルアレイ上に形成された、前記第2のセルアレイと同じレイアウトで配列された複数のメモリセル、及びそのメモリセル上に前記第2のビット線と交差する方向に並ぶ複数のメモリセルを共通接続するように配設された複数の第2のワード線を有する第3のセルアレイと、
前記第3のセルアレイと前記第2のワード線を共有して前記第3のセルアレイ上に形成された、前記第3のセルアレイのメモリセルと同じレイアウトで配列された複数のメモリセル、及びそのメモリセル上に前記第2のワード線と交差する方向に並ぶ複数のメモリセルを共通接続するように配設された複数の第3のビット線を有する第4のセルアレイとを有し、
前記各セルアレイのメモリセルは、前記第1乃至第3のビット線と前記第1及び第2のワード線の各対応する交差部に積層されたカルコゲナイドとダイオードを有し、
前記第1のセルアレイと第2のセルアレイの間で前記第1のワード線を共有して上下に隣接する二つずつのメモリセルにより相補データを記憶するペアセルを構成し、
前記第3のセルアレイと第4のセルアレイの間で前記第2のワード線を共有して上下に隣接する二つずつのメモリセルにより相補データを記憶するペアセルを構成し、
前記書き込み回路は、前記第1乃至第4のセルアレイの積層方向に並ぶ二つのペアセルを構成する4つのメモリセルに対して同時に書き込みを行うものであって、
パルス幅が同じで位相差のある二種のパルスを発生するパルス発生回路と、
前記パルス発生回路が出力する二種のパルスの書き込みデータに応じて決まる組み合わせ論理によって、前記第1乃至第3のビット線に与える負論理書き込みパルスと第1及び第2のワード線に与える正論理書き込みパルスとをその重なり時間を決定して出力する論理ゲート回路と、
この論理ゲート回路から出力される負論理書き込みパルス及び正論理書き込みパルスの少なくとも一方を、書き込みデータが高抵抗値状態である場合に昇圧するパルス昇圧回路とを有する
ことを特徴とする相変化メモリ装置。 - 基板と、
前記基板上に積層されて、それぞれに相変化により決まる抵抗値をデータとして記憶する複数のメモリセルがマトリクス配列された複数のセルアレイと、
前記複数のセルアレイ内の近接する二つメモリセルにより構成されるペアセルに、その一方を高抵抗値、他方を低抵抗値状態に書き込む書き込み回路と、
前記ペアセルの相補的な抵抗値状態を1ビットデータとして読み出す読み出し回路とを有し、
前記各セルアレイは、互いに平行な複数の第1の配線と、前記第1の配線とは絶縁分離されて第1の配線と交差して配設された複数の第2の配線とを有し、
前記各メモリセルは、前記第1の配線と第2の配線の各交差部に積層されたカルコゲナイドとダイオードを有し、
上下に隣接するセルアレイの間で前記第2の配線を共有しており且つ、
上下に隣接するセルアレイの間で前記カルコゲナイドとダイオードの積層順序が逆であり、
各セルアレイの中で、前記第2の配線を共有し且つ異なる第1の配線に接続される隣接する二つのメモリセルによりペアセルを構成する
ことを特徴とする相変化メモリ装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/003256 WO2004084228A1 (en) | 2003-03-18 | 2003-03-18 | Phase change memory device |
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JP2006514392A JP2006514392A (ja) | 2006-04-27 |
JP4377816B2 true JP4377816B2 (ja) | 2009-12-02 |
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US (4) | US20060203541A1 (ja) |
EP (1) | EP1609154B1 (ja) |
JP (1) | JP4377816B2 (ja) |
CN (1) | CN1764982B (ja) |
WO (1) | WO2004084228A1 (ja) |
Families Citing this family (144)
Publication number | Priority date | Publication date | Assignee | Title |
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US7966429B2 (en) * | 2007-05-28 | 2011-06-21 | Super Talent Electronics, Inc. | Peripheral devices using phase-change memory |
US7767993B2 (en) | 2002-04-04 | 2010-08-03 | Kabushiki Kaisha Toshiba | Resistance change memory device |
US7663132B2 (en) | 2002-04-04 | 2010-02-16 | Kabushiki Kaisha Toshiba | Resistance change memory device |
US7623370B2 (en) | 2002-04-04 | 2009-11-24 | Kabushiki Kaisha Toshiba | Resistance change memory device |
KR100543445B1 (ko) * | 2003-03-04 | 2006-01-23 | 삼성전자주식회사 | 상변화 기억 소자 및 그 형성방법 |
US7706167B2 (en) | 2003-03-18 | 2010-04-27 | Kabushiki Kaisha Toshiba | Resistance change memory device |
US7719875B2 (en) | 2003-03-18 | 2010-05-18 | Kabushiki Kaisha Toshiba | Resistance change memory device |
US20060203541A1 (en) * | 2003-03-18 | 2006-09-14 | Haruki Toda | Phase change memory device |
US7778062B2 (en) | 2003-03-18 | 2010-08-17 | Kabushiki Kaisha Toshiba | Resistance change memory device |
US7400522B2 (en) | 2003-03-18 | 2008-07-15 | Kabushiki Kaisha Toshiba | Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation |
US7755934B2 (en) | 2003-03-18 | 2010-07-13 | Kabushiki Kaisha Toshiba | Resistance change memory device |
US7394680B2 (en) | 2003-03-18 | 2008-07-01 | Kabushiki Kaisha Toshiba | Resistance change memory device having a variable resistance element with a recording layer electrode served as a cation source in a write or erase mode |
JP4254293B2 (ja) * | 2003-03-25 | 2009-04-15 | 株式会社日立製作所 | 記憶装置 |
US7459715B2 (en) | 2003-04-03 | 2008-12-02 | Kabushiki Kaisha Toshiba | Resistance change memory device |
US7729158B2 (en) | 2003-04-03 | 2010-06-01 | Kabushiki Kaisha Toshiba | Resistance change memory device |
KR100604871B1 (ko) * | 2004-06-17 | 2006-07-31 | 삼성전자주식회사 | 상보형 불휘발성 메모리 소자와 그 동작 방법과 그 제조 방법과 그를 포함하는 논리소자 및 반도체 장치 |
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-
2003
- 2003-03-18 US US10/548,575 patent/US20060203541A1/en not_active Abandoned
- 2003-03-18 WO PCT/JP2003/003256 patent/WO2004084228A1/en active Application Filing
- 2003-03-18 JP JP2004569564A patent/JP4377816B2/ja not_active Expired - Fee Related
- 2003-03-18 CN CN038262983A patent/CN1764982B/zh not_active Expired - Lifetime
- 2003-03-18 EP EP03816361.4A patent/EP1609154B1/en not_active Expired - Lifetime
-
2008
- 2008-01-07 US US11/970,154 patent/US7859885B2/en not_active Expired - Lifetime
-
2010
- 2010-12-13 US US12/966,346 patent/US8102699B2/en not_active Expired - Fee Related
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2011
- 2011-12-28 US US13/338,950 patent/US8559211B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CN1764982B (zh) | 2011-03-23 |
EP1609154A1 (en) | 2005-12-28 |
US8559211B2 (en) | 2013-10-15 |
EP1609154B1 (en) | 2013-12-25 |
US20060203541A1 (en) | 2006-09-14 |
US20080112211A1 (en) | 2008-05-15 |
US7859885B2 (en) | 2010-12-28 |
US20110080778A1 (en) | 2011-04-07 |
US20120099370A1 (en) | 2012-04-26 |
CN1764982A (zh) | 2006-04-26 |
WO2004084228A1 (en) | 2004-09-30 |
JP2006514392A (ja) | 2006-04-27 |
US8102699B2 (en) | 2012-01-24 |
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