WO2017131642A1 - Resistive memory cell including a selector - Google Patents

Resistive memory cell including a selector Download PDF

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Publication number
WO2017131642A1
WO2017131642A1 PCT/US2016/014966 US2016014966W WO2017131642A1 WO 2017131642 A1 WO2017131642 A1 WO 2017131642A1 US 2016014966 W US2016014966 W US 2016014966W WO 2017131642 A1 WO2017131642 A1 WO 2017131642A1
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WO
WIPO (PCT)
Prior art keywords
electrode
layer
selector
resistive memory
oxide
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Application number
PCT/US2016/014966
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French (fr)
Inventor
Yoocharn Jeon
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Hewlett Packard Enterprise Development Lp
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Priority to PCT/US2016/014966 priority Critical patent/WO2017131642A1/en
Publication of WO2017131642A1 publication Critical patent/WO2017131642A1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/22—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the metal-insulator-metal type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • Non-volatile memory is computer memory that can store information even when not powered.
  • Types of non-volatile memory may include resistive RAM (random access memory) (RRAM or ReRAM), phase change RAM (PCRAM), conductive bridge RAM (CBRAM), ferroelectric RAM (F-RAM), etc.
  • Resistance memory elements such as resistive RAM, or ReRAM
  • resistive RAM can be programmed to different resistance states by applying programming energy. After programming, the state of the resistive memory elements can be read and remains stable over a specified time period.
  • Large arrays of resistive memory elements can be used to create a variety of resistive memory devices, including non-volatile solid state memory, programmable logic, signal processing, control systems, pattern recognition devices, and other applications. Examples of resistive memory devices include valence change memory and electrochemical metallization memory, both of which involve ionic motion during electrical switching and belong to the category of memristors.
  • Memristors are devices that can be programmed to different resistive states by applying a programming energy, for example, a voltage or current pulse. This energy generates a combination of electric field and thermal effects that can modulate the conductivity of both non-volatile switch and non-linear select functions in a memristive element. After programming, the state of the memristor can be read and remains stable over a specified time period.
  • a programming energy for example, a voltage or current pulse. This energy generates a combination of electric field and thermal effects that can modulate the conductivity of both non-volatile switch and non-linear select functions in a memristive element.
  • Fig. 1A depicts a resistive memory cell integrated with a selector, according to an example.
  • FIG. 1 B depicts an enlarged portion of Fig. 1 A.
  • Figs. 2A-2J depict, in cross-section, an example method for manufacturing the resistive memory cell integrated with the selector.
  • FIG. 3 is a flow chart depicting aspects of the example method of Figs. 2A- 2J.
  • Resistive memories are suitable for persistent memory applications that require short read/write latencies.
  • a crossbar arrangement of the resistive memory element without an access transistor at each cross point may be important for high density integration.
  • a selector device may be needed for each cross point to prevent the leakage current during read/write operations.
  • a selector device has two electrodes and one of the electrodes is connected to a memory element.
  • the electrode connected to the memory element (an intermediate electrode) may be separated from any other devices to individually access a memory element at a time.
  • a crossbar is considered to be a 2D (two-dimensional) structure and is not readily stackable to form a 3D structure for high density applications.
  • a stack of a first electrode, a selector, and a second electrode may be formed in a device layer of a multilayer structure of a plurality of alternating device, or conducting, layers and separation, or insulating, layers.
  • the second electrodes may be separated from neighboring second electrodes.
  • a resistive switching layer sometimes called herein a resistive memory layer, may be formed in contact with a plurality of the second electrodes.
  • a third electrode may be formed in contact with the resistive switching layer.
  • the selector and the resistive switching layer may be exchanged without change in the operating characteristics of the final device.
  • the multilayer stacks form 3D structures that may be suitable for high density applications.
  • Fig. 1A depicts a portion of the final structure 10, including the resistive memory cell integrated with the selector, prepared by, for example, the method depicted in Figs. 2A-2J, and specifically, an enlarged portion of Fig. 2J.
  • the resistive memory cell integrated with the selector 10 may be a stack 12 of alternating device layers 14 and separation layers 16, in which the device layers 14 may serve as the first electrode.
  • Fig. 1 B which is an enlarged portion of Fig. 1 A
  • at the end of each device layer 14 may be provided the selector 18 and an intermediate electrode, or second electrode, 20.
  • recesses 22 may be formed in the ends 14a of the conductive layers 14 (the recesses 22 are best seen in Fig.
  • the resistive switching layer 24 may be formed on a sidewall 34 of the stacks 12 and may be in contact with the plurality of selectors 18 and second electrodes 20.
  • the third electrode 26 may be in contact with the resistive switching layer 24.
  • the first electrodes 14 may each be contacted out of plane or vertically up through each stack 12, much like 3D NAND Flash architecture.
  • the device layers, or first electrodes, 14 may form bit lines, while the third electrode 26 may form source lines or vice versa.
  • Each stack 12 may be supported on a metallization layer 28, in turn supported on a CMOS (Complementary Metal-Oxide-Semiconductor) layer 30.
  • the metallization layer 28 may provide electrical connections between resistive memory cells 10 and the CMOS layer 30.
  • the CMOS layer 30 may provide conventional processing associated with CMOS circuitry, using the resistive switching memory (e.g., memristors) as a memory medium into which information can be written and out of which information can be read.
  • Figs. 2A-2J depict an example sequence of process steps that may be used to manufacture the resistive memory cell integrated with the selector. These steps are now described.
  • CMOS layers 30 may be provided, on which the metallization layer 28 may be formed.
  • the metallization layer 28 may be formed by any of the metal deposition processes and metal traces (not shown) may be defined, such as by lithography.
  • the metallization layer 28 may be composed of any of the conducting materials commonly used in CMOS technology, including, but not limited to, aluminum, copper, gold, platinum, palladium, alloys thereof, and the like.
  • a device layer, or first electrode, 14 and a separation layer 16 may be deposited alternatingly on the metallization layer 28, starting with a somewhat thicker base separation layer 16' and terminating in an uppermost separation layer 16".
  • Fig. 2A shows the resulting structure.
  • the first electrodes 14 may be made of electrode materials commonly employed in resistive switching devices, such as aluminum (Al), platinum (Pt), tungsten (W), gold (Au), titanium (Ti), ruthenium dioxide (RuO 2 ), titanium nitride (TiN), tungsten nitride (WN 2 ), tantalum (Ta), hafnium nitride (HfN), niobium nitride (NbN), iridium oxide (lrO 2 ), tantalum nitride (TaN), alloys thereof, and the like.
  • the metal component of the first electrode 14 may be the same as the metal component of the resistive switching layer.
  • the material of the conductor layer 14 may also include Ta.
  • the conductor layers 14 may have a thickness within a range of about 1 nm to about 100 nm. In some examples, the thickness of the conductor layers may be about 30 nm.
  • the separation layers 16 and 16" may be made of an insulating material selected from SiO 2 , AI 2 O 3 , Ta 2 O 5 , TiO 2 , Y 2 O 3 , HfO 2 , Nb 2 O 5 , ZrO 2 , CaO, MgO, Dy 2 O 3 , La 2 O 3 , and Si 3 N 4 , and may have a thickness within a range of about 1 nm to about 1 ,000 nm.
  • the base insulator layer 16' may be made the same insulating materials as layers 16 or different and may have a thickness somewhat thicker than layer 16 to aid in subsequent etching. Deposition of all layers may be done by any of the layer deposition processes, such as ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), sputtering, evaporation, laser ablation, and the like.
  • a masking layer 32 may be formed on top of the uppermost layer 16" of the multiple alternating layers 14, 16 and patterned, such as by etching, to define the memory cells.
  • the whole stack of the multiple alternating layers 14, 16, 16', 16" may be etched into the desired pattern of stacks 12 with the formed mask 32.
  • the pattern can be in the form of an array of openings (circles or squares in cross-section) in a stack of sheets.
  • the portion that is to be etched away may be cylindrical holes and they may become cylindrical columns of claddings of the resistive switching layer 24 and the third electrode 26; the third electrode 26 can fill the holes and be the cores of the columns.
  • dry etching such as Reactive Ion Etching (RIE) may be employed to anisotropically etch the layers not covered by the mask 32 and thereby form the plurality of stacks 12.
  • RIE Reactive Ion Etching
  • the etching process may terminate at the metallization layer 28, either naturally (because the etchant does not etch the metallization layer) or timed (because the etching is stopped after a pre-determined period of time at or slightly in the metallization layer).
  • Fig. 2C depicts the etched structure, in which three stacks 12 are shown.
  • the completed structure 10 may have fewer or more than the three stacks 12.
  • the multiple alternating layers 14, 16, 16', 16" may next be exposed to an etchant that selectively etches the conductor part 14 of the multiple layers. Isotropic dry etches or isotropic wet etches may be used to etch the conducting layers 14. As shown in Fig. 2D, the selective etching provides recesses 22 on the sidewalls 34 patterned by the first etch step. The depth of the recesses 22 may be larger than the sum of the thicknesses of the selector 18 and the second electrode 20 that are deposited in the following steps (see Figs. 2E and 2F). After the etching step, the mask layer 32 may not be removed, but rather may remain in place for a subsequent use, described below.
  • the conductor layers 14 can be another (sacrificial) insulator layers (not shown), which are replaced with conductor layers later after the sacrificial layers are removed by isotropic etching. This may make multilayer etching less challenging.
  • the sacrificial insulator layers may be isotropically etched at this step to form the recesses 22.
  • the selector material 18 and the intermediate, or second, electrode 20 material may be deposited on the all exposed surfaces by a conformal deposition technique.
  • ALD atomic layer deposition
  • Other conformal deposition techniques such as LPCVD (low pressure chemical vapor deposition), may be used to perform the conformal deposition.
  • Fig. 2E depicts the resulting structure after deposition of the selector material 18, while Fig. 2F depicts the resulting structure after deposition of the intermediate electrode material 20.
  • the selector materials 18 may be selected from NbO x , TaO x , TiO x , HfO x , ⁇ , VOx, ⁇ , Si, SiO x , SiN x , AIN X , and Ge x Sb y Te z , and combinations of these, where x, y, and z may represent either stoichiometric or non-stoichiometric
  • the thickness of the selector material 18 may be within a range of about 1 nm to about 100 nm.
  • the material for the second electrode 20 may be selected from TiN, W, WN 2 , Ta, TaN, Nb, NbN, Al, Cu, Ti, Pt, Ir, Ru, lrO 2 , RuO 2 , Pd, Ni, Ag, Au, Mo, and Co, and combinations of these.
  • the thickness of the second electrode 20 may be within a range of about 1 nm to about 100 nm.
  • the selector 18 layer and the second electrode layer 20 may be anisotropically etched to remove the layers on the side walls 34, but to keep them in the recesses 22. This separates the second electrodes 20 from neighboring second electrodes.
  • the resulting structure is depicted in Fig. 2G. It is to be noted that this step may separate the second electrodes 20 from all the other second electrodes when the openings are circular. However, when the first patterns are stripes, it may just separate the second
  • the second electrodes 20 between the third electrode patterns may still be needed to be etched to be disconnected.
  • the stripe openings between stacks 12 may still leave the second electrodes 20 connected along the out-of-plane direction, in which direction the first electrodes 14 run.
  • the second electrodes 20 are shared with the cells sharing the first electrodes 14.
  • another etching step may be performed that removes the whole stack where the recessed portions 22 are, but leaves the first electrodes 14 connected.
  • the mask layer 32 may be removed when the stack pattern is circular openings, as shown in Fig. 2H.
  • the mask layer 32 can be narrowed down and retained to disconnect the second electrodes 20 after the third electrode etching.
  • the resistive switching layer 24 and the third electrode layer 26 may be deposited by conformal deposition techniques on all the exposed surfaces. Even if the resistive switching layer 24 is not patterned into individual memory elements, each cell can be individually accessible by a unique combination of the first electrode 14 and the third electrode 26, since the intermediate electrodes 20 are separated from one another and dedicated to only one memory cell.
  • Fig. 2I depicts the resulting structure after deposition of the resistive switching layer 24, while Fig. 2J depicts the resulting structure after deposition of the third electrode layer 26. This resulting structure may be called a vertical crossbar (to distinguish it from a horizontal crossbar in 2D.
  • Another term for this structure may be 3D RRAM.
  • Metal or semiconductor oxides may be employed as the resistive switching layer 24; examples include either transition metal oxides, such as tantalum oxide, titanium oxide, yttrium oxide, hafnium oxide, niobium oxide, zirconium oxide, or other like oxides, or non-transition metal oxides, such as aluminum oxide, calcium oxide, magnesium oxide, dysprosium oxide, lanthanum oxide, silicon dioxide, or other like oxides. Further examples include transition metal nitrides, such as aluminum nitride, gallium nitride, tantalum nitride, and silicon nitride. The thickness of the resistive switching layer may range from about 1 nm to about 100 nm.
  • the third electrode 26 may be a material selected from the group consisting of TiN, W, WN 2 , Ta, TaN, Nb, NbN, Al, Cu, Ti, Pt, Ir, Ru, lrO 2 , RuO 2 , Pd, Ni, Ag, Au, Mo, and Co and may be the same or different as the second electrode 20.
  • the thickness of the third electrode 26 may have a thickness within a range of about 1 nm to about 100 nm.
  • the pattern may be at an angle to the pattern of the first electrodes 14 when the first electrodes are patterned in stripes. If the openings in the stack are circular, there may be another stack etching step to define the first electrode pattern, which runs out-of-plane of the drawings, between the second electrode etching and the third electrode deposition.
  • the second electrode 20 between the third electrode patterns can be etched using the combination of the retained stack pattern mask and the third electrode mask to disconnect the second electrodes 20 from other second electrodes of the cells connected to neighboring third electrodes 26.
  • the selector layer 18 and the memory element layer 24 can be swapped so that the memory elements are formed first and separated and a contiguous selector layer is formed after the second electrodes are separated.
  • a selected memory element can be individually accessed for writing or reading by applying an appropriate voltage that is higher than the threshold voltage of the selector between the first electrode and the third electrode in contact with the selected device while the mid-point voltage is applied all the rest of the first electrodes and the third electrodes in the array. Only the selector in the selected device is turned on because all the second electrodes are separated from other second electrodes. Since all the first electrodes and the third electrodes are shared by plurality of memory elements, if the second electrode of the selected cell were connected to other second electrodes, then any other cells sharing the connection would be accessed together. It would then make it difficult to individually access a cell independently, which is why the second electrodes are isolated from each other.
  • Fig. 3 depicts a method 100 for manufacturing the resistive memory cell integrated with the selector.
  • the method 100 may include providing 105 the
  • the method 100 may further include forming 1 10 a stack 12 of alternating device layers 14 and separation layers 16 on the metallization layer 28.
  • the device layers 14 are a conducting material that forms a first electrode, while the separation layers 16 are an insulating material.
  • the stack 12 may have a sidewall 34 defined by ends of the device layers 14 and the separation layers 16.
  • the method 100 may further include forming 1 15 a recess 22 in each first electrode 14 in the sidewall 34 relative to a layer 16 of insulating material above and a layer 16 of insulating material below the first electrode.
  • the method 100 may further include depositing 120 one of a selector material 18 or a resistive switching material 24 at least one the exposed surface of the first electrodes 14 to form a generally U-shaped opening.
  • the method 100 may further include forming 125 a second electrode 20 in contact with the selector material 18 or the resistive switching material 24 in at least a part of the recess 24.
  • the method 100 may further include removing 130 any second electrode material 20 that is outside of the recess 22, i.e., on the sidewalls 34 of the stacks 12.
  • the method 100 may further include forming 135 the other of a layer 24 of the resistive memory material or the selector material 18 on the sidewalls 34 of the stacks 12. [0044] The method 100 may conclude with forming 140 a layer 30 of a third electrode 26 formed on the layer of resistive memory material 24 or selector material 18.
  • the combination of the first electrode 14, the layer of resistive memory material 24, and the third electrode 26 may define the resistive memory cell.
  • the first electrode 14 and the third electrode 26 may be electrically connected to a plurality of resistive memory cells.
  • individual memory cells may be uniquely addressed by a combination of accessing a particular first electrode 14 and the third electrode 26.
  • the second electrode 20 may be separated from other second electrodes. In this regard, the second electrodes 20 may be considered to be "floating".
  • Memory cells with integrated selectors can be fabricated with a bit cost scalable multilayer architecture, which may provide a way to produce high density memories with a significantly lower cost.
  • ranges provided herein include the stated range and any value or sub-range within the stated range.
  • a range from about 50 to about 100 should be interpreted to include not only the explicitly recited limits of about 50 to about 100, but also to include individual values, such as 75, 90, etc., and sub-ranges, such as from about 65 to about 85, etc.
  • “about” is utilized to describe a value, this is meant to encompass minor variations (up to ⁇ 10%) from the stated value.

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Abstract

A resistive memory cell is integrated with a selector. The device structure includes a stack of a first electrode, one of a selector or a resistive switching layer, and a second electrode formed in a device layer of a multilayer structure of a plurality of alternating device layers and separation layers. Each second electrode is separated from other second electrodes. The device structure further includes the other of the resistive switching layer or the selector formed in contact with a plurality of the second electrodes. The device structure further includes a third electrode formed in contact with the resistive switching layer or the selector layer. A method for manufacturing the device structure is also provided.

Description

RESISTIVE MEMORY CELL INCLUDING A SELECTOR
BACKGROUND
[0001 ] Non-volatile memory is computer memory that can store information even when not powered. Types of non-volatile memory may include resistive RAM (random access memory) (RRAM or ReRAM), phase change RAM (PCRAM), conductive bridge RAM (CBRAM), ferroelectric RAM (F-RAM), etc.
[0002] Resistance memory elements, such as resistive RAM, or ReRAM, can be programmed to different resistance states by applying programming energy. After programming, the state of the resistive memory elements can be read and remains stable over a specified time period. Large arrays of resistive memory elements can be used to create a variety of resistive memory devices, including non-volatile solid state memory, programmable logic, signal processing, control systems, pattern recognition devices, and other applications. Examples of resistive memory devices include valence change memory and electrochemical metallization memory, both of which involve ionic motion during electrical switching and belong to the category of memristors.
[0003] Memristors are devices that can be programmed to different resistive states by applying a programming energy, for example, a voltage or current pulse. This energy generates a combination of electric field and thermal effects that can modulate the conductivity of both non-volatile switch and non-linear select functions in a memristive element. After programming, the state of the memristor can be read and remains stable over a specified time period. BRIEF DESCRIPTION OF THE DRAWINGS
[0004] Features of examples of the present disclosure will become apparent by reference to the following detailed description and drawings, in which like reference numerals correspond to similar, though perhaps not identical, components. For the sake of brevity, reference numerals or features having a previously described function may or may not be described in connection with other drawings in which they appear.
[0005] Fig. 1A depicts a resistive memory cell integrated with a selector, according to an example.
[0006] Fig. 1 B depicts an enlarged portion of Fig. 1 A.
[0007] Figs. 2A-2J depict, in cross-section, an example method for manufacturing the resistive memory cell integrated with the selector.
[0008] Fig. 3 is a flow chart depicting aspects of the example method of Figs. 2A- 2J.
DETAILED DESCRIPTION
[0009] Resistive memories are suitable for persistent memory applications that require short read/write latencies. A crossbar arrangement of the resistive memory element without an access transistor at each cross point may be important for high density integration.
[0010] In a crossbar arrangement of memory elements, a selector device may be needed for each cross point to prevent the leakage current during read/write operations. Usually, a selector device has two electrodes and one of the electrodes is connected to a memory element. The electrode connected to the memory element (an intermediate electrode) may be separated from any other devices to individually access a memory element at a time.
[001 1 ] However, a crossbar is considered to be a 2D (two-dimensional) structure and is not readily stackable to form a 3D structure for high density applications.
[0012] In accordance with principles disclosed herein, a stack of a first electrode, a selector, and a second electrode may be formed in a device layer of a multilayer structure of a plurality of alternating device, or conducting, layers and separation, or insulating, layers. The second electrodes may be separated from neighboring second electrodes. A resistive switching layer, sometimes called herein a resistive memory layer, may be formed in contact with a plurality of the second electrodes. A third electrode may be formed in contact with the resistive switching layer. The selector and the resistive switching layer may be exchanged without change in the operating characteristics of the final device. The multilayer stacks form 3D structures that may be suitable for high density applications.
[0013] Fig. 1A depicts a portion of the final structure 10, including the resistive memory cell integrated with the selector, prepared by, for example, the method depicted in Figs. 2A-2J, and specifically, an enlarged portion of Fig. 2J. The resistive memory cell integrated with the selector 10 may be a stack 12 of alternating device layers 14 and separation layers 16, in which the device layers 14 may serve as the first electrode. As shown in Fig. 1 B, which is an enlarged portion of Fig. 1 A, at the end of each device layer 14 may be provided the selector 18 and an intermediate electrode, or second electrode, 20. As will be shown below, recesses 22 may be formed in the ends 14a of the conductive layers 14 (the recesses 22 are best seen in Fig. 2D, while the ends 14a of the device layers 14 are best seen in Fig. 2C). The resistive switching layer 24 may be formed on a sidewall 34 of the stacks 12 and may be in contact with the plurality of selectors 18 and second electrodes 20. The third electrode 26 may be in contact with the resistive switching layer 24.
[0014] The first electrodes 14 may each be contacted out of plane or vertically up through each stack 12, much like 3D NAND Flash architecture. The device layers, or first electrodes, 14 may form bit lines, while the third electrode 26 may form source lines or vice versa.
[0015] Each stack 12 may be supported on a metallization layer 28, in turn supported on a CMOS (Complementary Metal-Oxide-Semiconductor) layer 30. The metallization layer 28 may provide electrical connections between resistive memory cells 10 and the CMOS layer 30. The CMOS layer 30 may provide conventional processing associated with CMOS circuitry, using the resistive switching memory (e.g., memristors) as a memory medium into which information can be written and out of which information can be read.
[0016] Figs. 2A-2J depict an example sequence of process steps that may be used to manufacture the resistive memory cell integrated with the selector. These steps are now described.
[0017] One or more CMOS layers 30 may be provided, on which the metallization layer 28 may be formed. The metallization layer 28 may be formed by any of the metal deposition processes and metal traces (not shown) may be defined, such as by lithography. The metallization layer 28 may be composed of any of the conducting materials commonly used in CMOS technology, including, but not limited to, aluminum, copper, gold, platinum, palladium, alloys thereof, and the like.
[0018] Multiple layers of a device layer, or first electrode, 14 and a separation layer 16 may be deposited alternatingly on the metallization layer 28, starting with a somewhat thicker base separation layer 16' and terminating in an uppermost separation layer 16". Fig. 2A shows the resulting structure. The first electrodes 14 may be made of electrode materials commonly employed in resistive switching devices, such as aluminum (Al), platinum (Pt), tungsten (W), gold (Au), titanium (Ti), ruthenium dioxide (RuO2), titanium nitride (TiN), tungsten nitride (WN2), tantalum (Ta), hafnium nitride (HfN), niobium nitride (NbN), iridium oxide (lrO2), tantalum nitride (TaN), alloys thereof, and the like. The metal component of the first electrode 14 may be the same as the metal component of the resistive switching layer. For example, where the resistive switching layer 24 includes Ta, the material of the conductor layer 14 may also include Ta. The conductor layers 14 may have a thickness within a range of about 1 nm to about 100 nm. In some examples, the thickness of the conductor layers may be about 30 nm.
[0019] The separation layers 16 and 16" may be made of an insulating material selected from SiO2, AI2O3, Ta2O5, TiO2, Y2O3, HfO2, Nb2O5, ZrO2, CaO, MgO, Dy2O3, La2O3, and Si3N4, and may have a thickness within a range of about 1 nm to about 1 ,000 nm. The base insulator layer 16' may be made the same insulating materials as layers 16 or different and may have a thickness somewhat thicker than layer 16 to aid in subsequent etching. Deposition of all layers may be done by any of the layer deposition processes, such as ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), sputtering, evaporation, laser ablation, and the like.
[0020] As shown in Fig. 2B, a masking layer 32 may be formed on top of the uppermost layer 16" of the multiple alternating layers 14, 16 and patterned, such as by etching, to define the memory cells. The whole stack of the multiple alternating layers 14, 16, 16', 16" may be etched into the desired pattern of stacks 12 with the formed mask 32. The pattern can be in the form of an array of openings (circles or squares in cross-section) in a stack of sheets. The portion that is to be etched away may be cylindrical holes and they may become cylindrical columns of claddings of the resistive switching layer 24 and the third electrode 26; the third electrode 26 can fill the holes and be the cores of the columns.
[0021 ] As an example, dry etching, such as Reactive Ion Etching (RIE) may be employed to anisotropically etch the layers not covered by the mask 32 and thereby form the plurality of stacks 12. The etching process may terminate at the metallization layer 28, either naturally (because the etchant does not etch the metallization layer) or timed (because the etching is stopped after a pre-determined period of time at or slightly in the metallization layer). Fig. 2C depicts the etched structure, in which three stacks 12 are shown. The completed structure 10 may have fewer or more than the three stacks 12.
[0022] The multiple alternating layers 14, 16, 16', 16" may next be exposed to an etchant that selectively etches the conductor part 14 of the multiple layers. Isotropic dry etches or isotropic wet etches may be used to etch the conducting layers 14. As shown in Fig. 2D, the selective etching provides recesses 22 on the sidewalls 34 patterned by the first etch step. The depth of the recesses 22 may be larger than the sum of the thicknesses of the selector 18 and the second electrode 20 that are deposited in the following steps (see Figs. 2E and 2F). After the etching step, the mask layer 32 may not be removed, but rather may remain in place for a subsequent use, described below. [0023] As another example of forming the recesses 22, the conductor layers 14 can be another (sacrificial) insulator layers (not shown), which are replaced with conductor layers later after the sacrificial layers are removed by isotropic etching. This may make multilayer etching less challenging. In this case, the sacrificial insulator layers may be isotropically etched at this step to form the recesses 22.
[0024] The following description is directed to forming the selector material 18 in the recesses 22 and the resistive switching material 24 on the sidewalls 34 of the stacks 12. However, it is to be appreciated that the resistive switching material 24 may be formed in the recesses 22 and the selector material 18 may be formed on the sidewalls 34 of the stacks 12. The completed devices 10 operate the same either way.
[0025] The selector material 18 and the intermediate, or second, electrode 20 material may be deposited on the all exposed surfaces by a conformal deposition technique. ALD (atomic layer deposition) is an example of one way of performing the conformal deposition. Other conformal deposition techniques, such as LPCVD (low pressure chemical vapor deposition), may be used to perform the conformal deposition. Fig. 2E depicts the resulting structure after deposition of the selector material 18, while Fig. 2F depicts the resulting structure after deposition of the intermediate electrode material 20.
[0026] The selector materials 18 may be selected from NbOx, TaOx, TiOx, HfOx, ΑΙΟχ, VOx, ΖηΟχ, Si, SiOx, SiNx, AINX, and GexSbyTez, and combinations of these, where x, y, and z may represent either stoichiometric or non-stoichiometric
compositions. The thickness of the selector material 18 may be within a range of about 1 nm to about 100 nm.
[0027] The material for the second electrode 20 may be selected from TiN, W, WN2, Ta, TaN, Nb, NbN, Al, Cu, Ti, Pt, Ir, Ru, lrO2, RuO2, Pd, Ni, Ag, Au, Mo, and Co, and combinations of these. The thickness of the second electrode 20 may be within a range of about 1 nm to about 100 nm.
[0028] Using the mask layer 32 retained from the previous etch step, the selector 18 layer and the second electrode layer 20 may be anisotropically etched to remove the layers on the side walls 34, but to keep them in the recesses 22. This separates the second electrodes 20 from neighboring second electrodes. The resulting structure is depicted in Fig. 2G. It is to be noted that this step may separate the second electrodes 20 from all the other second electrodes when the openings are circular. However, when the first patterns are stripes, it may just separate the second
electrodes 20 from the electrodes of the lower and upper layers. The second electrodes 20 between the third electrode patterns may still be needed to be etched to be disconnected. The stripe openings between stacks 12 may still leave the second electrodes 20 connected along the out-of-plane direction, in which direction the first electrodes 14 run. In other words, the second electrodes 20 are shared with the cells sharing the first electrodes 14. To separate the second electrodes 20 in that direction, another etching step may be performed that removes the whole stack where the recessed portions 22 are, but leaves the first electrodes 14 connected.
[0029] At this stage, the mask layer 32 may be removed when the stack pattern is circular openings, as shown in Fig. 2H. When stripe patterns are used for the stack pattern, the mask layer 32 can be narrowed down and retained to disconnect the second electrodes 20 after the third electrode etching.
[0030] The resistive switching layer 24 and the third electrode layer 26 may be deposited by conformal deposition techniques on all the exposed surfaces. Even if the resistive switching layer 24 is not patterned into individual memory elements, each cell can be individually accessible by a unique combination of the first electrode 14 and the third electrode 26, since the intermediate electrodes 20 are separated from one another and dedicated to only one memory cell. Fig. 2I depicts the resulting structure after deposition of the resistive switching layer 24, while Fig. 2J depicts the resulting structure after deposition of the third electrode layer 26. This resulting structure may be called a vertical crossbar (to distinguish it from a horizontal crossbar in 2D.
Another term for this structure may be 3D RRAM.
[0031 ] Metal or semiconductor oxides may be employed as the resistive switching layer 24; examples include either transition metal oxides, such as tantalum oxide, titanium oxide, yttrium oxide, hafnium oxide, niobium oxide, zirconium oxide, or other like oxides, or non-transition metal oxides, such as aluminum oxide, calcium oxide, magnesium oxide, dysprosium oxide, lanthanum oxide, silicon dioxide, or other like oxides. Further examples include transition metal nitrides, such as aluminum nitride, gallium nitride, tantalum nitride, and silicon nitride. The thickness of the resistive switching layer may range from about 1 nm to about 100 nm.
[0032] The third electrode 26 may be a material selected from the group consisting of TiN, W, WN2, Ta, TaN, Nb, NbN, Al, Cu, Ti, Pt, Ir, Ru, lrO2, RuO2, Pd, Ni, Ag, Au, Mo, and Co and may be the same or different as the second electrode 20. The thickness of the third electrode 26 may have a thickness within a range of about 1 nm to about 100 nm.
[0033] In delineating the third electrodes 26, the pattern may be at an angle to the pattern of the first electrodes 14 when the first electrodes are patterned in stripes. If the openings in the stack are circular, there may be another stack etching step to define the first electrode pattern, which runs out-of-plane of the drawings, between the second electrode etching and the third electrode deposition.
[0034] When stripe patterns are used for the stack pattern, then after the third electrode etching, the second electrode 20 between the third electrode patterns can be etched using the combination of the retained stack pattern mask and the third electrode mask to disconnect the second electrodes 20 from other second electrodes of the cells connected to neighboring third electrodes 26.
[0035] As noted above, in another example, the selector layer 18 and the memory element layer 24 can be swapped so that the memory elements are formed first and separated and a contiguous selector layer is formed after the second electrodes are separated.
[0036] In operation of the plurality of resistive memory cells, each including a selector, a selected memory element can be individually accessed for writing or reading by applying an appropriate voltage that is higher than the threshold voltage of the selector between the first electrode and the third electrode in contact with the selected device while the mid-point voltage is applied all the rest of the first electrodes and the third electrodes in the array. Only the selector in the selected device is turned on because all the second electrodes are separated from other second electrodes. Since all the first electrodes and the third electrodes are shared by plurality of memory elements, if the second electrode of the selected cell were connected to other second electrodes, then any other cells sharing the connection would be accessed together. It would then make it difficult to individually access a cell independently, which is why the second electrodes are isolated from each other.
[0037] Fig. 3 depicts a method 100 for manufacturing the resistive memory cell integrated with the selector. The method 100 may include providing 105 the
metallization layer 28.
[0038] The method 100 may further include forming 1 10 a stack 12 of alternating device layers 14 and separation layers 16 on the metallization layer 28. As indicated, the device layers 14 are a conducting material that forms a first electrode, while the separation layers 16 are an insulating material. The stack 12 may have a sidewall 34 defined by ends of the device layers 14 and the separation layers 16.
[0039] The method 100 may further include forming 1 15 a recess 22 in each first electrode 14 in the sidewall 34 relative to a layer 16 of insulating material above and a layer 16 of insulating material below the first electrode.
[0040] The method 100 may further include depositing 120 one of a selector material 18 or a resistive switching material 24 at least one the exposed surface of the first electrodes 14 to form a generally U-shaped opening.
[0041 ] The method 100 may further include forming 125 a second electrode 20 in contact with the selector material 18 or the resistive switching material 24 in at least a part of the recess 24.
[0042] The method 100 may further include removing 130 any second electrode material 20 that is outside of the recess 22, i.e., on the sidewalls 34 of the stacks 12.
[0043] The method 100 may further include forming 135 the other of a layer 24 of the resistive memory material or the selector material 18 on the sidewalls 34 of the stacks 12. [0044] The method 100 may conclude with forming 140 a layer 30 of a third electrode 26 formed on the layer of resistive memory material 24 or selector material 18.
[0045] The combination of the first electrode 14, the layer of resistive memory material 24, and the third electrode 26 may define the resistive memory cell. The first electrode 14 and the third electrode 26 may be electrically connected to a plurality of resistive memory cells. As a consequence, individual memory cells may be uniquely addressed by a combination of accessing a particular first electrode 14 and the third electrode 26. As noted above, the second electrode 20 may be separated from other second electrodes. In this regard, the second electrodes 20 may be considered to be "floating".
[0046] Memory cells with integrated selectors can be fabricated with a bit cost scalable multilayer architecture, which may provide a way to produce high density memories with a significantly lower cost.
[0047] Reference throughout the specification to "one example", "another example", "an example", and so forth, means that a particular element (e.g., feature, structure, and/or characteristic) described in connection with the example is included in at least one example described herein, and may or may not be present in other examples. In addition, it is to be understood that the described elements for any example may be combined in any suitable manner in the various examples unless the context clearly dictates otherwise.
[0048] It is to be understood that the ranges provided herein include the stated range and any value or sub-range within the stated range. For example, a range from about 50 to about 100 should be interpreted to include not only the explicitly recited limits of about 50 to about 100, but also to include individual values, such as 75, 90, etc., and sub-ranges, such as from about 65 to about 85, etc. Furthermore, when "about" is utilized to describe a value, this is meant to encompass minor variations (up to ±10%) from the stated value. [0049] In describing and claiming the examples disclosed herein, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise.
[0050] While several examples have been described in detail, it is to be understood that the disclosed examples may be modified. Therefore, the foregoing description is to be considered non-limiting.

Claims

What is claimed is:
1 . A resistive memory cell including a selector, including:
a stack of a first electrode, one of a selector or a resistive switching layer, and a second electrode formed in a device layer of a multilayer structure of a plurality of alternating device layers and separation layers, wherein the second electrode is separated from other second electrodes;
the other of the resistive switching layer or the selector formed in contact with a plurality of the second electrodes; and
a third electrode formed in contact with the resistive switching layer or the selector layer.
2. The resistive memory cell as defined in claim 1 wherein the stack is supported on a layer of metallization that in turn is supported on a CMOS layer, wherein the layer of metallization comprises a material selected from the group consisting of aluminum, copper, gold, platinum, palladium, tungsten, and alloys thereof.
3. The resistive memory cell as defined in claim 1 wherein the alternating separation layers comprise an insulating material selected from the group consisting of SiO2, AI2O3, Ta2O5, TiO2, Y2O3, HfO2, Nb2O5, ZrO2, CaO, MgO, Dy2O3, La2O3, and Si3N4, and have a thickness within a range of about 1 nm to about 1 ,000 nm.
4. The resistive memory cell as defined in claim 1 wherein the alternating device layers comprise a material selected from the group consisting of Al, Pt, W, Au, Ti, RuO2, TiN, WN2, Ta, HfN, NbN, lrO2, and TaN, and have a thickness within a range of about 1 nm to about 100 nm.
5. The resistive memory cell as defined in claim 1 wherein the selector or the resistive switching layer and second electrode are formed in a recess in an end of each device layer and have a depth that is larger than the sum of a thickness of the selector plus a thickness of the second electrode.
6. The resistive memory cell as defined in claim 1 wherein the selector comprises a material selected from the group consisting of NbOx, TaOx, TiOx, HfOx, ΑΙΟχ, VOx, Ζηθχ, Si, SiOx, SiNx, AINX, and GexSbyTez, and combinations of these, where x, y, and z represent either a stoichiometric composition or a non-stoichiometric compositions, and wherein the selector has a thickness within a range of about 1 nm to about 100 nm.
7. The resistive memory cell as defined in claim 1 wherein the second electrode and third electrode each comprise a material selected from the group consisting of TiN, W, WN2, Ta, TaN, Nb, NbN, Al, Cu, Ti, Pt, Ir, Ru, Ir02, Ru02, Pd, Ni, Ag, Au, Mo, and Co and may be the same or different, and each electrode has a thickness within a range of about 1 nm to about 100 nm.
8. The resistive memory cell as defined in claim 1 wherein the resistive memory material comprises a material selected from the group consisting of tantalum oxide, titanium oxide, yttrium oxide, hafnium oxide, niobium oxide, zirconium oxide, aluminum oxide, calcium oxide, magnesium oxide, dysprosium oxide, lanthanum oxide, silicon dioxide, or other like oxides aluminum nitride, gallium nitride, tantalum nitride, and silicon nitride and combinations thereof and has a thickness within a range of about 1 nm to about 100 nm.
9. A method of manufacturing a resistive memory cell including a selector, the method including:
providing a layer of metallization;
forming a stack of alternating device layers and separation layers on the layer of metallization, the device layers comprising conducting material that forms a first electrode and the separation layers comprising insulating material, the stack having a sidewall defined by ends of the device layers and separation layers;
forming a recess in each first electrode in the sidewall relative to a separation layer of insulating material above and below the first electrode;
depositing one of a selector material or a resistive switching material at least on the exposed surface of the first electrodes to form a generally U-shaped opening; forming a second electrode in contact with the selector material or the resistive switching material in at least a part of the recess;
removing any second electrode material outside of the recess;
forming a layer of the other of the resistive memory material or the selector material on the sidewall and contacting at least the second electrode; and
forming a layer of a third electrode on the layer of resistive memory material or the selector layer,
wherein the first electrode, the layer of resistive memory material, and the third electrode define the resistive memory cell,
wherein the first electrode and the third electrode are electrically connected to a plurality of resistive memory cells, and
wherein the second electrode is separated from other second electrodes.
10. The method as defined in claim 9 wherein the selector, the second electrode, the resistive switching material, and the third electrode are all deposited conformally by a process selected from the group consisting of Atomic Layer
Deposition or Chemical Vapor Deposition.
1 1 . The method as defined in claim 10 wherein the layer of metallization is supported on a CMOS layer and comprises a material selected from the group consisting of aluminum, copper, gold, platinum, palladium, and alloys thereof and wherein the metallization layer provides interconnections between the CMOS layer and each resistive memory cell.
12. The method as defined in claim 10 wherein the recesses are formed to a depth that is larger than the sum of a thickness of the selector plus a thickness of the second electrode.
13. The method as defined in claim 10 wherein the selector comprises a material selected from the group consisting of NbOx, TaOx, TiOx, HfOx, AIOx, VOx, Ζηθχ, Si, SiOx, SiNx, AINX, and GexSbyTez, and combinations of these, where x, y, and z represent either a stoichiometric composition or a non-stoichiometric composition, and wherein the selector has a thickness within a range of about 1 nm to about 100 nm and wherein the resistive memory material comprises a material selected from the group consisting of tantalum oxide, titanium oxide, yttrium oxide, hafnium oxide, niobium oxide, zirconium oxide, aluminum oxide, calcium oxide, magnesium oxide, dysprosium oxide, lanthanum oxide, silicon dioxide, or other like oxides aluminum nitride, gallium nitride, tantalum nitride, and silicon nitride and has a thickness within a range of about 1 nm to about 100 nm.
14. The method as defined in claim 10 wherein the second electrode and the third electrode each comprise a material selected from the group consisting of TiN, W, WN2, Ta, TaN, Nb, NbN, Al, Cu, Ti, Pt, Ir, Ru, Ir02, Ru02, Pd, Ni, Ag, Au, Mo, and Co and may be the same or different, and each electrode has a thickness within a range of about 1 nm to about 100 nm.
15. A resistive memory cell including a selector, including:
a CMOS layer;
a layer of metallization on the CMOS layer;
a stack of alternating device layers of conducting material and separation layers of insulating material, the stack having a sidewall defined by ends of the layers of the insulating material and the conducting material, wherein each layer of conducting material has a recess in the sidewall relative to a layer of insulating material above and a layer of insulating material below the layer of conducting material; each recess lined with one of a selector material or a resistive switching material to form a generally U-shaped opening that is filled with a second electrode; a layer of the other of the resistive memory material or the selector material formed on the sidewall and contacting at least the second electrode, wherein the layer of resistive memory material also contacts the first electrode; and
a layer of a third electrode formed on the layer of the resistive memory material or the selector material formed on the sidewall,
wherein the first electrode, the layer of resistive memory material, and the third electrode define the resistive memory cell,
wherein the first electrode and the third electrode are electrically connected to a plurality of resistive memory cells, and
wherein the second electrode is separated from other second electrodes.
PCT/US2016/014966 2016-01-26 2016-01-26 Resistive memory cell including a selector WO2017131642A1 (en)

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