CN110783453B - Dual-mode resistive random access memory device and preparation method thereof - Google Patents
Dual-mode resistive random access memory device and preparation method thereof Download PDFInfo
- Publication number
- CN110783453B CN110783453B CN201910903216.1A CN201910903216A CN110783453B CN 110783453 B CN110783453 B CN 110783453B CN 201910903216 A CN201910903216 A CN 201910903216A CN 110783453 B CN110783453 B CN 110783453B
- Authority
- CN
- China
- Prior art keywords
- layer
- random access
- self
- resistive random
- access memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 46
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 23
- 230000008859 change Effects 0.000 claims abstract description 17
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000137 annealing Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 239000004973 liquid crystal related substance Substances 0.000 claims 2
- 229910052802 copper Inorganic materials 0.000 claims 1
- 238000005019 vapor deposition process Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 16
- 239000010408 film Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- 230000015654 memory Effects 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 230000010354 integration Effects 0.000 description 10
- 239000007772 electrode material Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
- 230000002457 bidirectional effect Effects 0.000 description 6
- 230000005284 excitation Effects 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011368 organic material Substances 0.000 description 4
- 229910000314 transition metal oxide Inorganic materials 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
Abstract
The invention provides a dual-mode resistive random access memory, which comprises a substrate and a bottom electrode-resistive random access layer-self-selection layer-top electrode structure positioned on the substrate. The invention also provides a preparation method of the dual-mode resistive random access memory, which comprises the following steps: 1) Defining a bottom electrode pattern, and preparing a bottom electrode on the substrate according to the pattern; 2) Depositing a resistive layer on the bottom electrode by adopting a PVD (physical vapor deposition), ALD (atomic layer deposition) or CVD (chemical vapor deposition) method; 3) Depositing a self-selection layer on the resistance change layer by adopting a PVD (physical vapor deposition) or ALD (atomic layer deposition) method, and applying an annealing treatment procedure; 4) Defining a bottom electrode lead-out hole pattern, and etching a bottom electrode lead-out hole in the resistive layer and the self-selection layer according to the pattern; 5) A top electrode pattern is defined, according to which a top electrode is prepared on the self-selected layer. The invention is based on the realization of a resistive random access memory device with self-selection by using a conventional CMOS process, so as to reduce or even eliminate the crosstalk problem existing in the crossbar structure of the resistive random access memory.
Description
Technical Field
The invention belongs to the technical field of semiconductor and CMOS hybrid integrated circuits, and particularly relates to a dual-mode resistive random access memory with two switching modes and a preparation method thereof.
Background
With the development of integrated circuits, the device size is smaller and the integration density is higher. Meanwhile, with the development of the mobile internet, the power consumption requirement on devices of mobile terminal equipment is higher and higher. For the nonvolatile memory, the flash memory (flash) which currently occupies the main share of the market is reduced in size and integrated density to the limit, and the operation voltage is high, so that the development of the future mobile internet is difficult to meet.
In many new research on flash memory substitutes, resistive Random Access Memory (RRAM) has the advantages of high integration level, low power consumption for reading and writing, high reading and writing speed and the like, so that the Resistive Random Access Memory (RRAM) becomes a favorable competitor for next-generation memories. Resistive random access memories generally have two states, a high resistance state ("0" state) and a low resistance state ("1" state). In actual operation, the two states can be switched by applying different external voltage stimuli. Meanwhile, due to the nonvolatile characteristic, the resistance value of the resistance change memory still does not change after the voltage excitation is removed. The structure of the resistive random access memory is quite simple, and is similar to the capacitor structure and is a metal-resistive random layer-metal sandwich structure. The structure is quite simple, and the characteristic dimension area can be reduced to 4F in theory 2 The method is quite suitable for integrating the memory array of the Crossbar structure. In addition, 3D Crossbar or 3D vertical integration similar to conventional flash memory can be formed by stacking Crossbar structures in multiple layersThe integration density of the resistive random access memory is improved in one step.
However, for a resistive random access memory in a memory array, leakage current in the array needs to be considered in design. In a memory array, when one memory device is selected through word lines (word lines) and bit lines (bit lines), other half-selected memory devices provide some leakage current due to the voltage application. In the worst case, when a device of a high resistance state is selected, the surrounding devices are all of a low resistance state, and the surrounding high leakage current will cover the low current that would have been from only the high resistance state device, resulting in a read error. Due to the existence of leakage current, reading errors can occur, and meanwhile power consumption can be increased, so that large-scale integration of the resistive random access memory is not facilitated.
In order to solve the problem of leakage current faced in the integration of a resistive memory array, there are two general solutions when integrating a resistive memory: namely a 1T1R (One-transmitter One-RRAM) structural unit and a 1S1R (One-Selector One-RRAM) structural unit. The common design concept of the two structures is to shut down the other resistive random access memory when one resistive random access memory is selected, so that the resistance value of the other resistive random access memory is infinite (ideal), and the interference is weakened. The 1T1R structure is to control each cell by connecting a transistor (transistor) in series to the resistive random access memory. This approach can solve the leakage current problem, but the area of each cell increases due to the introduction of the transistor, impairing the integration advantage of the resistive random access memory itself. The other is a 1S1R structure, a selection device (selector) and RRAM are directly integrated into a storage unit, the selection device has switching characteristics under different voltage excitation, and the selection device is also in a sandwich structure, and the area of the selection device is almost the same as that of a resistive random access memory. The smaller area of the 1s1r cell compared to the 1t1r is advantageous for forming a higher density of integration.
The current 1S1R structure is typically a metal-resistive layer-metal-selective thin film-metal. Due to the common intermediate metal, it is difficult to realize a 3D vertical structure within 1 via. Meanwhile, for the crossbar structure, the intermediate metal is also very complex to process.
Disclosure of Invention
In view of the above-mentioned shortcomings, the present invention proposes a dual-film resistive random access memory and a method for manufacturing the same, based on the implementation of a resistive random access memory device with self-selection by using a conventional CMOS process, so as to reduce or even eliminate the crosstalk problem existing in the crossbar structure of the resistive random access memory.
In order to solve the technical problems, the invention adopts the following technical scheme:
a dual-mode resistive random access memory comprises a substrate and a bottom electrode-resistive random access layer-self-selection layer-top electrode structure positioned on the substrate.
Further, the bottom electrode-resistive layer-self-selection layer-top electrode structure is a Metal-Insulator-Metal (Metal-Insulator-Metal) capacitor structure or a Metal-Semiconductor-Metal (Metal-Semiconductor-Metal) capacitor structure.
Further, the substrate is made of silicon or glass;
the bottom electrode and the top electrode are made of metal materials, and the thickness of the bottom electrode and the top electrode is 10nm-200nm;
the resistance change layer adopts transition metal oxide with resistance change characteristics, and the thickness is 5nm-100nm; or organic material with thickness of 200nm-500nm;
the self-selection layer is a film with IMT (Insulator-Metal Transition) characteristics, the film is in Insulator characteristics when the voltage value is lower than the threshold voltage, and is in Metal characteristics when the voltage value is higher than the threshold voltage, and the thickness of the film is 1nm-100nm by adopting oxide.
Further, the metal material is Ti, al, au, W, cu, ta, pt, ir or TiN, taN and other materials;
the transition metal oxide is TaO x 、HfO x 、SiO x Or SrTiO 3 The organic material is parylene;
the oxide is VO 2 、NbO 2 GST, etc.
A preparation method of a dual-mode resistive random access memory comprises the following steps:
1) Defining a bottom electrode pattern, and preparing a bottom electrode on the substrate according to the pattern;
2) Depositing a resistive layer on the bottom electrode by adopting a PVD (physical vapor deposition), ALD (atomic layer deposition) or CVD (chemical vapor deposition) method;
3) Depositing a self-selection layer on the resistance change layer by adopting a PVD (physical vapor deposition) or ALD (atomic layer deposition) method, and applying a corresponding annealing treatment procedure according to the material property;
4) Defining a bottom electrode lead-out hole pattern, and etching a bottom electrode lead-out hole in the resistive layer and the self-selection layer according to the pattern;
5) A top electrode pattern is defined, according to which a top electrode is prepared on the self-selected layer.
Further, the method of defining the pattern in the steps 1), 4) and 5) is to define the pattern on the photoresist by using a photolithography technique.
Further, the preparation method of the bottom electrode and the top electrode comprises a PVD or evaporation deposition method.
Further, the resistive layer adopts transition metal oxide with resistive characteristics, and the thickness is 5nm-100nm; or organic material with thickness of 200nm-500nm.
Further, the self-selection layer adopts VO 2 、NbO 2 Or GST, with a thickness of 1nm to 100nm.
The invention provides a self-selection dual-mode resistive random access memory and a preparation method thereof, wherein a film with selection characteristics is inserted into the resistive random access memory to form a double-layer structure, and the combination of a resistive random access layer, a self-selection layer and electrode materials is reasonably designed to optimize the current-voltage characteristics of the resistive random access memory, so that the resistive random access memory shows symmetrical bidirectional self-selection characteristics. The resistive random access memory has symmetrical bidirectional self-selection characteristics, and the crossbar array formed by the resistive random access memory can effectively inhibit leakage current due to the existence of the self-selection characteristics, namely the low resistance state or the high resistance state, and the resistance value on the original leakage current path is far greater than the resistance value to be read, so that misreading is avoided. The device lays a road for realizing the area reduction of the resistive random access memory and large-scale integration.
Drawings
FIG. 1 is a graph showing the current-voltage characteristics of the dual mode resistive random access memory.
In the figure: s1-a resistance change process from a high resistance state to a low resistance state under the excitation of forward voltage; s2-a low-resistance state maintaining process; s3-a forward low-resistance state self-selection process; s4-a negative low-resistance state self-selection process; s5, a resistance change process from a low resistance state to a high resistance state under the excitation of negative voltage; s6, a high-resistance state maintaining process.
FIG. 2 is a schematic diagram of a crossbar array and leakage current.
Fig. 3A-3E are schematic views of the preparation process in example 1, and fig. 3F is a schematic illustration of fig. 3A-3E.
Detailed Description
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Example 1
The embodiment provides a dual-mode resistive random access memory and a preparation method thereof, wherein the resistive random access memory adopts a silicon substrate, adopts TiN as a bottom electrode material and adopts HfO 2 (or non-stoichiometric oxide thereof) as the material of the resistive layer, VO is adopted 2 As the self-selective layer, tiN was used as the top electrode material.
HfO 2 And VO (Voice over Internet protocol) 2 Are materials compatible with standard CMOS processes. Based on HfO 2 The resistive random access memory has the advantages of ultra-fast switching speed, high switching ratio and good holding characteristic. VO (VO) 2 As a common film with selective properties, it is simple to prepare and very controllable. The advantages of the two materials are combined, and the reasonable design of the physical mechanism layer meets the requirements of compatible CMOS technology, can realize the bidirectional self-selection characteristic of the resistive random access memory, and has important significance for improving the integration density of the resistive random access bar structure array and producing the resistive random access memory on a large scale.
The preparation method of the resistive random access memory comprises the following steps:
1) Defining a bottom electrode pattern on the photoresist by utilizing a photoetching technology, depositing a TiN bottom electrode material on the silicon substrate by adopting a PVD method, wherein the thickness is 70nm, and removing the photoresist, as shown in FIG. 3A;
2) Depositing a layer of HfO on the bottom electrode by ALD method 2 The thickness of the resistive layer film material is 6nm, as shown in FIG. 3B;
3) Depositing a layer of VO on the resistive layer by ALD method 2 The energy band modification layer (namely the self-selective layer) material realizes bidirectional nonlinear self-rectification, and the thickness is 30nm, as shown in figure 3C;
4) Firstly, defining a bottom electrode lead-out hole pattern on photoresist by using a photoetching technology, etching a bottom electrode lead-out hole on the resistance change layer and the self-selection layer by using a dry etching method, and removing the photoresist, wherein the figure 3D is shown;
5) Defining a top electrode pattern on the photoresist by using a photoetching technology, depositing a TiN top electrode material with the thickness of 100nm on the energy band modification layer (namely the self-selection layer) by using a PVD method, and removing the photoresist to obtain the self-selection resistance random access memory, as shown in figure 3E.
Example 2
The embodiment also provides a dual-mode resistive random access memory and a preparation method thereof, wherein the resistive random access memory adopts TaN as a bottom electrode material and adopts TaO x As the material of the resistive layer, nbO is adopted 2 And the self-selective layer adopts TaN as a top electrode material.
The preparation method of the resistive random access memory comprises the following steps:
1) Defining a bottom electrode pattern on the photoresist by utilizing a photoetching technology, depositing a TaN bottom deposition material on a silicon substrate by adopting a PVD method, wherein the thickness is 20nm, and removing the photoresist;
2) Depositing a TaO layer on the bottom electrode by PVD method x The thickness of the resistive layer film material is 30nm;
3) Depositing a layer of NbO on the resistive layer by PVD method 2 The material realizes bidirectional nonlinear self-rectification, and the thickness is 40nm;
4) Firstly defining a bottom electrode lead-out hole pattern on photoresist by using a photoetching technology, etching a bottom electrode lead-out hole on the resistance change layer and the self-selection layer by using a dry etching method, and removing the photoresist;
5) Defining a top electrode pattern on the photoresist by utilizing a photoetching technology, depositing a TaN top electrode material on the self-selection layer by adopting a PVD method, wherein the thickness is 100nm, and removing the photoresist to obtain the self-selection resistive random access memory.
As can be seen from the above examples, the preparation of the transition metal oxide resistive layer thin film material and the self-selecting material can be performed by either PVD or ALD, which can be made thinner than PVD; the preparation of the organic material as the resistance change layer adopts a CVD method.
For the dual-mode resistive random access memory provided by the invention, a resistive random access test is carried out on a device through DC sweep, the obtained current-voltage (I-V) characteristic is shown as a figure 1, and in the figure, S1 is a resistive random access process from a high resistance state to a low resistance state under the excitation of forward voltage; s2, a low-resistance state maintaining process; s3, a forward low-resistance state self-selection process; s4, a negative low-resistance state self-selection process; s5, a resistance change process from a low resistance state to a high resistance state under the excitation of negative voltage; s6, a high-resistance state maintaining process. During testing, the bottom electrode of the device is grounded, and voltage shown in the figure is applied to the top electrode, so that the resistance value of the device is converted between high resistance and low resistance, and the resistance change effect can be proved. At the same time, under the operation of positive and negative voltages, the current-voltage characteristic curve can show the self-selection characteristic which is approximately symmetrical.
By integrating the self-selection film and the resistive film, the characteristics that the self-selection film is an insulator under low voltage and is a metal conductor higher than threshold voltage are utilized, and the resistive voltage of the resistive film and the switching voltage of the self-selection film are reasonably matched, so that the self-selection dual-mode resistive memory is realized.
FIG. 2 is a schematic diagram of a crossbar array and leakage current, in which it is known that the magnitude of the current flowing through the device needs to be read to determine whether the device is in a high-resistance state or a low-resistance state due to the reading of the resistance of the device in the array. In the worst case, if one device in the crossbar array is to be read, and all surrounding devices are in a low-resistance state, when the device in the high-resistance state is read, current bypasses the device in the high-resistance state, and leakage current is formed on the surrounding low-resistance devices. In this case, in the crossbar structure, the shortest path through which the leakage current flows is as shown in the unselected three devices in fig. 2, that is, when the selected device (the device in the dashed line in the figure) is the Vread voltage, the actual voltage division of each device on the crosstalk path is half of Vread, and the read current is actually the leakage current flowing through the surrounding devices in the low resistance state, resulting in misreading. If the device adopts the self-selection resistive random access memory provided by the invention, the current in the high resistance state of Vread reading is larger than the low resistance state current of Vread reading by one half as shown in the current-voltage curve of FIG. 1, namely the resistance of the reading path is smaller than the crosstalk path due to the self-selection effect of the low resistance state, so that the crosstalk is effectively restrained, and the current in the negative voltage state is also effectively restrained. Therefore, the bidirectional self-selection effect in the low-resistance state can effectively inhibit the leakage current in the crossbar array.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and those skilled in the art may modify or substitute the technical solution of the present invention without departing from the spirit and scope of the present invention, and the protection scope of the present invention shall be defined by the claims.
Claims (6)
1. The dual-mode resistive random access memory is characterized by comprising a substrate and a bottom electrode-resistive random access layer-self-selection layer-top electrode structure positioned on the substrate; wherein, the liquid crystal display device comprises a liquid crystal display device,
the resistance change layer adopts HfO 2 VO is adopted from the selection layer 2 The thickness of the self-selection layer is 1nm-100nm, and the bottom electrode and the top electrode are made of metal materials Ti, al, au, W, cu, ta, pt, ir, tiN or TaN; or alternatively
TaO is adopted as the resistance change layer x The self-selection layer adopts NbO 2 The thickness of the self-selection layer is 40nm-100nm, the self-selection layer is deposited on the resistive layer by adopting a PVD or ALD method, and an annealing treatment procedure is applied; the bottom electrode adopts Ti, al, au, W, cu, ta, pt, ir, tiN or TaN; the top electrode is Cu, ta, al, tiN, ti or W.
2. The dual mode resistive random access memory of claim 1, wherein the substrate is silicon or glass.
3. The dual mode resistive random access memory of claim 1 or 2, wherein the bottom electrode and the top electrode each have a thickness of 10nm to 200nm; the thickness of the resistance change layer is 5nm-100nm.
4. A method for preparing the dual-mode resistive random access memory, which is used for preparing the dual-mode resistive random access memory according to any one of claims 1 to 3, and is characterized by comprising the following steps:
1) Defining a bottom electrode pattern, and preparing a bottom electrode on the substrate according to the pattern;
2) Depositing a resistive layer on the bottom electrode by adopting a PVD (physical vapor deposition), ALD (atomic layer deposition) or CVD (chemical vapor deposition) method;
3) Depositing a self-selection layer on the resistance change layer by adopting a PVD (physical vapor deposition) or ALD (atomic layer deposition) method, and applying an annealing treatment procedure;
4) Defining a bottom electrode lead-out hole pattern, and etching a bottom electrode lead-out hole in the resistive layer and the self-selection layer according to the pattern;
5) A top electrode pattern is defined, according to which a top electrode is prepared on the self-selected layer.
5. The method of claim 4, wherein the method of defining the pattern in steps 1), 4) and 5) is: a pattern is defined on the photoresist using photolithography techniques.
6. The method of claim 4, wherein the bottom and top electrode are prepared by a PVD or vapor deposition process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910903216.1A CN110783453B (en) | 2019-09-24 | 2019-09-24 | Dual-mode resistive random access memory device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910903216.1A CN110783453B (en) | 2019-09-24 | 2019-09-24 | Dual-mode resistive random access memory device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110783453A CN110783453A (en) | 2020-02-11 |
| CN110783453B true CN110783453B (en) | 2024-02-09 |
Family
ID=69383766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910903216.1A Active CN110783453B (en) | 2019-09-24 | 2019-09-24 | Dual-mode resistive random access memory device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110783453B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653666A (en) * | 2020-06-12 | 2020-09-11 | 北京大学 | Gating device, resistive random access memory and operation method thereof |
| CN111969109B (en) * | 2020-09-01 | 2023-09-19 | 厦门半导体工业技术研发有限公司 | Resistive random access memory, resistive random access element and preparation method thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855304A (en) * | 2012-11-29 | 2014-06-11 | 爱思开海力士有限公司 | Variable resistance memory device |
| US9177916B1 (en) * | 2014-11-25 | 2015-11-03 | Intermolecular, Inc. | Amorphous silicon doped with fluorine for selectors of resistive random access memory cells |
| CN105870321A (en) * | 2016-03-28 | 2016-08-17 | 北京大学 | Nonlinear self-rectifying resistive random access memory and preparation method therefor |
| CN106463340A (en) * | 2015-01-05 | 2017-02-22 | 王士原 | Resistive random-access memory with implanted and radiated channels |
| CN106711327A (en) * | 2015-11-13 | 2017-05-24 | 台湾积体电路制造股份有限公司 | Metal-insulator-metal (MIM) capacitor structure and method of fabrication thereof |
| WO2017131642A1 (en) * | 2016-01-26 | 2017-08-03 | Hewlett Packard Enterprise Development Lp | Resistive memory cell including a selector |
| CN108258115A (en) * | 2018-03-16 | 2018-07-06 | 湖北大学 | A kind of 1S1R devices and its manufacturing method based on niobium oxide gate tube and zirconium oxide change resistance layer |
| CN108493336A (en) * | 2018-03-28 | 2018-09-04 | 中国科学院微电子研究所 | Self-rectifying resistance-variable storing device and preparation method thereof |
| CN109065710A (en) * | 2018-07-25 | 2018-12-21 | 清华大学 | A kind of gate device architecture and the preparation method and application thereof based on multilevel oxide film |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101482814B1 (en) * | 2007-07-25 | 2015-01-14 | 인터몰레큘러 인코퍼레이티드 | Multistate nonvolatile memory elements |
| US8053364B2 (en) * | 2008-05-01 | 2011-11-08 | Intermolecular, Inc. | Closed-loop sputtering controlled to enhance electrical characteristics in deposited layer |
| KR101257365B1 (en) * | 2011-07-22 | 2013-04-23 | 에스케이하이닉스 주식회사 | Resistive RAM of having threshold switching operation and Method of fabricating the same |
| WO2013119617A1 (en) * | 2012-02-06 | 2013-08-15 | President And Fellows Of Harvard College | Electrically-driven phase transitions in functional oxide heterostructures |
| KR20150011793A (en) * | 2012-04-25 | 2015-02-02 | 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. | Nonlinear memristors |
| JP2014216647A (en) * | 2013-04-29 | 2014-11-17 | エーエスエムアイピー ホールディング ビー．ブイ． | Method for manufacturing resistive random access memory having metal-doped resistive switching layer |
-
2019
- 2019-09-24 CN CN201910903216.1A patent/CN110783453B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855304A (en) * | 2012-11-29 | 2014-06-11 | 爱思开海力士有限公司 | Variable resistance memory device |
| US9177916B1 (en) * | 2014-11-25 | 2015-11-03 | Intermolecular, Inc. | Amorphous silicon doped with fluorine for selectors of resistive random access memory cells |
| CN106463340A (en) * | 2015-01-05 | 2017-02-22 | 王士原 | Resistive random-access memory with implanted and radiated channels |
| CN106711327A (en) * | 2015-11-13 | 2017-05-24 | 台湾积体电路制造股份有限公司 | Metal-insulator-metal (MIM) capacitor structure and method of fabrication thereof |
| WO2017131642A1 (en) * | 2016-01-26 | 2017-08-03 | Hewlett Packard Enterprise Development Lp | Resistive memory cell including a selector |
| CN105870321A (en) * | 2016-03-28 | 2016-08-17 | 北京大学 | Nonlinear self-rectifying resistive random access memory and preparation method therefor |
| CN108258115A (en) * | 2018-03-16 | 2018-07-06 | 湖北大学 | A kind of 1S1R devices and its manufacturing method based on niobium oxide gate tube and zirconium oxide change resistance layer |
| CN108493336A (en) * | 2018-03-28 | 2018-09-04 | 中国科学院微电子研究所 | Self-rectifying resistance-variable storing device and preparation method thereof |
| CN109065710A (en) * | 2018-07-25 | 2018-12-21 | 清华大学 | A kind of gate device architecture and the preparation method and application thereof based on multilevel oxide film |
Non-Patent Citations (4)
| Title |
|---|
| Co-Occurrence of Threshold Switching and Memory Switching in Pt/NbOx/Pt Cells for Crosspoint Memory Applications;Xinjun Liu et al.;《IEEE ELECTRON DEVICE LETTERS》;20120229;第33卷(第2期);第236-238页 * |
| Integration of a niobium oxide selector on a tantalum oxide memristor by local oxidation using Joule heating;Leon, JJD et al.;LOW-DIMENSIONAL MATERIALS AND DEVICES 2016》;第9934卷;第1-5页 * |
| Leon, JJD et al..Integration of a niobium oxide selector on a tantalum oxide memristor by local oxidation using Joule heating.LOW-DIMENSIONAL MATERIALS AND DEVICES 2016》.2017,第9934卷第1-5页. * |
| Xinjun Liu et al..Co-Occurrence of Threshold Switching and Memory Switching in Pt/NbOx/Pt Cells for Crosspoint Memory Applications.《IEEE ELECTRON DEVICE LETTERS》.2012,第33卷(第2期),第236页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110783453A (en) | 2020-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10340312B2 (en) | Memory element with a reactive metal layer | |
| EP1858074B1 (en) | Nonvolatile memory device using oxygen-deficient metal oxide layer and method of manufacturing the same | |
| CN101106171B (en) | Non-volatile memory device including variable resistance material | |
| TWI540775B (en) | Resistance change nonvolatile memory device, semiconductor device, and method of operating resistance change nonvolatile memory device | |
| KR100668348B1 (en) | Nonvolatile memory device and fabrication method of the same | |
| US20150140772A1 (en) | Using multi-layer mimcaps with defective barrier layers as selector element for a cross bar memory array | |
| US10056432B2 (en) | Self-rectifying RRAM cell structure having two resistive switching layers with different bandgaps and RRAM 3D crossbar array architecture | |
| CN110783453B (en) | Dual-mode resistive random access memory device and preparation method thereof | |
| US20160093802A1 (en) | Self-rectifying resistive random access memory cell structure | |
| CN105870321B (en) | A kind of non-linear self-rectifying resistance-variable storing device and preparation method thereof | |
| CN102005536A (en) | Improved NiO-based resistive random access memory (RRAM) and manufacturing method thereof | |
| US20130217199A1 (en) | Method for fabricating resistive memory device | |
| CN101577311A (en) | One-time programming memory and manufacturing method thereof | |
| CN110752293A (en) | Bidirectional threshold switch selection device and preparation method thereof | |
| WO2013120285A1 (en) | Semiconductor memory device and access method therefor | |
| US20170062522A1 (en) | Combining Materials in Different Components of Selector Elements of Integrated Circuits | |
| US10297748B2 (en) | Three-terminal atomic switching device and method of manufacturing the same | |
| CN116634853A (en) | Resistive random access memory and preparation method thereof | |
| CN116600631A (en) | Resistive random access memory and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |