CN116634853A - Resistive random access memory and preparation method thereof - Google Patents

Resistive random access memory and preparation method thereof Download PDF

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Publication number
CN116634853A
CN116634853A CN202310450080.XA CN202310450080A CN116634853A CN 116634853 A CN116634853 A CN 116634853A CN 202310450080 A CN202310450080 A CN 202310450080A CN 116634853 A CN116634853 A CN 116634853A
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layer
random access
resistive
access memory
resistive random
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高飞
仇圣棻
杨芸
陈亮
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Xinyuan Semiconductor Hangzhou Co ltd
Xinyuan Semiconductor Shenzhen Co ltd
Xinyuan Semiconductor Shanghai Co ltd
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Xinyuan Semiconductor Hangzhou Co ltd
Xinyuan Semiconductor Shenzhen Co ltd
Xinyuan Semiconductor Shanghai Co ltd
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Publication of CN116634853A publication Critical patent/CN116634853A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/253—Multistable switching devices, e.g. memristors having three or more electrodes, e.g. transistor-like devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Semiconductor Memories (AREA)

Abstract

The application provides a resistance random access memory and a preparation method thereof. The chemical mechanical polishing is realized only by polishing the through hole filling layer to a preset thickness, so that the occurrence of concave or convex of a filling structure of the lower electrode through hole is avoided, and the influence on the resistance change layer is further reduced; thereby achieving the technical effect of reducing the function and the difference between the structures of the resistive switching structures on the same wafer.

Description

Resistive random access memory and preparation method thereof
Technical Field
The application relates to the technical field of resistive random access memories, in particular to a resistive random access memory and a preparation method thereof.
Background
The resistive random access memory (ReRAM, resistive Random Access Memory) is receiving more and more attention due to its advantages of low voltage, high speed, low power consumption, simple structure, compatibility with CMOS (Complementary Metal Oxide Semiconductor ) conventional technology, low cost, high density, etc., and is considered as a new memory which is a mainstream memory product that may replace flash memories for the next generation. RRAM is typically a 3-layer structure formed of a metal-resistive medium-metal stack that utilizes the resistance of the high and low states to store data, and the resistance of the resistive film material of the intermediate layer can be resistance switched by applying voltages of different polarities and magnitudes across the device. The key structure of RRAM is a resistance change material structure, and a TiN/TaO/Ta/TiN structure is used, and the structure is used for storing data by forming and breaking a conductive channel to realize reversible transition between a high-resistance state and a low-resistance state under positive voltage and negative voltage.
The existing preparation process flow of the resistive random access memory is shown in figure 1, firstly, chemical Mechanical Polishing (CMP) is carried out after a through hole (via) of a lower electrode (BE) is filled through film deposition, photoetching, etching and film deposition until the upper surfaces of carbon-containing silicon nitride structures on two sides of the through hole are exposed, and then the preparation of the lower electrode is completed; and then performing film deposition to complete the preparation of a Gap film (Gap film) of an upper electrode (TE), and finally completing the whole preparation of the resistive random access memory through photoetching and etching.
The existing preparation process has the following defects: the alignment Mark signal and the OVL Mark Damage which are needed by photoetching are influenced, so that the process is influenced, and the process window is reduced.
Therefore, there is a need for a method for manufacturing a resistive random access memory that reduces the impact of polishing.
Disclosure of Invention
The application aims to provide a resistive random access memory and a preparation method thereof, which are used for solving at least one problem existing in the prior art.
In order to achieve the above object, the present application provides a method for manufacturing a resistive random access memory, the method comprising:
depositing a via filling layer for filling the lower electrode via on the dielectric layer;
grinding the through hole filling layer until the thickness of the through hole filling layer covered on the dielectric layer reaches a set thickness threshold value;
sequentially depositing a resistive layer and an upper electrode on the via filling layer;
and etching the through hole filling layer, the resistive layer and the upper electrode to form a resistive structure of the resistive random access memory.
Further, the preferred method includes, prior to the step of sequentially depositing the resistive layer and the upper electrode on the via fill layer, further comprising,
and depositing a metal layer on the through hole filling layer, and sequentially depositing a resistance change layer and an upper electrode on the metal layer.
Further, the preferred method includes the steps of depositing a metal layer on the via fill layer, depositing a resistive layer and an upper electrode sequentially on the metal layer, including,
depositing a first metal layer on the via filling layer;
and sequentially depositing a second metal layer, a resistance change layer and an upper electrode on the first metal layer.
Further, the preferred method includes, after the step of depositing a metal layer on the via fill layer and sequentially depositing a resistive layer and an upper electrode on the metal layer, further includes,
photoetching and etching the resistive layer and the upper electrode; depositing a growth side wall protection layer on the side surface of the resistance change layer, the surface and the side surface of the upper electrode and the surface of the metal layer;
and etching the through hole filling layer, the metal layer and the side wall protection layer to form the resistive random access memory resistive random access structure.
Further, the preferred method includes that the material of the via filling layer is TaN or W.
Further, a preferred method includes that the material of the metal layer is W, lr, ru or Pt.
Further, a preferred method includes setting the thickness of the via filling layer to 10nm to 160nm.
Further, a preferred method includes setting the thickness of the via filling layer to 10nm to 90nm.
In a second aspect, the present application provides a resistive random access memory, including a dielectric layer having a lower electrode via therein and a via fill layer for filling the lower electrode via; the through hole filling layer is an isolation dielectric film with a set thickness and covered on the dielectric layer; and a resistive layer and an upper electrode are sequentially laminated on the through hole filling layer. Further, it is preferable that a metal layer is provided between the resistive layer and the via filling layer. Further, it is preferable that the metal layer includes a first metal layer and a second metal layer.
In a third aspect, the present application provides a memory cell comprising a gate and a resistive random access memory coupled to the gate. Wherein the gate may be a three-terminal gate device.
In a fourth aspect, the present application provides a memory device, where the memory device includes a memory controller and a resistive random access memory, and the memory controller is configured to read and write data from and to the resistive random access memory.
In a fifth aspect, the present application provides an electronic device, including a circuit board and a resistive random access memory connected to the circuit board.
As described above, according to the resistive random access memory, the preparation method thereof, the memory unit, the memory device and the electronic device, the grinding stopping point of the through hole filling layer is changed. The beneficial effects are as follows:
the chemical mechanical polishing only needs to polish the through hole filling layer to a preset thickness, so that the occurrence of concave or convex of a filling structure of a lower electrode through hole is avoided, the influence on the resistive layer is further reduced, and the occurrence of serious Loading conditions of a current chip and a wafer and the serious Loading conditions of ISO and Density areas in the same chip are avoided; the influence of an alignment Mark signal and an OVL Mark Damage which are needed by photoetching is avoided, so that the technical effects of ensuring a resistance change storage structure process and improving a process window are achieved.
To the accomplishment of the foregoing and related ends, one or more aspects of the application comprise the features hereinafter fully described and particularly pointed out in the claims. The following description details certain exemplary aspects of the application. These aspects are indicative, however, of but a few of the various ways in which the principles of the application may be employed. Furthermore, the application is intended to include all such aspects and their equivalents.
Drawings
FIG. 1 is a schematic diagram of a process flow for manufacturing a conventional resistive random access memory;
FIG. 2 is a schematic diagram of a resistive random access memory according to embodiment 1 of the present application;
FIG. 3 is a schematic flow chart of a method for manufacturing a resistive random access memory according to embodiment 1 of the present application;
fig. 4 is a schematic diagram of the structure of a resistive random access memory according to embodiment 2 of the present application;
FIG. 5 is a schematic diagram of a manufacturing process of a resistive random access memory according to embodiment 2 of the present application;
fig. 6 is a schematic diagram of the structure of a resistive random access memory according to embodiment 3 of the present application.
In the drawing, 1, a lower electrode through hole; 2. a dielectric layer; 3. a via filling layer; 4. a metal layer; 5. a resistive layer; 6. an upper electrode; 7. a sidewall protection layer; 41. a first metal layer; 42. a second metal layer.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. The specific techniques or conditions are not noted in the examples, and the reagents or apparatus used, or the manufacturer, may be purchased from a regular distributor, following the techniques or conditions described in the literature in the field, or following the product specifications.
Memory (memory) is a memory device used in modern information technology to hold information. The main function of the memory is to store various data (e.g., service data, program data). Memory typically employs a physical device (e.g., a memory cell) having two stable states (denoted "0" and "1", respectively) to implement a memory function. The memory may store data based on how much charge is stored. Such as dynamic random access memory and flash memory, are typically based on how much charge is stored to characterize the stored data. The memory may also be characterized as storing data based on the magnitude of the resistance. For example, resistive random access memories typically store data based on a device resistance magnitude characterization. Resistive random access memory is a nonvolatile memory with adjustable resistance. The resistive random access memory unit structure adopts an MIM capacitor structure, and an insulating layer or a semiconductor functional material layer, also called a sandwich structure (Sandwich Structrue), is sandwiched between an upper electrode and a lower electrode. Specifically, the resistive random access memory can realize a memory function by controlling the movement of oxygen ions to control the resistance of the device. The memory array may employ a crossbar cross array structure. The cross array structure has simple process, high density and better geometric reduction capability.
FIG. 1 is a schematic diagram showing a manufacturing flow of a conventional resistive random access memory; in the polishing step, as shown in fig. 1 in the prior art, the surface of the filling structure of the bottom electrode via needs to be polished until the upper surfaces of the carbon-containing silicon nitride structures (i.e., film 3) on both sides of the via are exposed. Because the chemical mechanical polishing needs to polish the filling structure layer (i.e. film 4) of the through hole and the carbon-containing silicon nitride structure layers (i.e. film 3) on two sides of the through hole at the same time, the difference of materials to be polished is easy to polish unevenness, so that the filling structure of the through hole of the lower electrode is concave or convex; the upper part of the lower electrode through hole is closely arranged to form a resistance change structure consisting of a resistance change layer. The effect on the resistive random access memory is as follows: 1) The process window for chemical mechanical polishing is small, the Loading of the current width in Die and width in wafer is serious, and even the Loading of ISO and Density areas in the same chip is serious; 2) Thereby triggering Alignment Mark/OVL Mark damage to thereby cause OVL Shift and also influence the structural function of the resistance change structure; 3) Meanwhile, the functions and the differences between the structures of the resistive switching structures on the same wafer are increased; 4) The Alignment Mark signal (Alignment Mark) and the OVL Mark Damage which are needed by photoetching can be caused, so that the process is influenced, and the process window is reduced.
Example 1
In order to illustrate the resistive random access memory, the preparation method and the electronic device diagram provided by the application. Fig. 2 shows the structure of an RRAM according to embodiment 1 of the present application. Fig. 3 shows a flow of a method for manufacturing an RRAM structure according to embodiment 1 of the present application.
As shown in fig. 2, the present application provides a resistive random access memory comprising a dielectric layer 2 having a lower electrode via 1 therein and a via filling layer 3 for filling the lower electrode via 1; the through hole filling layer 3 is an isolating dielectric film with set thickness covered on the dielectric layer 2; a resistive layer 5 and an upper electrode 6 are sequentially laminated on the via filling layer 3.
That is, the physical vapor deposition or atomic layer deposition process is adopted to deposit the lower electrode layer on the surface of the dielectric layer and in the lower electrode through hole; depositing a through hole filling layer serving as an isolation medium on the surface of the lower electrode layer by adopting a chemical vapor deposition process; in the prior art, a chemical mechanical polishing process is used to planarize the via fill layer to remove the film layer above the dielectric layer, leaving only the fill structure in the bottom electrode via. In the application, the grinding stopping point of the through hole filling layer is changed, and the through hole filling layer is grinded by adopting chemical machinery until the thickness of the through hole filling layer covered on the dielectric layer reaches the set thickness. The resistive material layer of the resistive memory can be one or more of Ni, ti, al, ta, hf transition metal oxides. The resistive switching mechanism of such materials is mainly due to the movement of oxygen ions to form oxygen vacancy conductive filaments, and at the same time, the number of defects in the resistive switching material layer will also directly affect the resistive switching characteristics of the device. In this case, the resistive layer may be formed on the electrode layer by atomic layer deposition, sputtering, or the like. The thickness of the resistive layer can be set according to practical requirements. For example, a resistive layer 8nm thick can be formed on the lower electrode by atomic layer deposition. The material of the resistance change layer can be selected according to practical requirements, for example, the material of the resistance change layer can be HfOx, niO, tiO 2 、Al 2 O 3 、Ta 2 O 5 Waiting for passingAny one of the transition metal oxides. The lower electrode is typically formed of a metallic material. The metallic material includes, but is not limited to, copper, aluminum, titanium nitride, silver, nickel, platinum, palladium. Based on this, the lower electrode can be generated by PVD, and the upper electrode can be generated by sputtering or the like, for example. In some embodiments, the thickness of the upper electrode may be equal to the thickness of the lower electrode, which may be 20nm, for example. In other embodiments, the thickness of the upper electrode may not be equal to the thickness of the lower electrode. Similarly, the material of the upper electrode may be the same as that of the lower electrode, and for example, may be TiN. In some embodiments, the material of the upper electrode may also be different from the material of the lower electrode.
The filling material of the via filling layer 3 may be, but is not limited to, taN and W. The thickness of the via filling layer is set to 10nm to 160nm, preferably 10nm to 90nm. In the application, a through hole filling layer (namely, a film 4) with the top surface consistent with the height of a carbon-containing silicon nitride structural layer (namely, a film 3) at two sides of the through hole is mainly changed into a through hole filling layer with a certain thickness which is entirely covered on the film3 and the lower electrode.
As shown in fig. 3, the application provides a method for preparing a resistive random access memory, which comprises the following steps:
s110, depositing a through hole filling layer 3 for filling the lower electrode through hole 1 on the dielectric layer 2;
s120, grinding the through hole filling layer 3 until the thickness of the through hole filling layer 3 covered on the dielectric layer 2 reaches a set thickness threshold;
s130, sequentially depositing a resistive layer 5 and an upper electrode 6 on the through hole filling layer 3;
and S140, etching the through hole filling layer 3, the resistance change layer 5 and the upper electrode 6 to form a resistance change structure of the resistance change memory.
In a specific implementation, the operation steps for obtaining the resistive random access memory shown in fig. 2 include cleaning the substrate, and growing film 1 and film 2 and film3 as dielectric layer 2 in sequence; the deposition generating film4 fills the lower electrode through hole 1, and the film4 is ground (CMP) until the thickness value of the through hole filling structure reaches a preset thickness threshold value; a resistive layer 5 (film 5) and an upper electrode 6 (film 6) are deposited in sequence on the film 4; photoetching the resistive layer 5 and the upper electrode 6; etching the resist layer 5 and the upper electrode 6 after photoetching; depositing a growth sidewall protection layer 7 (film 7) on the side of the resistive layer 5, the surface of the upper electrode 6 and the side; and etching the side wall protection layer 7 to obtain the resistive random access memory resistive random access structure protruding on the dielectric layer 2 and the lower electrode.
That is, the present application adjusts the stop point of the grinding, changing from the current grinding of all the films on the film3 to not grinding all the films on the film 3; according to the application, different film structures do not need to be ground at the same time, the residual films are etched by subsequent etching, the problem caused by Loading is solved, a process window is increased, and the difference between RRAM unit structure functions and RRAM unit structure functions is optimized. By changing the grinding stopping point, a through hole filling layer with a preset thickness is arranged before the deposition of the resistive layer of the resistive memory, so that the chemical mechanical grinding is realized only by grinding the through hole filling layer to the preset thickness, the situation that the through hole filling layer is flattened to remove a film layer above a dielectric layer by adopting a chemical mechanical polishing process and the filling structure in a lower electrode through hole is ground to the film3 is only reserved, or the filling structure in the lower electrode through hole is insufficiently protruded out of the plane of the film3 because of grinding is avoided; the influence on the resistive layer is further reduced, and the serious Loading conditions of the current chip and the wafer and the Loading conditions of ISO and Density areas in the same chip are avoided; the influence of an alignment Mark signal and an OVL Mark Damage which are needed by photoetching is avoided, so that the process of guaranteeing a resistance change storage structure is achieved, and a process window is improved; thereby achieving the technical effect of reducing the function and the difference between the structures of the resistive switching structures on the same wafer.
Example 2
In order to illustrate the resistive random access memory and the preparation method thereof. Fig. 4 shows the structure of an RRAM according to embodiment 2 of the present application. Fig. 5 shows a preparation process of the RRAM according to example 2 of the present application.
As shown in fig. 4, in order to further enhance the stability of the resistive random access memory, the present embodiment provides a resistive random access memory including a dielectric layer 2 having a lower electrode via 1 therein and a via filling layer 3 for filling the lower electrode via 1; the through hole filling layer 3 is an isolating dielectric film with set thickness covered on the dielectric layer 2; a resistive layer 5 and an upper electrode 6 are sequentially laminated on the through hole filling layer 3; a metal layer 4 is provided between the resistive layer 5 and the via filling layer 3. Forming a dielectric layer film 2 and a film3 on the film 1, forming a lower electrode and a via filling layer 3 (film 4) in the dielectric layer via 1; forming a metal layer (film 5) on the film 4; a resistive layer (film 6), an upper electrode (film 7), a barrier layer (film 8) and a sidewall protection layer (film 9) are sequentially deposited on the metal layer. Wherein the material of the through hole filling layer is TaN or W; the metal layer is made of W, lr, ru or Pt; the material of the via filling layer and the material of the metal layer may be identical or different, and are not particularly limited herein.
That is, on the basis of changing the through hole filling layer 3 with the top level with the film3 of the dielectric layer into a through hole filling layer with a certain thickness arranged above the film3 of the dielectric layer, in order to further reduce the influence of other processes on the resistance change layer, thereby ensuring the electrical property of the resistance change memory; according to the application, a metal layer is deposited on the through hole filling layer, and a resistive layer and an upper electrode are sequentially deposited on the metal layer. The time between the whole generation processes is shorter, the time is easier to clamp and control, and the time for the surface of the metal layer 4 to react with components in the environment is reduced, so that the technical effect of improving the electrical property of the resistive random access memory is achieved.
In order to achieve the above object, this embodiment provides a method for manufacturing a resistive random access memory, including: depositing a via filling layer 3 for filling the lower electrode via 1 on the dielectric layer 2; grinding the through hole filling layer 3 until the thickness of the through hole filling layer 3 covered on the dielectric layer 2 reaches a set thickness threshold; depositing a metal layer 4 on the through hole filling layer 3, and sequentially depositing a resistive layer 5 and an upper electrode 6 on the metal layer 4; and etching the through hole filling layer 3, the metal layer 4, the resistance change layer 5 and the upper electrode 6 to form a resistance change structure of the resistance change memory.
As a modification of the present embodiment, as shown in fig. 5, the specific steps of etching the via filling layer 3, the resistive layer 5, and the upper electrode 6 to form the resistive structure of the resistive random access memory include: photoetching and etching the resistance change 5 and the upper electrode 6; depositing a growth side wall protection layer on the side surface of the resistance change layer 5, the surface and the side surface of the upper electrode 6 and the surface of the metal layer 4; and etching the through hole filling layer 3, the metal layer 4 and the side wall protection layer 7 to form the resistive random access memory resistive structure.
Specifically, the substrate is cleaned, and film 1, film 2, and film3 are grown in this order, wherein film 2 and film3 serve as dielectric layers; filling the lower electrode through hole 1 by lower electrode metal, forming a lower electrode, depositing to generate a through hole filling layer film4, and grinding (CMP) the film4 until the thickness value of the through hole filling structure reaches a preset thickness threshold value; a metal layer (film 5), a resistance change layer 5 (film 6), an upper electrode 6 (film 7) and a barrier layer (film 8) are sequentially deposited on the film 4; photoetching and etching the resistive layer 5 (film 6), the upper electrode 6 (film 7) and the barrier layer (film 8); depositing a growth sidewall protection layer 7 (film 9) on the sides of the resistive layer 5, the upper electrode 6 and the surface and sides of the barrier layer; the sidewall protection layer 7 (film 9), the metal layer (film 5) and the via filling layer (film 4) are etched to obtain a resistive random access memory resistive random access structure protruding above the dielectric layer 2 and the lower electrode.
Example 3
Further, as a modification of the present embodiment, in order to further improve the influence of the interface (interface) generated by the resistive layer 5 and the metal layer 4 on the electrical property of the resistive memory, the metal layer 4 is provided in two layers.
As shown in fig. 6, in order to further enhance the stability of the resistive random access memory, the present embodiment provides a resistive random access memory including a dielectric layer 2 having a lower electrode via 1 therein and a via filling layer 3 for filling the lower electrode via 1; the through hole filling layer 3 is an isolating dielectric film with set thickness covered on the dielectric layer 2; a first metal layer 41 is deposited on the via fill layer 3, and a second metal layer 42, a resistive layer 5, and an upper electrode 6 are sequentially deposited on the first metal layer 41. Forming a dielectric layer film 2 and a film3 on the film 1, forming a lower electrode and a via filling layer 3 (film 4) in the dielectric layer via 1; forming a first metal layer (film 5) on the film 4; a second metal layer (film 6), a resistive layer (film 7), an upper electrode (film 8) and a sidewall protection layer (film 9) are deposited in this order on the first metal layer.
The preparation method of the resistive random access memory comprises depositing a via filling layer for filling the lower electrode via on a dielectric layer; grinding the through hole filling layer until the thickness of the through hole filling layer covered on the dielectric layer reaches a set thickness threshold value; depositing a first metal layer on the via filling layer; and sequentially depositing a second metal layer, a resistance change layer and an upper electrode on the first metal layer.
Specifically, in this embodiment, in order to further improve the effect of the interface (interface) generated between the resistive layer and the metal layer on the electrical property of the resistive memory, the metal layer is provided as two layers; that is, a first metal layer is grown on the dielectric layer and the lower electrode; generating a second metal layer on the first metal layer; and generating a resistive layer and an upper electrode on the second metal layer. The second metal layer, the resistive layer and the upper electrode are grown on the same machine. In order to ensure the thickness uniformity (Thickness Uniformity) of the film body deposited and generated by the same machine, the thickness of the second metal layer should be thinner; while the thickness of the first metal layer is thicker. In a specific implementation, the metal layer may be formed by a deposition process. The first metal layer and the second metal layer may be deposited on the same machine or on different machines, which is not limited herein. Wherein the deposition process comprises one or more of physical vapor deposition (physical vapour deposition, PVD), chemical vapor deposition (chemical vapordeposition, CVD) or atomic layer deposition (atomic layer deposition, ALD). The thickness of the second metal layer is 20 nm-40 nm. It should be noted that, the material of the metal layer should be selected from metal materials with strong oxidation resistance and good heat conduction, and may be, but not limited to, W, pt, lr and Ru.
According to the application, the resistance change layer can be less affected by other processes by adding the plurality of metal layers, so that the influence of environmental factors is reduced as much as possible, and the electrical property of the RRAM Film and the process stability are improved.
The application improves the grinding process, and aims at the current mechanical chemical grinding which needs to grind the film3 and the film structure with different filling structures of the lower electrode through hole, so that the mechanical chemical grinding can not smooth the filling structures of the film3 and the lower electrode through hole during grinding, and the RRAM unit structure is arranged above the lower electrode through hole, thereby having great influence on the functions of the RRAM unit structure. Resulting in increased functional and structural differences between RRAM and RRAM on the same wafer. In addition, the same problems can also cause the problems that the process is influenced and the process window is reduced due to the (alignment Mark signal) and the OVL Mark Damage which are needed by photoetching, and the application does not need to grind the film structure of the film3 and the filling structure of the through hole of the lower electrode at the same time, so the problem can be improved. By changing the grinding stopping point of the through hole filling layer, a plurality of metal layers are added; thereby reducing the influence on the resistance change layer; thereby achieving the technical effect of reducing the function and the difference between the structures of the resistive switching structures on the same wafer.
The current-voltage characteristic curves of the resistive random access memories prepared according to the flow shown in fig. 1 and the resistive random access memories prepared in examples 1 and 2 (the current-voltage characteristic curves of each example are detected in a plurality of numbers, and the most representative curves are selected for comparison), and it is known that the current-voltage characteristics of the resistive random access memories prepared in examples 1 and 2 are better than those of the resistive random access memories prepared according to the flow shown in fig. 1.
Memory cells, memory devices, and electronic devices including the resistive memory device will be described.
The embodiment of the application also provides a memory cell, which comprises: and a gate, and a resistive memory device connected to the gate. The gate may be a three-terminal gate device, for example, a transistor, or a two-terminal gate device, for example, an ovonic threshold switch device. Taking a gate as a transistor as an example, a plug is formed between the transistor and the resistive random access memory device, and the transistor and the resistive random access memory device can be electrically connected through the plug.
Specifically, the transistor includes a source, a drain, and a gate, and the resistive memory device is connected between the drain and the bit line. In addition, the source of the transistor may be connected to a source line, and the gate may be connected to a word line.
The embodiment of the application also provides a memory device, which comprises a memory controller and the above resistance change memory device, wherein the memory controller is used for reading and writing data of the resistance change memory device. In particular, the memory controller may provide a write voltage or a read voltage to the resistive memory device, thereby writing data to the resistive memory device, or reading data in the resistive memory device. For example, the memory controller may control voltages of the word line, the bit line, and the source line to control an operating state of a gate (e.g., a transistor) in the memory cell, thereby providing a write voltage or a read voltage between the upper electrode and the lower electrode of the resistive memory device. The writing voltage and the reading voltage can cause the resistance of the resistance change memory device to change, so that the memory state is changed.
The embodiment of the application also provides electronic equipment. The electronic device may include a circuit board and a resistive memory device coupled to the circuit board. The circuit board and the resistance change memory device can be electrically connected, and the resistance change memory device and the circuit board are matched to realize a data storage function. In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the embodiments of the memory cell, the memory device, and the electronic device, since they are substantially similar to the structural embodiments of the resistive memory device, the description is relatively simple, and the relevant points will be referred to in the description of the structural embodiments.
The resistive memory device may be used in a memory chip or a memory integrated chip. The integrated memory and calculation chip refers to a chip integrating memory and calculation. For ease of understanding, embodiments of the present application are illustrated with a memory chip. The memory integrated chip comprises a control circuit, a decoding circuit, a read-write circuit and a memory array. The control circuit is used for providing control signals for the whole chip. The storage array is used for storing data, and further, the storage array in the integrated memory chip is also used for calculating data. The decoding circuit is used for selecting rows and columns of the memory array. The read-write circuit is used for performing read or write operation on the selected memory cell.
The memory array includes a plurality of memory cells. Each memory cell includes a transistor disposed over a substrate and a resistive memory device disposed over the transistor. The structure of the resistive memory device can be described with reference to the accompanying description. The transistor may be a MOS transistor, which may include a source (S), a drain (D), and a gate (G). The resistive memory device may be arranged in particular above the gate. The resistive memory device is electrically connected to the gate of the transistor. In some embodiments, the resistive memory device may also be electrically connected to the drain through a plug. The plugs may be metal materials such as tungsten plugs formed of tungsten metal.
Specifically, the control circuit provides control signals including address signals and command signals. The decoding circuit receives the address signal and the command signal, and decodes according to the address signal to select a memory cell corresponding to the address signal in the memory array. The read-write circuit performs read-write operation on the selected memory cell according to the command signal. For example, when the read-write circuit performs a write operation to a selected memory cell, the read-write circuit may output data stored in the selected memory cell.
Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the singular does not exclude a plurality. A plurality of units or means recited in the system claims can also be implemented by means of software or hardware by means of one unit or means. The terms second, etc. are used to denote a name, but not any particular order.
Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present application and not for limiting the same, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present application without departing from the spirit and scope of the technical solution of the present application.

Claims (14)

1. A method for manufacturing a resistive random access memory, the method comprising:
depositing a via filling layer for filling the lower electrode via on the dielectric layer;
grinding the through hole filling layer until the thickness of the through hole filling layer covered on the dielectric layer reaches a set thickness threshold value;
sequentially depositing a resistive layer and an upper electrode on the through hole filling layer;
and etching the through hole filling layer, the resistance change layer and the upper electrode to form the resistance change structure of the resistance change memory.
2. The method of manufacturing a resistive random access memory according to claim 1, further comprising, before the step of sequentially depositing the resistive layer and the upper electrode on the via filling layer,
and depositing a metal layer on the through hole filling layer, and sequentially depositing the resistive layer and the upper electrode on the metal layer.
3. The method of manufacturing a resistive random access memory according to claim 1, wherein the step of depositing a metal layer on the via fill layer, and sequentially depositing the resistive layer and the upper electrode on the metal layer, comprises,
depositing a first metal layer on the via filling layer;
and sequentially depositing a second metal layer, the resistance change layer and the upper electrode on the first metal layer.
4. The method of manufacturing a resistive random access memory according to claim 2, wherein a metal layer is deposited on the via fill layer, and wherein after the step of sequentially depositing the resistive layer and the upper electrode on the metal layer, further comprising,
photoetching and etching are carried out on the resistance change layer and the upper electrode; depositing a growth side wall protection layer on the side surface of the resistance change layer, the surface and the side surface of the upper electrode and the surface of the metal layer;
and etching the through hole filling layer, the metal layer and the side wall protection layer to form the resistive random access memory resistive random access structure.
5. The method for manufacturing a resistive random access memory according to claim 1, wherein,
the material of the through hole filling layer is TaN or W.
6. A method for manufacturing a resistive random access memory according to claim 3,
the metal layer is made of W, lr, ru or Pt.
7. A method for manufacturing a resistive random access memory according to claim 1 or 3,
the set thickness of the through hole filling layer is 10 nm-160 nm.
8. The method of manufacturing a resistive random access memory according to claim 7,
the set thickness of the through hole filling layer is 10 nm-90 nm.
9. A resistive random access memory is characterized in that,
the dielectric layer is internally provided with a lower electrode through hole, and the through hole filling layer is used for filling the lower electrode through hole; the through hole filling layer is an isolation dielectric film with a set thickness and covered on the dielectric layer;
and a resistive layer and an upper electrode are sequentially laminated on the through hole filling layer.
10. The resistive random access memory of claim 9 wherein,
and a metal layer is arranged between the resistance change layer and the through hole filling layer.
11. The resistive random access memory of claim 10 wherein,
the metal layer includes a first metal layer and a second metal layer.
12. A memory cell, characterized in that,
the memory cell comprising a gate and the resistive random access memory according to any one of claims 9-11 connected to the gate.
13. A memory device, characterized in that the memory device comprises a memory controller and a resistive random access memory according to any one of claims 9-11, the memory controller being configured to read and write data from and to the resistive random access memory.
14. An electronic device comprising a circuit board and a resistive random access memory according to any one of claims 9-11 connected to the circuit board.
CN202310450080.XA 2023-04-24 2023-04-24 Resistive random access memory and preparation method thereof Pending CN116634853A (en)

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