JP5159270B2 - 不揮発性半導体記憶装置及びその製造方法 - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
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- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
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- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
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- G—PHYSICS
- G11—INFORMATION STORAGE
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Description
[全体構成]
図1は、本発明の第1の実施の形態に係る不揮発性メモリのブロック図である。
図2は、メモリセルアレイ1の一部の斜視図、図3は、図2におけるメモリセル1つ分の拡大斜視図である。
[数1]
W1=W1′>W1″
W2,W2′>W2″
という関係になっている。
次に、図8に示した本実施形態に係る不揮発性メモリの製造方法について説明する。
図19は、本発明の第2の実施形態に係る不揮発性半導体記憶装置のメモリセル部分を示す斜視図である。この実施形態では、非オーミック素子NOと可変抵抗素子VRの配置が、図3の配置と上下逆になっている。このような構成においても、可変抵抗素子VR側の断面積が非オーミック素子NOの断面積よりも小さいことにより本発明の効果が得られる。この場合、オーバーエッチング気味のエッチング条件で逆テーパ状のメモリセルMCを形成すれば良い。
図20は、本発明の第3の実施形態に係る不揮発性半導体記憶装置のメモリセル部分を示す斜視図である。この実施形態では、非オーミック素子NOの断面積と可変抵抗素子VRの断面積をそれぞれ一定にし、前者を後者よりも大面積とした構成を備えている。このような構成であっても上述した本発明の効果が得られる。
また、図21に示すように、上述したメモリ構造を複数積層した三次元構造とすることもできる。図22は、図21のII−II′断面を示す断面図である。図示の例は、セルアレイ層MA0〜MA3からなる4層構造のメモリセルアレイで、ワード線WL0jがその上下のメモリセルMC0,MC1で共有され、ビット線BL1iがその上下のメモリセルMC1,MC2で共有され、ワード線WL1jがその上下のメモリセルMC2,MC3で共有されている。各メモリセルMCは、非オーミック素子NO側の断面積が可変抵抗素子VR側の断面積よりも大きくなるように、それぞれテーパ状に形成されている。また、このような配線/セル/配線/セルの繰り返しではなく、配線/セル/配線/層間絶縁膜/配線/セル/配線のように、セルアレイ層間に層間絶縁膜を介在させるようにしても良い。
Claims (5)
- 複数の第1の配線と、
これら複数の第1の配線と交差する複数の第2の配線と、
前記第1及び第2の配線の交差部で両配線間に接続され、抵抗値の変化で情報を記憶する可変抵抗素子を含むメモリセルと
を有し、
前記メモリセルは、
前記可変抵抗素子の断面積が他の部分の断面積よりも小さくなるように形成され、
前記可変抵抗素子と直列に接続される非オーミック素子を含み、
前記非オーミック素子は、その断面積が前記可変抵抗素子の断面積よりも大きくなるように形成され、
前記第1の配線側から前記第2の配線側へと連続的に断面積が小さくなるように形成され、
前記可変抵抗素子は、前記第2の配線側に配置されている
ことを特徴とする不揮発性半導体記憶装置。 - 前記メモリセルは、少なくとも一つの側面が略一定の角度のテーパを有する
ことを特徴とする請求項1記載の不揮発性半導体記憶装置。 - 前記メモリセルの前記第1の配線側接続端の前記第2の配線方向の幅は、このメモリセルの前記第2の配線側接続端の前記第2の配線方向の幅より広く、かつ、前記第1の配線の幅と等しく、
前記第2の配線の幅、及び前記メモリセルの前記第1の配線側接続端の前記第1の配線方向の幅は、このメモリセルの前記第2の配線側接続端の前記第1の配線方向の幅より長い
ことを特徴とする請求項1又は2記載の不揮発性半導体記憶装置。 - 半導体基板の上に、少なくとも層間絶縁膜、第1の配線を形成する層、非オーミック素子を形成する層及び可変抵抗素子を形成する層が順次積層された積層体を形成する工程と、
前記積層体に、開口側が底面側よりも幅広で、深さが前記第1の配線を形成する層の下面に達する、前記第1の配線が形成される方向に延びる複数の第1の溝を形成する工程と、
前記第1の溝に第1の絶縁膜を埋め込む工程と、
前記第1の絶縁膜が埋め込まれた積層体に、開口側が底面側よりも幅広で、深さが前記第1の配線を形成する層の上面に達する、前記第1の配線と交差する第2の配線が形成される方向に延びる複数の第2の溝を形成する工程と、
前記第2の溝に第2の絶縁膜を埋め込む工程と、
前記第2の絶縁膜が埋め込まれた積層体の上に前記第2の配線を形成する工程と
を備えたことを特徴とする不揮発性半導体記憶装置の製造方法。 - 前記第1の溝を形成する工程及び前記第2の溝を構成する工程は、
前記積層体の上面に、ナノインプリント技術を用いて下面が上面よりも幅広の側壁がテーパ状に形成されたレジストを形成する工程と、
前記レジストをマスクとして前記積層体をエッチングする工程と
を有することを特徴とする請求項4記載の不揮発性半導体記憶装置の製造方法。
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US12/275,794 US20090134431A1 (en) | 2007-11-22 | 2008-11-21 | Nonvolatile semiconductor storage apparatus and method of manufacturing the same |
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KR20230154529A (ko) * | 2022-05-02 | 2023-11-09 | 삼성전자주식회사 | 반도체 메모리 소자 |
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US6967350B2 (en) * | 2002-04-02 | 2005-11-22 | Hewlett-Packard Development Company, L.P. | Memory structures |
WO2004084228A1 (en) * | 2003-03-18 | 2004-09-30 | Kabushiki Kaisha Toshiba | Phase change memory device |
US7606059B2 (en) * | 2003-03-18 | 2009-10-20 | Kabushiki Kaisha Toshiba | Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array |
JP2005167064A (ja) * | 2003-12-04 | 2005-06-23 | Sharp Corp | 不揮発性半導体記憶装置 |
JP2005294376A (ja) * | 2004-03-31 | 2005-10-20 | Toshiba Corp | 磁気記録素子及び磁気メモリ |
CN1938781B (zh) * | 2004-04-16 | 2011-09-21 | 松下电器产业株式会社 | 具有可变电阻的薄膜存储器件 |
JP4466315B2 (ja) * | 2004-10-21 | 2010-05-26 | 株式会社日立製作所 | 相変化メモリ |
US7733684B2 (en) * | 2005-12-13 | 2010-06-08 | Kabushiki Kaisha Toshiba | Data read/write device |
KR100746224B1 (ko) * | 2006-01-02 | 2007-08-03 | 삼성전자주식회사 | 멀티비트 셀들을 구비하는 상변화 기억소자들 및 그프로그램 방법들 |
US20080048293A1 (en) * | 2006-08-22 | 2008-02-28 | Samsung Electronics Co., Ltd. | Semiconductor device having heating structure and method of forming the same |
CN101501850B (zh) * | 2006-10-16 | 2011-01-05 | 松下电器产业株式会社 | 非易失性存储元件及其制造方法 |
US9018615B2 (en) * | 2007-08-03 | 2015-04-28 | Macronix International Co., Ltd. | Resistor random access memory structure having a defined small area of electrical contact |
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US9373664B2 (en) | 2014-07-28 | 2016-06-21 | Samsung Electronics Co., Ltd. | Variable resistance memory devices and methods of manufacturing the same |
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