JP2011129737A - 半導体記憶装置の製造方法及び半導体記憶装置 - Google Patents
半導体記憶装置の製造方法及び半導体記憶装置 Download PDFInfo
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Abstract
【解決手段】半導体基板101上に第1の配線層及びメモリセル層104Aを形成した後、第1の方向に延びる第1の溝を形成して第1の配線103を形成し、第1の溝の側壁に薄膜161を形成し、第1の溝に層間絶縁膜105を埋め込み積層体を形成し、積層体の上に第2の配線層を形成し、第2の方向に延びる第2の溝186を形成して第2の配線106を形成し、第2の溝186の底部から露出した薄膜161を除去し、第2の溝186の底部から露出したメモリセル層104Aを第1の配線層の上部まで除去して柱状のメモリセルを形成する。薄膜161は、層間絶縁膜105よりもエッチング速度が速く且つ隣接するメモリセル層104Aの部分よりも先に除去される。
【選択図】図13
Description
[メモリセルアレイの構造]
図1は、本発明の第1の実施形態に係る半導体メモリのクロスポイント型セルアレイの一部を示す斜視図であり、図2(a)は、図1におけるI−I´線で切断して矢印方向に見たメモリセル1つ分の断面図、同図(b)は上記メモリセルの等価回路図である。
次に、図4A及び図4Bに示した2層構造のメモリセルアレイの製造方法について説明する。
[メモリセルアレイの構造]
図22は、第2の実施形態に係る半導体メモリのメモリセルアレイの一部を示す斜視図である。なお、第2の実施形態において、第1の実施形態のメモリセルアレイの符号101〜186と対応する部分には、符号201〜286を付し、対応する部分の重複説明は割愛する。
次に、図22に示した2層構造のメモリセルアレイの製造方法について説明する。
[メモリセルアレイの構造]
図28は、第3の実施形態に係る半導体メモリのメモリセルアレイの一部を示す斜視図である。なお、第3の実施形態において、第1の実施形態のメモリセルアレイの符号101〜191と対応する部分には、符号301〜391を付し、対応する部分の重複説明は割愛する。
次に、図28に示した2層構造のメモリセルアレイの製造方法について説明する。
第1〜第3の実施形態では、2層構造のメモリセルアレイの製造方法を説明したが、以上の積層構造の形成を繰り返すことにより、任意の積層数を持つクロスポイント型のメモリセルアレイの形成が可能である。逆に、単層のメモリセルアレイを製造する場合には、上層のメモリセル材料の形成を省略すれば良い。
Claims (5)
- 半導体基板上に第1の配線層を形成する工程と、
前記第1の配線層の上に第1のメモリセルを構成する第1のメモリセル層を形成する工程と、
前記第1のメモリセル層を形成する工程の後、深さが前記第1の配線層の底部に至る第1の方向に延びる第1の溝を形成して第1の配線を形成する工程と、
前記第1の溝の側壁に第1の薄膜を形成する工程と、
前記第1の薄膜が形成された第1の溝に第1の層間絶縁膜を埋め込み第1の積層体を形成する工程と、
前記第1の積層体の上に第2の配線層を形成する工程と、
深さが前記第2の配線層の底部に至る前記第1の方向と交差する第2の方向に延びる第2の溝を形成して第2の配線を形成する工程と、
前記第2の溝の底部から露出した前記第1の薄膜を除去する工程と、
前記第2の溝の底部から露出した前記第1のメモリセル層を前記第1の配線層の上部まで除去して柱状の前記第1のメモリセルを形成する工程と
を備え、
前記第1の薄膜は、前記第1の層間絶縁膜よりもエッチング速度が速く、かつ隣接する前記第1のメモリセル層の部分よりも先に除去が行われる
ことを特徴とする半導体記憶装置の製造方法。 - 前記第2の配線層を形成する工程の後、前記第2の配線を形成する工程の前、
前記第2の配線層の上に第2のメモリセルを構成する第2のメモリセル層を形成する工程と、
前記第1のメモリセルを形成する工程の後、
前記第2の溝の側壁に第2の薄膜を形成する工程と、
前記第2の薄膜が形成された第2の溝に第2の層間絶縁膜を埋め込み第2の積層体を形成する工程と、
前記第2の積層体の上に第3の配線層を形成する工程と、
深さが前記第3の配線層の底部に至る前記第1の方向に延びる第3の溝を形成して第3の配線を形成する工程と、
前記第3の溝の底部から露出した前記第2の薄膜を除去する工程と、
前記第3の溝の底部から露出した前記第2のメモリセル層を前記第2の配線層の上部まで除去して柱状の前記第2のメモリセルを形成する工程と
をさらに備え、
前記第2の薄膜は、前記第2の層間絶縁膜よりもエッチング速度が速く、かつ隣接する前記第2のメモリセル層の部分よりも先に除去が行われる
ことを特徴とする請求項1記載の半導体記憶装置の製造方法。 - 前記第1の薄膜を形成する工程は、
前記第1のメモリセル層の上面、前記第1の溝の側壁及び底部に前記第1の薄膜を形成する工程と、
前記第1の溝の側壁に形成された部分を除いて前記第1の薄膜を部分的に除去する工程と
を有する
ことを特徴とする請求項1又は2記載の半導体記憶装置の製造方法。 - 前記第1の薄膜を形成する工程は、前記第1のメモリセル層の上面、前記第1の溝の側壁及び底部に前記第1の薄膜を形成する工程を有し、
前記第1の積層体を形成する工程は、
前記第1の薄膜が形成された第1の溝に第1の層間絶縁膜を埋める工程と、
前記第1の薄膜の上面が露出するまで、前記第1の層間絶縁膜の上部を除去する工程と、
前記第1のメモリセル層が露出するまで、前記第1の薄膜の上部を除去する工程と
を有する
ことを特徴とする請求項1又は2記載の半導体記憶装置の製造方法。 - 第1の方向に延びる複数の第1の配線と、
前記第1の方向と交差する第2の方向に延びる複数の第2の配線と、
前記第1及び第2の配線の交差部で両配線間に接続された複数の柱状のメモリセルと、
隣接する前記メモリセル間に設けられた層間絶縁膜と
を備え、
前記メモリセルと前記層間絶縁膜との間は空隙である
ことを特徴とする半導体記憶装置。
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US12/838,960 US20110147942A1 (en) | 2009-12-18 | 2010-07-19 | Method of manufacturing semiconductor memory device and semiconductor memory device |
KR1020100088446A KR101164358B1 (ko) | 2009-12-18 | 2010-09-09 | 반도체 기억 장치의 제조 방법 및 반도체 기억 장치 |
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JP2013055103A (ja) * | 2011-09-01 | 2013-03-21 | Toshiba Corp | 分子メモリ装置の製造方法 |
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KR20110070756A (ko) | 2011-06-24 |
KR101164358B1 (ko) | 2012-07-09 |
US20110147942A1 (en) | 2011-06-23 |
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