JP2018525823A - 導電線を含む半導体デバイス、および、導電線を含む半導体デバイスの製造方法 - Google Patents
導電線を含む半導体デバイス、および、導電線を含む半導体デバイスの製造方法 Download PDFInfo
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- JP2018525823A JP2018525823A JP2018506100A JP2018506100A JP2018525823A JP 2018525823 A JP2018525823 A JP 2018525823A JP 2018506100 A JP2018506100 A JP 2018506100A JP 2018506100 A JP2018506100 A JP 2018506100A JP 2018525823 A JP2018525823 A JP 2018525823A
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Abstract
【選択図】図14
Description
本出願は、「導電線を含む半導体デバイス、および、導電線を含む半導体デバイスの製造方法」について2015年8月28日に出願された米国特許出願整理番号14/838,768号の出願日の利益を享受する権利を主張する。
本明細書で開示された実施例は、導電線(導電線の各々が、接点パッド用に、導電線の他の部分よりも実質的に大きな面積を占めている広がった部分を含んでいる)を有する半導体デバイス、ならびに、このような導電線および半導体デバイスを生成する方法に関連する。
個々に第1の部分、第2の部分、および、広がった部分を含む複数の第1の導電線(前記広がった部分は、前記第1の導電線の前記第1の部分と前記第2の部分に接続している)、
複数の第2の導電線(少なくとも前記第2の導電線のいくつかは一組の前記第1の導電線の間に配置されており、個々の第2の導電線は、前記第2の導電線の端部分に前記第2の導電線の他の部分よりも大きな断面積を含む)、ならびに、
前記複数の第1の導電線、および、前記複数の第2の導電線の各々の上のパッド
を含み、
前記複数の第2の導電線の各々の上のパッドは、前記第2の導電線の各々の前記端部分に位置し、
前記複数の第1の導電線の各々の上のパッドは、前記第1の導電線の各々の前記広がった部分に位置する。
(ここで、前記導電線を形成するステップは、
1つおきの導電線を、第1の部分、および、広がった部分によって前記第1の部分につながっている第2の部分を有するように形成するステップ、
少なくともいくつかの前記導電線について、個々の前記導電線の端部分にパッドを形成するステップ、ならびに、
少なくともいくつかの前記導電線の前記広がった部分に、パッドを形成するステップ
を含む)
フォトレジスト材料のラインを半導体デバイス上に形成するステップ(個々の前記フォトレジスト材料のラインは、個々の前記フォトレジスト材料のラインの他の部分に比べて広がった部分を含み)、
前記フォトレジスト材料のラインの側壁にスペーサーを形成するステップ、
前記フォトレジスト材料のラインを除去するステップ、
窒化物材料を前記スペーサーの上に形成するステップ、
前記スペーサーを囲む前記窒化物材料の輪を形成するために、前記窒化物材料の一部を除去するステップ、ならびに、
導電線のパターンを形成するために、前記窒化物材料の輪、および、前記スペーサーのパターンを、下層の導電性物質に転写するステップ(少なくともいくつかの導電線は、個々の前記導電線の他の部分よりも広がった部分を有する)
を含む。
Claims (20)
- メモリセルを含む半導体基板上の導電線を含む半導体デバイス。
(ここで、少なくともいくつかの前記導電線は、個々の導電線の両端部分の間に位置する広がった部分を含み、前記広がった部分は前記個々の導電線の他の部分よりも幅が広く、
少なくともいくつかの前記導電線は、その導電線の他の部分よりも大きな断面積を有する端部分を含む) - 前記導電線の前記広がった部分は前記導電線の複数の端部分の間にある
請求項1に記載の半導体デバイス。 - 前記導電線の他の部分よりも広い断面積を有する端部分を含む前記導電線の端部分にパッドをさらに含む
請求項1に記載の半導体デバイス。 - 前記端部分の前記パッドは、前記導電線のパッドの略半分を含む
請求項3に記載の半導体デバイス。 - 前記端部分にパッドを含む導電線は、前記広がった部分を含む導電線とは異なる
請求項3に記載の半導体デバイス。 - 略半分の前記導電線が前記広がった部分を有する
請求項1に記載の半導体デバイス。 - 隣り合った導電線を分離する少なくとも1つの隙間を、前記半導体デバイスの周辺領域にさらに含む
請求項1に記載の半導体デバイス。 - 前記広がった部分の各々に接点をさらに含む
請求項1に記載の半導体デバイス。 - 隣り合った導電線の間隔が約10nm〜約20nmである
請求項1に記載の半導体デバイス。 - 前記導電線の前記広がった部分にパッドをさらに含む
請求項1に記載の半導体デバイス。 - 前記広がった部分は、縦方向と横方向に互いにずれている
請求項1に記載の半導体デバイス。 - 前記広がった部分を含む前記導電線は、第1の部分、および、第2の部分を含み、
前記第1の部分と前記第2の部分は、前記広がった部分を介して互いにつながっている
請求項1に記載の半導体デバイス。 - 前記第1の部分と前記第2の部分は横方向に互いにずれている
請求項12に記載の半導体デバイス。 - 前記広がった領域の少なくともいくつかは、カーブした表面を有する
請求項1に記載の半導体デバイス。 - 半導体デバイス上に導電線を形成するステップを含む、半導体デバイスを形成する方法。
(ここで、前記導電線を形成するステップは、
1つおきの導電線を、第1の部分、および、広がった部分によって前記第1の部分につながっている第2の部分を有するように形成するステップ、
少なくともいくつかの前記導電線について、個々の前記導電線の端部分にパッドを形成するステップ、ならびに、
少なくともいくつかの前記導電線の前記広がった部分に、パッドを形成するステップを含む) - 少なくともいくつかの前記導電線の広がった部分を、前記導電線の他の部分よりも大きな断面積を有するように形成するステップ
をさらに含む、請求項15に記載の方法。 - 前記半導体基板の周辺領域の少なくともいくつかの前記導電線に接点パッドを形成するステップは、前記導電線の端部分に接点パッドを形成するステップを含む
請求項15に記載の方法。 - 少なくともいくつかの前記導電線の前記広がった部分に複数のパッドを形成するステップは、前記複数のパッドを縦方向に互いにずらして形成するステップを含む
請求項15に記載の方法。 - 少なくともいくつかの前記導電線について、個々の前記導電線の端部分にパッドを形成するステップは、前記半導体デバイスのアレイ領域に前記パッドを形成するステップを含む
請求項15に記載の方法。 - 前記半導体デバイス上に導電線を形成するステップは、
フォトレジスト材料のラインを半導体デバイス上に形成するステップであって、ここで、個々の前記フォトレジスト材料のラインは、個々の前記フォトレジスト材料のラインの他の部分に比べて広がった部分を含む、ステップ、
前記フォトレジスト材料のラインの側壁にスペーサーを形成するステップ、
前記フォトレジスト材料のラインを除去するステップ、
窒化物材料を前記スペーサーの上に形成するステップ、
前記スペーサーを囲む前記窒化物材料の輪を形成するために、前記窒化物材料の一部を除去するステップ、ならびに、
導電線のパターンを形成するために、前記窒化物材料の輪、および、前記スペーサーのパターンを、下層の導電性物質に転写するステップであって、少なくともいくつかの導電線は、前記広がった部分でつながっている第1の部分と第2の部分を含む、ステップ
を含む、請求項15に記載の方法。
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US20180114751A1 (en) | 2018-04-26 |
US20190103350A1 (en) | 2019-04-04 |
JP2019204965A (ja) | 2019-11-28 |
US10388601B2 (en) | 2019-08-20 |
CN107949907B (zh) | 2022-03-22 |
WO2017039887A1 (en) | 2017-03-09 |
KR102112941B1 (ko) | 2020-05-19 |
JP6845443B2 (ja) | 2021-03-17 |
EP3341962A1 (en) | 2018-07-04 |
EP3341962A4 (en) | 2019-04-17 |
CN107949907A (zh) | 2018-04-20 |
KR20180034696A (ko) | 2018-04-04 |
KR20200055803A (ko) | 2020-05-21 |
SG10201912557WA (en) | 2020-02-27 |
KR102166353B1 (ko) | 2020-10-16 |
JP6561198B2 (ja) | 2019-08-14 |
US9911693B2 (en) | 2018-03-06 |
US10811355B2 (en) | 2020-10-20 |
US20170062324A1 (en) | 2017-03-02 |
EP3341962B1 (en) | 2023-07-19 |
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