JP2017118133A - 3次元メモリアレイアーキテクチャ - Google Patents
3次元メモリアレイアーキテクチャ Download PDFInfo
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- 239000000463 material Substances 0.000 claims description 256
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- 239000011810 insulating material Substances 0.000 description 39
- 239000012782 phase change material Substances 0.000 description 25
- 238000000034 method Methods 0.000 description 18
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- 229910052787 antimony Inorganic materials 0.000 description 5
- 150000004770 chalcogenides Chemical class 0.000 description 5
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- 229910018110 Se—Te Inorganic materials 0.000 description 2
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- 229910052738 indium Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
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- 229910005939 Ge—Sn Inorganic materials 0.000 description 1
- 229910020938 Sn-Ni Inorganic materials 0.000 description 1
- 229910020923 Sn-O Inorganic materials 0.000 description 1
- 229910002855 Sn-Pd Inorganic materials 0.000 description 1
- 229910018731 Sn—Au Inorganic materials 0.000 description 1
- 229910008937 Sn—Ni Inorganic materials 0.000 description 1
- 229910008772 Sn—Se Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- 150000001342 alkaline earth metals Chemical class 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
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- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
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Abstract
【解決手段】3次元メモリアレイ568は、第1及び第2の方向に格子状に配置された複数のメモリセル構造体550と、第1の方向に波型に延在し、第1の列のメモリセル構造体のうち奇数番目のメモリセル構造体のそれぞれに電気的に接続し、偶数番目のメモリセル構造体のそれぞれ及び第1の列以外のメモリセル構造体とは電気的に接続しない第1のビット線BLk,Oと、第1の方向に波型に延在し、第1のビット線に隣接する、第1の列のメモリセル構造体のうち偶数番目のメモリセル構造体のそれぞれに電気的に接続し、奇数番目のメモリセル構造体のそれぞれ及び第1の列以外のメモリセル構造体とは電気的に接続しない第2のビット線BLk,Eと、を備える。
【選択図】図5D
Description
本開示は、弁護士整理番号1001.0680001を有し、「THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE」と題する、本願と共に出願する、米国特許出願第13/600、699号に関連し、その全体が参照により本明細書に組み込まれる。
102 導電線(ワード線)
104 導電線(ビット線)
106 メモリセル
208 3次元メモリアレイ
210、212 ワード線
214 ビット線
216、218 メモリセル
320 3次元メモリアレイ
322 ワード線
324 ビット線
326 導電延長部
328 メモリセル構造体
422 ワード線
424 ビット線
426 導電延長部
430 3次元メモリアレイ
438、440、441、442 メモリセル構造体
522 第1の導電線(ワード線)
524 第2の導電線(ビット線)
544 3次元メモリアレイ
547 導電線(奇数)
549 導電線(偶数)
550 メモリセル構造体
551 導電線
552 セル選択デバイス材料
554 記憶素子材料
556 導電延長部
558、560 メモリセル(活性領域)
562 自己整合バイア
566 3次元メモリアレイ
568 3次元メモリアレイ
570 3次元メモリアレイ
622 ワード線
624 頂部ビット線
650 メモリセル構造体
651 底部ビット線
722 ワード線
724 頂部ビット線
750 メモリセル構造体
751 底部ビット線
822 ワード線
824 ビット線
850 メモリセル構造体
852 セル選択デバイス材料
853 頂部停止材料
851 ビット線
854 記憶素子材料
855 底部停止材料
856 導電延長部
922 ワード線
924 ビット線
926 導電延長部
938、940、941、942 メモリセル
951 ビット線
1022 導電材料
1045 ヒータ材料
1048 絶縁材料
1052 セル選択デバイス材料
1054 記憶素子材料
1055 セル選択デバイス材料
1056 導電延長部材料
1062 エッチング停止材料
1081 3次元メモリアレイ
1082 エッチング停止材料
1085 導電材料
1091 絶縁材料
1092 絶縁材料
1093 メモリセル
Claims (8)
- 第1の方向と前記第1の方向に直行する第2の方向に格子状に配置された複数のメモリセル構造体であって、前記複数のメモリセル構造体のうち前記第1の方向に一列に配置された第1の列のメモリセル構造体を備える複数のメモリセル構造体と、
前記第1の方向に波型に延在する第1のビット線であって、前記第1の列のメモリセル構造体のうち奇数番目のメモリセル構造体のそれぞれに電気的に接続し、偶数番目のメモリセル構造体のそれぞれ及び前記第1の列以外に配置されたメモリセル構造体とは電気的に接続しないように形成された第1のビット線と、
前記第1の方向に波型に延在し前記第1のビット線に隣接する第2のビット線であって、前記第1の列のメモリセル構造体のうち前記偶数番目のメモリセル構造体のそれぞれに電気的に接続し、前記奇数番目のメモリセル構造体のそれぞれ及び前記第1の列以外に配置された前記メモリセル構造体とは電気的に接続しないように形成された第2のビット線と、
を備えるメモリアレイ。 - 前記複数のメモリセル構造体の間の複数の階層に前記第2の方向に延在する複数のワード線をさらに備える、請求項1に記載のメモリアレイ。
- 前記複数のメモリセル構造体のそれぞれは、
前記第1の方向及び前記第2の方向に直交する第3の方向に延在する導電延長部と、
前記導電延長部の周囲に形成される記憶素子材料と、
前記導電延長部の周囲に形成されるセル選択材料と、
を備える、請求項2に記載のメモリアレイ。 - 前記複数のメモリセル構造体のそれぞれは、前記複数のメモリセル構造体の前記導電延長部と前記複数のワード線が交差する部分のそれぞれにメモリセルを備える、請求項3に記載のメモリアレイ。
- 前記第1のビット線と前記第2のビット線は互いに同一面内に存在する、請求項1〜4のいずれか1項に記載のメモリアレイ。
- 前記複数のビット線は、前記複数の階層の上に延在する、請求項1〜5のいずれか1項に記載のメモリアレイ。
- 前記複数のビット線の前記第2の方向のピッチは前記複数のメモリセル構造体の前記第2の方向のピッチの半分である、請求項1〜6のいずれか1項に記載のメモリアレイ。
- 前記複数のワード線の各々に隣接しかつ通信可能に結合されるヒータ材料を更に備え、
前記ヒータ材料は前記複数のワード線のうちの少なくとも1本より小さな断面積を有し、
前記ヒータ材料は前記複数のワード線のうちのそれぞれの1本と前記記憶素子材料との間に直列に配置される、
請求項2〜7のいずれか1項に記載のメモリアレイ。
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US13/600,777 US8729523B2 (en) | 2012-08-31 | 2012-08-31 | Three dimensional memory array architecture |
US13/600,777 | 2012-08-31 |
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US9444046B2 (en) | 2016-09-13 |
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US8729523B2 (en) | 2014-05-20 |
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