JP2017224830A - 3次元メモリアレイアーキテクチャ - Google Patents
3次元メモリアレイアーキテクチャ Download PDFInfo
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- 230000015654 memory Effects 0.000 title claims abstract description 468
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- 229910052738 indium Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
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- 239000004065 semiconductor Substances 0.000 description 2
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- 229910005939 Ge—Sn Inorganic materials 0.000 description 1
- 229910020938 Sn-Ni Inorganic materials 0.000 description 1
- 229910020923 Sn-O Inorganic materials 0.000 description 1
- 229910002855 Sn-Pd Inorganic materials 0.000 description 1
- 229910018731 Sn—Au Inorganic materials 0.000 description 1
- 229910008937 Sn—Ni Inorganic materials 0.000 description 1
- 229910008772 Sn—Se Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 1
- 150000001342 alkaline earth metals Chemical class 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
本開示は、弁護士整理番号1001.0680001を有し、「THREE DIMENSIONAL MEMORY ARRAY ARCHITECTURE」と題する、本願と共に出願する、米国特許出願第13/600、699号に関連し、その全体が参照により本明細書に組み込まれる。
102 導電線(ワード線)
104 導電線(ビット線)
106 メモリセル
208 3次元メモリアレイ
210、212 ワード線
214 ビット線
216、218 メモリセル
320 3次元メモリアレイ
322 ワード線
324 ビット線
326 導電延長部
328 メモリセル構造体
422 ワード線
424 ビット線
426 導電延長部
430 3次元メモリアレイ
438、440、441、442 メモリセル構造体
522 第1の導電線(ワード線)
524 第2の導電線(ビット線)
544 3次元メモリアレイ
547 導電線(奇数)
549 導電線(偶数)
550 メモリセル構造体
551 導電線
552 セル選択デバイス材料
554 記憶素子材料
556 導電延長部
558、560 メモリセル(活性領域)
562 自己整合バイア
566 3次元メモリアレイ
568 3次元メモリアレイ
570 3次元メモリアレイ
622 ワード線
624 頂部ビット線
650 メモリセル構造体
651 底部ビット線
722 ワード線
724 頂部ビット線
750 メモリセル構造体
751 底部ビット線
822 ワード線
824 ビット線
850 メモリセル構造体
852 セル選択デバイス材料
853 頂部停止材料
851 ビット線
854 記憶素子材料
855 底部停止材料
856 導電延長部
922 ワード線
924 ビット線
926 導電延長部
938、940、941、942 メモリセル
951 ビット線
1022 導電材料
1045 ヒータ材料
1048 絶縁材料
1052 セル選択デバイス材料
1054 記憶素子材料
1055 セル選択デバイス材料
1056 導電延長部材料
1062 エッチング停止材料
1081 3次元メモリアレイ
1082 エッチング停止材料
1085 導電材料
1091 絶縁材料
1092 絶縁材料
1093 メモリセル
Claims (17)
- 互いに異なる複数の階層に積層された複数のデッキであって、それぞれが、互いに積層された第1の導電線材料と記憶素子材料とを有する、複数のデッキと、
複数の絶縁材料であって、それぞれが、前記複数のデッキの中の対応する隣接デッキ間に介在する、複数の絶縁材料と、
前記複数のデッキに対して実質的に垂直に延びるように配置された少なくとも一つの導電延長部であって、前記複数のデッキの各々における前記第1の導電線材料に、対応する前記記憶素子材料を介して、動作状態において結合されるように構成された少なくとも一つの導電延長部材料と、
を含む装置。 - 前記複数のデッキの各々における前記第1の導電線材料は導電線材料端で終端され、
前記複数のデッキの各々における前記記憶素子材料は、前記第1の導電線材料の前記導電線材料端に対して前記少なくとも一つの導電延長部材料に向かって突き出た突出部を有する、
請求項1に記載の装置。 - 前記複数のデッキの各々は、前記第1の導電線材料の前記導電線材料端を覆う誘電体材料をさらに有する、
請求項2に記載の装置。 - 前記複数のデッキの各々は、第2の導電線材料をさらに有し、前記第1の導電線材料、前記記憶素子材料および前記第2の導電線材料は、前記記憶素子材料が前記第1および第2の導電線材料の間に位置するように積層されており、
前記少なくとも一つの導電延長部材料は、前記複数のデッキの各々における前記第1および第2の導電線材料のそれぞれに、対応する前記記憶素子材料を介して、動作状態において結合されるように構成されている、
請求項1に記載の装置。 - 前記複数のデッキの各々における前記第1の導電線材料は第1の導電線材料端で終端され、
前記複数のデッキの各々における前記第2の導電線材料は第2の導電線材料端で終端され、
前記複数のデッキの各々における前記記憶素子材料は、前記第1の導電線材料の前記第1の導電線材料端および前記第2の導電線材料の前記第2の導電線材料端のそれぞれに対して前記少なくとも一つの導電延長部材料に向かって突き出た突出部を有する、
請求項4に記載の装置。 - 前記複数のデッキの各々は、前記第1の導電線材料の前記第1の導電線材料端を覆う第1の誘電体材料と、前記第2の導電線材料の前記第2の導電線材料端を覆う第2の誘電体材料とをさらに有する、
請求項5に記載の装置。 - 前記少なくとも一つの導電延長部材料と前記複数のデッキの各々における前記記憶素子材料との間に介在するセル選択材料をさらに含む、
請求項1乃至6のいずれか一項に記載の装置。 - 前記記憶素子材料は、相変化材料(PCM)を有する、
請求項1乃至7のいずれか一項に記載の装置。 - 前記相変化材料(PCM)は、カルコゲナイド材料を有する、
請求項8に記載の装置。 - 前記記憶素子材料は、相変化材料(PCM)を有し、前記セル選択材料は、オボニック閾値スイッチ(OTS)材料を有する、
請求項7に記載の装置。 - それぞれが、互いに積層された第1の導電線材料と記憶素子材料とを有する、複数のデッキを、互いに異なる複数の階層に、隣接するデッキ間に絶縁材料を介在させて、積層することと、
前記複数のデッキに対し実質的に垂直に延びて、前記複数のデッキの各々における前記第1の導電線材料および前記記憶素子材料のぞれぞれの端部を区画するように少なくとも一つのバイアを形成することと、
前記複数のデッキの各々における前記第1の導電線材料の前記端部を前記複数のデッキの各々における前記記憶素子材料の前記端部に対して凹ませる凹み処理を行うことと、
前記少なくとも一つのバイアに導電延長部材料を形成して、前記導電延長部材料が前記複数のデッキの各々における前記第1の導電線材料に、対応する前記記憶素子材料を介して、動作状態において結合されるように構成することと、
を含む方法。 - 前記凹み処理を行うことは、前記複数のデッキの各々における前記第1の導電線材料の前記端部を含む部分を除去し、当該除去した部分を誘電体材料で埋めること、を含む、
請求項11に記載の方法。 - 前記凹み処理を行うことは、前記複数のデッキの各々における前記第1の導電線材料の前記端部を含む部分を酸化して当該部分を酸化物に変換すること、を含む、
請求項11に記載の方法。 - 前記複数のデッキの各々は、第2の導電線材料をさらに有し、前記第1の導電線材料、前記記憶素子材料および前記第2の導電線材料は、前記記憶素子材料が前記第1および第2の導電線材料の間に位置するように積層されており、
前記少なくとも一つのバイアを形成することは、さらに、前記少なくとも一つのバイアに前記複数のデッキの各々における前記第2の導電線材料の端部を区画するようになし、
前記凹み処理を行うことは、さらに、前記複数のデッキの各々における前記第2の導電線材料の前記端部を前記複数のデッキの各々における前記記憶素子材料の前記端部に対して凹ませるようになし、
前記導電延長部材料を形成することは、さらに、前記導電延長部材料が前記複数のデッキの各々における前記第2の導電線材料に、対応する前記記憶素子材料を介して、動作状態において結合されるように構成するようになす、
請求項11に記載の方法。 - 前記凹み処理を行うことは、前記複数のデッキの各々における前記第1の導電線材料の前記端部を含む部分と前記複数のデッキの各々における前記第2の導電線材料の前記端部を含む部分とを除去し、当該除去した部分の各々を誘電体材料で埋めること、を含む、
請求項14に記載の方法。 - 前記凹み処理を行うことは、前記複数のデッキの各々における前記第1の導電線材料の前記端部を含む部分と前記複数のデッキの各々における前記第2の導電線材料の前記端部を含む部分とを酸化して当該それぞれの部分を酸化物に変換すること、を含む、
請求項14に記載の方法。 - 前記導電延長部材料を形成する前に、前記少なくとも一つのバイアにセル選択材料を形成することをさらに含むことにより、前記導電延長部材料と前記複数のデッキの各々における前記記憶素子材料との間に前記セル選択材料を介在させるようにする、
請求項11乃至16のいずれか一項に記載の方法。
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KR102601974B1 (ko) * | 2019-05-03 | 2023-11-14 | 마이크론 테크놀로지, 인크 | 3차원 메모리 디바이스의 아키텍처 및 이와 관련된 방법 |
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JP6127144B2 (ja) | 2017-05-10 |
EP2891184A4 (en) | 2016-04-27 |
CN104718625B (zh) | 2018-04-20 |
TW201415477A (zh) | 2014-04-16 |
KR20150046149A (ko) | 2015-04-29 |
WO2014036461A1 (en) | 2014-03-06 |
EP2891184B1 (en) | 2019-05-15 |
US9444046B2 (en) | 2016-09-13 |
US8729523B2 (en) | 2014-05-20 |
JP6280256B2 (ja) | 2018-02-14 |
KR20170102391A (ko) | 2017-09-08 |
TWI508091B (zh) | 2015-11-11 |
JP6568155B2 (ja) | 2019-08-28 |
EP3561877B1 (en) | 2021-12-08 |
KR101775248B1 (ko) | 2017-09-05 |
JP2015534720A (ja) | 2015-12-03 |
US20140061575A1 (en) | 2014-03-06 |
JP2017118133A (ja) | 2017-06-29 |
EP3561877A2 (en) | 2019-10-30 |
KR101824856B1 (ko) | 2018-02-02 |
US20140295638A1 (en) | 2014-10-02 |
EP2891184A1 (en) | 2015-07-08 |
CN104718625A (zh) | 2015-06-17 |
EP3561877A3 (en) | 2020-02-19 |
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