JP2007067403A - 相変化メモリセルにおける相変化層の成形方法 - Google Patents
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- 239000012782 phase change material Substances 0.000 claims abstract description 4
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/068—Patterning of the switching material by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
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- H—ELECTRICITY
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
Abstract
本発明は、相変化メモリセルにおける相変化層の成形方法を提供する。
【解決手段】
相変化メモリセルは、相変化材料から成る相変化層を半導体ボディ上に含む。ハードマスク構造が相変化層上に形成され、レジストマスクがハードマスク構造上に形成される。レジストマスクを用いてハードマスク構造を成形することによってハードマスクが形成される。ハードマスクを用いて相変化層が成形される。相変化層を成形する前にレジストマスクが除去される。
【選択図】図15
Description
2・・・選択トランジスタ
7、110・・・半導体基板
8、20、54、58、114、125・・・誘電体層
21、120・・・開口
22、123・・・ヒーター
23・・・誘電体
28・・・スリット
28’ ・・・微小トレンチ
30、121・・・スペーサ
35、127、129・・・カルコゲン層(相変化層)
40、150・・・相変化記憶素子
45・・・蓋構造
47、132・・・ハードマスク構造
48、133・・・レジストマスク
50、134・・・ハードマスク
51・・・抵抗性ビット線
52、136・・・封止層
53、142・・・ビット線
56・・・金属ビット線
59、113…ワード線
60・・・相変化メモリセル
65・・・相変化メモリ装置
126・・・OMS/OTS積層体
128、130・・・バリア層
135・・・ドット
500・・・システム
510・・・制御器
530・・・メモリ
Claims (26)
- 半導体ボディ上に相変化材料から成る相変化層を形成する工程;
前記相変化層上にハードマスク構造を作り出す工程;
前記ハードマスク構造上にレジストマスクを作り出す工程;
前記レジストマスクを用いて前記ハードマスク構造を成形することによってハードマスクを形成する工程;
前記レジストマスクを除去する工程;及び
前記レジストマスクを除去する工程後に、前記ハードマスクを用いて前記相変化層を成形する工程;
を有する方法。 - 前記ハードマスク構造を作り出す工程が、誘電体を含むハードマスク構造を形成することを含む、ところの請求項1に記載の方法。
- 前記相変化層を成形する工程が前記ハードマスクを少なくとも部分的に除去するところの請求項1に記載の方法。
- 前記相変化層上に蓋構造を形成する工程を有し、前記ハードマスク構造が該蓋構造に接して形成されるところの請求項1に記載の方法。
- 前記レジストマスクを除去する工程がフォトレジスト剥離工程を有するところの請求項1に記載の方法。
- 前記半導体ボディ上の誘電体構造層及び該誘電体構造層内のヒーター素子を形成する工程をさらに有する請求項1に記載の方法。
- 前記相変化層を形成する工程が、前記ヒーター素子と直接的に接触させて該相変化層を堆積することを有し、それにより該ヒーター素子と該相変化層との接触領域に記憶素子を形作る、ところの請求項6に記載の方法。
- 前記記憶素子を形作ることが、少なくとも1つのサブリソグラフィ長を有する前記接触領域に該素子を形作ることを含む、ところの請求項7に記載の方法。
- カルコゲナイド層;
前記カルコゲナイド層を覆うバリア層;及び
前記バリア層上のマスク層;
を有する半導体構造。 - 前記バリア層が金属を含むところの請求項9に記載の構造。
- 前記金属がチタンを含むところの請求項10に記載の構造。
- 前記金属がTi/TiNを含むところの請求項11に記載の構造。
- 前記バリア層の厚さが約45nmであるところの請求項12に記載の構造。
- 前記バリア層が前記カルコゲナイド層を完全に覆っているところの請求項9に記載の構造。
- 前記バリア層上にレジストマスクを含む請求項9に記載の構造。
- 前記バリア層上にハードマスクを含む請求項9に記載の構造。
- 前記ハードマスク上にレジストマスクを含む請求項16に記載の構造。
- 分離された2つのカルコゲナイド層を含む請求項9に記載の構造。
- 半導体ボディ上に相変化材料から成る相変化層を形成する工程;
前記相変化層上にハードマスク構造を作り出す工程;
前記ハードマスク構造上にレジストマスクを作り出す工程;
前記レジストマスクを用いて前記ハードマスク構造を成形することによってハードマスクを形成する工程;
前記レジストマスクを除去する工程;及び
前記レジストマスクを除去する工程後に、前記ハードマスクを用いて前記相変化層を成形する工程;
を有するプロセスによって形成された製造物。 - 前記相変化層を成形する工程が前記ハードマスクを少なくとも部分的に除去するところのプロセスによって形成された請求項19に記載の製造物。
- 前記相変化層上に蓋構造を形成する工程を有し、前記ハードマスク構造が該蓋構造に接して形成されるところのプロセスによって形成された請求項19に記載の製造物。
- 前記レジストマスクを除去する工程がフォトレジスト剥離工程を有するところのプロセスによって形成された請求項19に記載の製造物。
- 前記半導体ボディ上の誘電体構造層及び該誘電体構造層内のヒーター素子を形成する工程をさらに有するプロセスによって形成された請求項19に記載の製造物。
- 前記相変化層を形成する工程が、前記ヒーター素子と直接的に接触させて該相変化層を堆積することを有し、それにより該ヒーター素子と該相変化層との接触領域に記憶素子を形作る、ところのプロセスによって形成された請求項23に記載の製造物。
- 前記記憶素子を形作ることが、少なくとも1つのサブリソグラフィ長を有する前記接触領域に該素子を形作ることを含む、ところのプロセスによって形成された請求項24に記載の製造物。
- プロセッサ、及び前記相変化層を含む相変化メモリを有する請求項19に記載の製造物。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/215,403 US20070045606A1 (en) | 2005-08-30 | 2005-08-30 | Shaping a phase change layer in a phase change memory cell |
US11/215,403 | 2005-08-30 |
Publications (2)
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JP2007067403A true JP2007067403A (ja) | 2007-03-15 |
JP5020570B2 JP5020570B2 (ja) | 2012-09-05 |
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Country Status (5)
Country | Link |
---|---|
US (2) | US20070045606A1 (ja) |
JP (1) | JP5020570B2 (ja) |
KR (1) | KR100808365B1 (ja) |
CN (1) | CN100505363C (ja) |
TW (1) | TWI319635B (ja) |
Cited By (9)
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JP2008300820A (ja) * | 2007-05-31 | 2008-12-11 | Ind Technol Res Inst | 相変化メモリ装置とその製造方法 |
JP2011517083A (ja) * | 2008-04-01 | 2011-05-26 | エヌエックスピー ビー ヴィ | バーチカル型相変化メモリセル |
US8110822B2 (en) * | 2009-07-15 | 2012-02-07 | Macronix International Co., Ltd. | Thermal protect PCRAM structure and methods for making |
JP2012084706A (ja) * | 2010-10-13 | 2012-04-26 | Sony Corp | 不揮発性メモリ素子及び不揮発性メモリ素子群、並びに、これらの製造方法 |
US8384060B2 (en) | 2008-03-11 | 2013-02-26 | Samsung Electronics Co., Ltd. | Resistive memory device |
JP2015065459A (ja) * | 2014-11-17 | 2015-04-09 | スパンション エルエルシー | 不揮発性メモリ用可変抵抗およびその製造方法並びに不揮発性メモリ |
JP2015534720A (ja) * | 2012-08-31 | 2015-12-03 | マイクロン テクノロジー, インク. | 3次元メモリアレイアーキテクチャ |
US9595667B2 (en) | 2012-08-31 | 2017-03-14 | Micron Technology, Inc. | Three dimensional memory array architecture |
US10461125B2 (en) | 2017-08-29 | 2019-10-29 | Micron Technology, Inc. | Three dimensional memory arrays |
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US7135696B2 (en) * | 2004-09-24 | 2006-11-14 | Intel Corporation | Phase change memory with damascene memory element |
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US8237140B2 (en) | 2005-06-17 | 2012-08-07 | Macronix International Co., Ltd. | Self-aligned, embedded phase change RAM |
US7696503B2 (en) | 2005-06-17 | 2010-04-13 | Macronix International Co., Ltd. | Multi-level memory cell having phase change element and asymmetrical thermal boundary |
US7494849B2 (en) * | 2005-11-03 | 2009-02-24 | Cswitch Inc. | Methods for fabricating multi-terminal phase change devices |
US7394088B2 (en) | 2005-11-15 | 2008-07-01 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method (combined) |
US7414258B2 (en) * | 2005-11-16 | 2008-08-19 | Macronix International Co., Ltd. | Spacer electrode small pin phase change memory RAM and manufacturing method |
US7449710B2 (en) | 2005-11-21 | 2008-11-11 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US7829876B2 (en) | 2005-11-21 | 2010-11-09 | Macronix International Co., Ltd. | Vacuum cell thermal isolation for a phase change memory device |
US7642539B2 (en) | 2005-12-13 | 2010-01-05 | Macronix International Co., Ltd. | Thin film fuse phase change cell with thermal isolation pad and manufacturing method |
US8062833B2 (en) * | 2005-12-30 | 2011-11-22 | Macronix International Co., Ltd. | Chalcogenide layer etching method |
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US20120298946A1 (en) | 2012-11-29 |
US20070045606A1 (en) | 2007-03-01 |
TW200709480A (en) | 2007-03-01 |
CN1925186A (zh) | 2007-03-07 |
JP5020570B2 (ja) | 2012-09-05 |
KR20070026157A (ko) | 2007-03-08 |
KR100808365B1 (ko) | 2008-02-27 |
TWI319635B (en) | 2010-01-11 |
CN100505363C (zh) | 2009-06-24 |
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