JP2011135065A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2011135065A JP2011135065A JP2010262859A JP2010262859A JP2011135065A JP 2011135065 A JP2011135065 A JP 2011135065A JP 2010262859 A JP2010262859 A JP 2010262859A JP 2010262859 A JP2010262859 A JP 2010262859A JP 2011135065 A JP2011135065 A JP 2011135065A
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- electrode
- transistor
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- oxide semiconductor
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- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
- OYQCBJZGELKKPM-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O-2].[Zn+2].[O-2].[In+3] OYQCBJZGELKKPM-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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Abstract
【解決手段】第1の配線と、第2の配線と、第3の配線と、第4の配線と、第1のゲート電極、第1のソース電極、および第1のドレイン電極を有する第1のトランジスタと、第2のゲート電極、第2のソース電極、および第2のドレイン電極を有する第2のトランジスタと、を有し、第1のトランジスタは、半導体材料を含む基板に設けられ、第2のトランジスタは酸化物半導体層を含んで構成された半導体装置である。
【選択図】図1
Description
本実施の形態では、開示する発明の一態様に係る半導体装置の構成および作製方法について、図1乃至図13、図22及び図23を参照して説明する。
図1(A)に示す半導体装置では、トランジスタ160のゲート電極と、トランジスタ162のソース電極またはドレイン電極の一方とは、電気的に接続されている。また、第1の配線(1st Line:ソース線とも呼ぶ)とトランジスタ160のソース電極とは、電気的に接続され、第2の配線(2nd Line:ビット線とも呼ぶ)とトランジスタ160のドレイン電極とは、電気的に接続されている。そして、第3の配線(3rd Line:第1信号線とも呼ぶ)とトランジスタ162のソース電極またはドレイン電極の他方とは、電気的に接続され、第4の配線(4th Line:第2信号線とも呼ぶ)と、トランジスタ162のゲート電極とは、電気的に接続されている。
図2は、図1(A)に示す半導体装置の構成の一例である。図2(A)には、半導体装置の断面を、図2(B)には、半導体装置の平面を、それぞれ示す。ここで、図2(A)は、図2(B)の線A1−A2および線B1−B2における断面に相当する。図2(A)および図2(B)に示される半導体装置は、下部に酸化物半導体以外の材料を用いたトランジスタ160を有し、上部に酸化物半導体を用いたトランジスタ162を有するものである。なお、トランジスタ160およびトランジスタ162は、いずれもn型トランジスタとして説明するが、p型トランジスタを採用しても良い。特に、トランジスタ160は、p型とすることが容易である。また、図1(B)乃至図1(D)に示す半導体装置についても、同様の構成を採用することができる。
次に、上記半導体装置の作製方法の一例について説明する。以下では、はじめに下部のトランジスタ160の作製方法について図3を参照して説明し、その後、上部のトランジスタ162の作製方法について図4および図5を参照して説明する。
まず、半導体材料を含む基板100を用意する(図3(A)参照)。半導体材料を含む基板100としては、シリコンや炭化シリコンなどの単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウムなどの化合物半導体基板、SOI基板などを適用することができる。ここでは、半導体材料を含む基板100として、単結晶シリコン基板を用いる場合の一例について示すものとする。なお、一般に「SOI基板」は、絶縁表面上にシリコン半導体層が設けられた構成の基板をいうが、本明細書等においては、絶縁表面上にシリコン以外の材料からなる半導体層が設けられた構成の基板をも含む概念として用いる。つまり、「SOI基板」が有する半導体層は、シリコン半導体層に限定されない。また、SOI基板には、ガラス基板などの絶縁基板上に絶縁層を介して半導体層が設けられた構成のものが含まれるものとする。
次に、図4および図5を用いて、層間絶縁層128上にトランジスタ162を作製する工程について説明する。なお、図4および図5は、層間絶縁層128上の各種電極や、トランジスタ162などの作製工程を示すものであるから、トランジスタ162の下部に存在するトランジスタ160等については省略している。
酸化物半導体において、物性研究は多くなされているが、これらの研究は、エネルギーギャップ中の局在準位そのものを十分に減らすという思想を含まない。開示する発明の一態様では、局在準位の原因たり得る水や水素を酸化物半導体中より除去することで、高純度化し、真性化(I型化)した酸化物半導体を作製する。これは、エネルギーギャップ中の局在準位そのものを十分に減らすという思想に立脚するものである。そして、これによって極めて優れた工業製品の製造を可能とするものである。
酸化物半導体との比較対象たり得る半導体材料としては、炭化珪素(例えば、4H−SiC)などがある。酸化物半導体と4H−SiCはいくつかの共通点を有している。キャリア密度はその一例である。常温での酸化物半導体の真性キャリア密度は10−7/cm3程度と見積もられるが、これは、4H−SiCにおける6.7×10−11/cm3と同様、極めて低い値である。シリコンの真性キャリア密度(1.4×1010/cm3程度)と比較すれば、その程度が並はずれていることが良く理解できる。
ここで、酸化物半導体を用いたトランジスタの電導機構につき、図6乃至図9を用いて説明する。なお、以下の説明では、理解の容易のため理想的な状況を仮定しており、そのすべてが現実の様子を反映しているとは限らない。また、以下の説明はあくまでも一考察に過ぎず、発明の有効性に影響を与えるものではないことを付記する。
開示する発明に係る技術思想の一は、酸化物半導体層におけるキャリア濃度を十分に小さくし、できる限り真性(i型)に近づけようとするものである。以下、キャリア濃度の求め方、および、酸化物半導体層において測定したキャリア濃度に関し、図22および図23を参照して説明する。
図10乃至図13には、半導体装置の構成の変形例を示す。なお、以下では、変形例として、トランジスタ162の構成が上記とは異なるものについて説明する。つまり、トランジスタ160の構成は上記と同様である。
本実施の形態では、本発明の一態様に係る半導体装置の回路構成および動作について説明する。
本実施の形態では、先の実施の形態で得られる半導体装置を搭載した電子機器の例について図24を用いて説明する。先の実施の形態で得られる半導体装置は、電力の供給がない場合でも、情報を保持することが可能である。また、書き込み、消去に伴う劣化が生じない。さらに、その動作も高速である。このため、当該半導体装置を用いて新たな構成の電子機器を提供することが可能である。なお、先の実施の形態に係る半導体装置は、集積化されて回路基板などに実装され、各電子機器の内部に搭載されることになる。
102 保護層
104 半導体領域
106 素子分離絶縁層
108 ゲート絶縁層
110 ゲート電極
112 絶縁層
114 不純物領域
116 チャネル形成領域
118 サイドウォール絶縁層
120 高濃度不純物領域
122 金属層
124 金属化合物領域
126 層間絶縁層
128 層間絶縁層
130a ソース電極またはドレイン電極
130b ソース電極またはドレイン電極
130c 電極
132 絶縁層
134 導電層
136a 電極
136b 電極
136c 電極
136d ゲート電極
138 ゲート絶縁層
140 酸化物半導体層
142a ソース電極またはドレイン電極
142b ソース電極またはドレイン電極
144 保護絶縁層
146 層間絶縁層
148 導電層
150a 電極
150b 電極
150c 電極
150d 電極
150e 電極
152 絶縁層
154a 電極
154b 電極
154c 電極
154d 電極
160 トランジスタ
162 トランジスタ
164 容量素子
166 トランジスタ
200 メモリセル
201 トランジスタ
202 トランジスタ
203 容量素子
210 メモリセルアレイ
211 書き込み回路
212 読み出し回路
213 駆動回路
214 列デコーダ
215 アドレスバッファ
216 制御回路
217 電位生成回路
218 データバッファ
219 マルチプレクサ
220 メモリセル
255 トランジスタ
301 本体
302 筐体
303 表示部
304 キーボード
311 本体
312 スタイラス
313 表示部
314 操作ボタン
315 外部インターフェイス
320 電子書籍
321 筐体
323 筐体
325 表示部
327 表示部
331 電源
333 操作キー
335 スピーカー
337 軸部
340 筐体
341 筐体
342 表示パネル
343 スピーカー
344 マイクロフォン
345 操作キー
346 ポインティングデバイス
347 カメラ用レンズ
348 外部接続端子
349 太陽電池セル
350 外部メモリスロット
361 本体
363 接眼部
364 操作スイッチ
365 表示部(B)
366 バッテリー
367 表示部(A)
370 テレビジョン装置
371 筐体
373 表示部
375 スタンド
377 表示部
379 操作キー
380 リモコン操作機
Claims (11)
- ソース線と、
ビット線と、
第1信号線と、
複数の第2信号線と、
複数のワード線と、
前記ソース線と前記ビット線との間に、直列に接続された複数のメモリセルと、
入力されたアドレス信号によって指定されたメモリセルを選択するように、前記複数の第2信号線および前記複数のワード線を駆動する、第2信号線およびワード線の駆動回路と、
書き込み電位を前記第1信号線に出力する、書き込み回路と、
前記指定されたメモリセルに接続された前記ビット線から入力されるビット線の電位と、複数の読み出し電位とを比較する読み出し回路と、
前記ビット線の電位と前記複数の読み出し電位の比較結果に基づいて複数の補正電圧のいずれかを選択する制御回路と、
前記書き込み電位及び前記複数の読み出し電位を生成して、前記書き込み回路および前記読み出し回路に供給する、電位生成回路と、
を有し、
前記複数のメモリセルの一は、
第1のゲート電極、第1のソース電極、および第1のドレイン電極を有する第1のトランジスタと、
第2のゲート電極、第2のソース電極、および第2のドレイン電極を有する第2のトランジスタと、
容量素子と、
を有し、
前記第1のトランジスタは、半導体材料を含む基板に設けられ、
前記第2のトランジスタは酸化物半導体層を含んで構成され、
前記第1のゲート電極と、前記第2のソース電極または前記第2のドレイン電極の一方と、前記容量素子の電極の一方とは、電気的に接続され、
前記ソース線と、前記第1のソース電極とは、電気的に接続され、
前記ビット線と、前記第1のドレイン電極とは、電気的に接続され、
前記第1信号線と、前記第2のソース電極または前記第2のドレイン電極の他方とは、電気的に接続され、
前記複数の第2信号線の一と、前記第2のゲート電極とは、電気的に接続され、
前記複数のワード線の一と、前記容量素子の電極の他方とは電気的に接続された半導体装置。 - ソース線と、
ビット線と、
第1信号線と、
複数の第2信号線と、
複数のワード線と、
前記ソース線と前記ビット線との間に、直列に接続された複数のメモリセルと、
入力されたアドレス信号によって指定されたメモリセルを選択するように、前記複数の第2信号線および前記複数のワード線を駆動する、第2信号線およびワード線の駆動回路と、
第1の書き込み動作において、第1の書き込み電位を前記第1信号線に出力し、第2の書き込み動作において、複数の第2の書き込み電位のいずれかを前記第1信号線に出力する書き込み回路と、
第1の読み出し動作において、前記指定されたメモリセルに接続された前記ビット線から入力される第1のビット線の電位と、複数の第1の読み出し電位とを比較し、第2の読み出し動作において、前記指定されたメモリセルに接続された前記ビット線から入力される第2のビット線の電位と、複数の第2の読み出し電位とを比較して該メモリセルのデータを読み出す、読み出し回路と、
前記第1のビット線の電位と、前記複数の第1の読み出し電位の比較結果に基づいて複数の補正電圧のいずれかを選択し、前記複数の第2の書き込み電位のいずれかを選択する制御回路と、
前記第1の書き込み電位、前記複数の第2の書き込み電位、前記複数の第1の読み出し電位、及び前記複数の第2の読み出し電位を生成して、前記書き込み回路および前記読み出し回路に供給する電位生成回路と、
を有し、
前記複数のメモリセルの一は、
第1のゲート電極、第1のソース電極、および第1のドレイン電極を有する第1のトランジスタと、
第2のゲート電極、第2のソース電極、および第2のドレイン電極を有する第2のトランジスタと、
容量素子と、
を有し、
前記第1のトランジスタは、半導体材料を含む基板に設けられ、
前記第2のトランジスタは酸化物半導体層を含んで構成され、
前記第1のゲート電極と、前記第2のソース電極または前記第2のドレイン電極の一方と、前記容量素子の電極の一方とは、電気的に接続され、
前記ソース線と、前記第1のソース電極とは、電気的に接続され、
前記ビット線と、前記第1のドレイン電極とは、電気的に接続され、
前記第1信号線と、前記第2のソース電極または前記第2のドレイン電極の他方とは、電気的に接続され、
前記複数の第2信号線の一と、前記第2のゲート電極とは、電気的に接続され、
前記複数のワード線の一と、前記容量素子の電極の他方とは電気的に接続された半導体装置。 - 前記半導体装置は、
第1の選択線と、
第2の選択線と、
前記第1の選択線と、ゲート電極において電気的に接続された第3のトランジスタと、
前記第2の選択線と、ゲート電極において電気的に接続された第4のトランジスタと、を有し、
前記ビット線は、前記第3のトランジスタを介して、前記第1のドレイン電極と、電気的に接続され、
前記ソース線は、前記第4のトランジスタを介して、前記第1のソース電極と、電気的に接続された請求項1または請求項2に記載の半導体装置。 - 前記第1のトランジスタは、
半導体材料を含む基板に設けられたチャネル形成領域と、前記チャネル形成領域を挟むように設けられた不純物領域と、前記チャネル形成領域上の第1のゲート絶縁層と、前記第1のゲート絶縁層上の第1のゲート電極と、前記不純物領域と電気的に接続する第1のソース電極および第1のドレイン電極と、を有する請求項1乃至請求項3のいずれか一に記載の半導体装置。 - 前記第2のトランジスタは、
前記半導体材料を含む基板上の第2のゲート電極と、前記第2のゲート電極上の第2のゲート絶縁層と、前記第2のゲート絶縁層上の酸化物半導体層と、前記酸化物半導体層と電気的に接続する第2のソース電極および第2のドレイン電極と、を有する請求項1乃至請求項4のいずれか一に記載の半導体装置。 - 前記半導体材料を含む基板は、単結晶半導体基板またはSOI基板である、請求項1乃至請求項5のいずれか一に記載の半導体装置。
- 前記半導体材料はシリコンである、請求項1乃至請求項6のいずれか一に記載の半導体装置。
- 前記酸化物半導体層は、In−Ga−Zn−O系の酸化物半導体材料を含んでなる、請求項1乃至請求項7のいずれか一に記載の半導体装置。
- 前記酸化物半導体層は、In2Ga2ZnO7の結晶を含んでなる、請求項1乃至請求項8のいずれか一に記載の半導体装置。
- 前記酸化物半導体層の水素濃度は5×1019atoms/cm3以下である、請求項1乃至請求項9のいずれか一に記載の半導体装置。
- 前記第2のトランジスタのオフ電流は1×10−13A以下である、請求項1乃至請求項10のいずれか一に記載の半導体装置。
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Also Published As
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TW201137872A (en) | 2011-11-01 |
KR101803254B1 (ko) | 2017-11-30 |
KR101911382B1 (ko) | 2018-10-24 |
JP7213318B2 (ja) | 2023-01-26 |
TW201812762A (zh) | 2018-04-01 |
JP6030714B2 (ja) | 2016-11-24 |
WO2011065258A1 (en) | 2011-06-03 |
TW201619960A (zh) | 2016-06-01 |
JP2012238870A (ja) | 2012-12-06 |
JP2017028320A (ja) | 2017-02-02 |
US8559220B2 (en) | 2013-10-15 |
KR20170132358A (ko) | 2017-12-01 |
JP5093936B2 (ja) | 2012-12-12 |
JP5647873B2 (ja) | 2015-01-07 |
JP2023033424A (ja) | 2023-03-10 |
JP6937407B2 (ja) | 2021-09-22 |
JP6255075B2 (ja) | 2017-12-27 |
JP2019075581A (ja) | 2019-05-16 |
KR20120094067A (ko) | 2012-08-23 |
JP5767366B2 (ja) | 2015-08-19 |
US20110128777A1 (en) | 2011-06-02 |
JP2014212324A (ja) | 2014-11-13 |
JP6685436B2 (ja) | 2020-04-22 |
JP2015065452A (ja) | 2015-04-09 |
JP6469206B2 (ja) | 2019-02-13 |
JP2022000895A (ja) | 2022-01-04 |
JP2018046295A (ja) | 2018-03-22 |
TWI655626B (zh) | 2019-04-01 |
TWI615838B (zh) | 2018-02-21 |
TWI556236B (zh) | 2016-11-01 |
JP2020129662A (ja) | 2020-08-27 |
JP2015216386A (ja) | 2015-12-03 |
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