JP2011029619A5 - 基板の処理方法 - Google Patents

基板の処理方法 Download PDF

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JP2011029619A5
JP2011029619A5 JP2010142496A JP2010142496A JP2011029619A5 JP 2011029619 A5 JP2011029619 A5 JP 2011029619A5 JP 2010142496 A JP2010142496 A JP 2010142496A JP 2010142496 A JP2010142496 A JP 2010142496A JP 2011029619 A5 JP2011029619 A5 JP 2011029619A5
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semiconductor
layer
substance
substrate
processing method
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JP2011029619A (ja
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Claims (1)

  1. 半導体基板上に、脆化層と、絶縁層と、前記脆化層と前記絶縁層とに挟まれた半導体層と、が選択的に配置された基板の処理方法であって、
    前記脆化層は、半導体に水素イオンを注入する工程を経て形成されたものであり、
    第１のエッチングによって、前記絶縁層を除去し、
    第２のエッチングによって、前記脆化層と前記半導体層とを除去し、
    前記第２のエッチングは、半導体を酸化する酸化剤として機能する物質と、半導体の酸化物を溶解する物質と、半導体の酸化及び半導体の酸化物の溶解の減速剤として機能する物質と、を含む溶液をエッチャントとすることを特徴とする基板の処理方法。
JP2010142496A 2009-06-24 2010-06-23 半導体基板の再生処理方法及びｓｏｉ基板の作製方法 Withdrawn JP2011029619A (ja)

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JP2010142496A JP2011029619A (ja) 2009-06-24 2010-06-23 半導体基板の再生処理方法及びｓｏｉ基板の作製方法

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JP2009149412 2009-06-24
JP2010142496A JP2011029619A (ja) 2009-06-24 2010-06-23 半導体基板の再生処理方法及びｓｏｉ基板の作製方法

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JP2011029619A JP2011029619A (ja) 2011-02-10
JP2011029619A5 true JP2011029619A5 (ja) 2013-05-09

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US (1) US8404563B2 (ja)
JP (1) JP2011029619A (ja)
KR (1) KR20120032487A (ja)
CN (1) CN102460642A (ja)
SG (1) SG176602A1 (ja)
TW (1) TWI524409B (ja)
WO (1) WO2010150671A1 (ja)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8318588B2 (en) 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
SG178179A1 (en) 2009-10-09 2012-03-29 Semiconductor Energy Lab Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate
CN102543675B (zh) * 2010-12-31 2014-11-05 中芯国际集成电路制造(上海)有限公司 玻璃衬底的处理方法
JP2012195579A (ja) * 2011-03-02 2012-10-11 Sumitomo Chemical Co Ltd 半導体基板、電界効果トランジスタ、半導体基板の製造方法および電界効果トランジスタの製造方法
US9123529B2 (en) * 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
FR2980916B1 (fr) * 2011-10-03 2014-03-28 Soitec Silicon On Insulator Procede de fabrication d'une structure de type silicium sur isolant
JP5865057B2 (ja) * 2011-12-19 2016-02-17 株式会社半導体エネルギー研究所 半導体基板の再生方法、及びｓｏｉ基板の作製方法
TWI645578B (zh) 2012-07-05 2018-12-21 半導體能源研究所股份有限公司 發光裝置及發光裝置的製造方法
KR102173801B1 (ko) 2012-07-12 2020-11-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치, 및 표시 장치의 제작 방법
WO2014113617A1 (en) 2013-01-21 2014-07-24 Innovative Finishes LLC Refurbished component, electronic device including the same, and method of refurbishing a component of an electronic device
WO2014186096A1 (en) * 2013-05-17 2014-11-20 Innovative Finishes LLC Refurbishing a component of an electronic device
JP6200273B2 (ja) * 2013-10-17 2017-09-20 信越半導体株式会社 貼り合わせウェーハの製造方法
DE102015000450A1 (de) * 2015-01-15 2016-07-21 Siltectra Gmbh Abtrennvorrichtung zum spanfreien Abtrennen von Wafern von Spendersubstraten
CN107403778A (zh) * 2016-05-19 2017-11-28 胡川 半导体基板及半导体板制作方法
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
WO2018011731A1 (en) * 2016-07-12 2018-01-18 QMAT, Inc. Method of a donor substrate undergoing reclamation
NL2017198B1 (en) * 2016-07-20 2018-01-26 Jiaco Instr Holding B V Decapsulation of electronic devices
FR3077924B1 (fr) 2018-02-13 2020-01-17 Soitec Structure demontable et procede de demontage utilisant ladite structure
US10686037B2 (en) 2018-07-19 2020-06-16 Vanguard International Semiconductor Corporation Semiconductor structure with insulating substrate and fabricating method thereof
TWI692874B (zh) * 2018-09-17 2020-05-01 世界先進積體電路股份有限公司 半導體結構以及製造方法
CN113192823B (zh) * 2021-04-27 2022-06-21 麦斯克电子材料股份有限公司 一种soi键合工艺后衬底片的再生加工方法

Family Cites Families (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4936792B1 (ja) * 1970-10-15 1974-10-03
US4517106A (en) * 1984-04-26 1985-05-14 Allied Corporation Soluble surfactant additives for ammonium fluoride/hydrofluoric acid oxide etchant solutions
JPS6286709A (ja) * 1985-10-11 1987-04-21 Mitsubishi Electric Corp 半導体装置の製造方法
CA2069038C (en) * 1991-05-22 1997-08-12 Kiyofumi Sakaguchi Method for preparing semiconductor member
US5494849A (en) * 1995-03-23 1996-02-27 Si Bond L.L.C. Single-etch stop process for the manufacture of silicon-on-insulator substrates
US5843322A (en) * 1996-12-23 1998-12-01 Memc Electronic Materials, Inc. Process for etching N, P, N+ and P+ type slugs and wafers
JPH10284431A (ja) * 1997-04-11 1998-10-23 Sharp Corp Ｓｏｉ基板の製造方法
US6162705A (en) * 1997-05-12 2000-12-19 Silicon Genesis Corporation Controlled cleavage process and resulting device using beta annealing
US6027988A (en) * 1997-05-28 2000-02-22 The Regents Of The University Of California Method of separating films from bulk substrates by plasma immersion ion implantation
US6548382B1 (en) * 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
JPH1154451A (ja) * 1997-08-07 1999-02-26 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置
US6413874B1 (en) * 1997-12-26 2002-07-02 Canon Kabushiki Kaisha Method and apparatus for etching a semiconductor article and method of preparing a semiconductor article by using the same
JP3932369B2 (ja) 1998-04-09 2007-06-20 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP3395661B2 (ja) * 1998-07-07 2003-04-14 信越半導体株式会社 Ｓｏｉウエーハの製造方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2000223682A (ja) 1999-02-02 2000-08-11 Canon Inc 基体の処理方法及び半導体基板の製造方法
KR100701342B1 (ko) * 1999-07-15 2007-03-29 신에쯔 한도타이 가부시키가이샤 접합 웨이퍼의 제조방법 및 접합 웨이퍼
JP2001085648A (ja) * 1999-07-15 2001-03-30 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法および貼り合わせウエーハ
WO2001011930A2 (en) * 1999-08-10 2001-02-15 Silicon Genesis Corporation A cleaving process to fabricate multilayered substrates using low implantation doses
US6500732B1 (en) * 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
JP3943782B2 (ja) * 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
JP2001274368A (ja) * 2000-03-27 2001-10-05 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法およびこの方法で製造された貼り合わせウエーハ
US6521492B2 (en) * 2000-06-12 2003-02-18 Seiko Epson Corporation Thin-film semiconductor device fabrication method
US7183177B2 (en) * 2000-08-11 2007-02-27 Applied Materials, Inc. Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
JP2002134375A (ja) 2000-10-25 2002-05-10 Canon Inc 半導体基体とその作製方法、および貼り合わせ基体の表面形状測定方法
FR2894990B1 (fr) * 2005-12-21 2008-02-22 Soitec Silicon On Insulator Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede
JP2003163335A (ja) * 2001-11-27 2003-06-06 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
JPWO2003049189A1 (ja) * 2001-12-04 2005-04-21 信越半導体株式会社 貼り合わせウェーハおよび貼り合わせウェーハの製造方法
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
US7119365B2 (en) * 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4289837B2 (ja) * 2002-07-15 2009-07-01 アプライド マテリアルズ インコーポレイテッド イオン注入方法及びｓｏｉウエハの製造方法
JP4328067B2 (ja) * 2002-07-31 2009-09-09 アプライド マテリアルズ インコーポレイテッド イオン注入方法及びｓｏｉウエハの製造方法、並びにイオン注入装置
TWI233154B (en) * 2002-12-06 2005-05-21 Soitec Silicon On Insulator Method for recycling a substrate
EP1427001A1 (en) 2002-12-06 2004-06-09 S.O.I. Tec Silicon on Insulator Technologies S.A. A method for recycling a surface of a substrate using local thinning
EP1427002B1 (en) 2002-12-06 2017-04-12 Soitec A method for recycling a substrate using local cutting
RU2217842C1 (ru) * 2003-01-14 2003-11-27 Институт физики полупроводников - Объединенного института физики полупроводников СО РАН Способ изготовления структуры кремний-на-изоляторе
JP2005072070A (ja) * 2003-08-28 2005-03-17 Sumitomo Mitsubishi Silicon Corp 剥離ウェーハの再生処理方法及び再生されたウェーハ
JP4828230B2 (ja) * 2004-01-30 2011-11-30 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハの製造方法
DE602004018951D1 (de) * 2004-11-09 2009-02-26 Soitec Silicon On Insulator Verfahren zum Herstellen von zusammengesetzten Wafern
US7112289B2 (en) * 2004-11-09 2006-09-26 General Chemical Performance Products Llc Etchants containing filterable surfactant
US7402520B2 (en) * 2004-11-26 2008-07-22 Applied Materials, Inc. Edge removal of silicon-on-insulator transfer wafer
JP4934966B2 (ja) * 2005-02-04 2012-05-23 株式会社Ｓｕｍｃｏ Ｓｏｉ基板の製造方法
JP5122731B2 (ja) * 2005-06-01 2013-01-16 信越半導体株式会社 貼り合わせウェーハの製造方法
JP4977999B2 (ja) * 2005-11-21 2012-07-18 株式会社Ｓｕｍｃｏ 貼合せ基板の製造方法及びその方法で製造された貼合せ基板
JP4715470B2 (ja) 2005-11-28 2011-07-06 株式会社Ｓｕｍｃｏ 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ
US7781309B2 (en) * 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
US7829436B2 (en) * 2005-12-22 2010-11-09 Sumco Corporation Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer
US7790565B2 (en) * 2006-04-21 2010-09-07 Corning Incorporated Semiconductor on glass insulator made using improved thinning process
US7579654B2 (en) * 2006-05-31 2009-08-25 Corning Incorporated Semiconductor on insulator structure made using radiation annealing
US7608521B2 (en) * 2006-05-31 2009-10-27 Corning Incorporated Producing SOI structure using high-purity ion shower
EP1926132A1 (en) * 2006-11-23 2008-05-28 S.O.I.Tec Silicon on Insulator Technologies Chromium-free etching solution for Si-substrates and SiGe-substrates, method for revealing defects using the etching solution and process for treating Si-substrates and SiGe-substrates using the etching solution
JP2008153411A (ja) * 2006-12-18 2008-07-03 Shin Etsu Chem Co Ltd Ｓｏｉ基板の製造方法
JP4820801B2 (ja) * 2006-12-26 2011-11-24 株式会社Ｓｕｍｃｏ 貼り合わせウェーハの製造方法
US7759233B2 (en) * 2007-03-23 2010-07-20 Micron Technology, Inc. Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures
JP5289805B2 (ja) * 2007-05-10 2013-09-11 株式会社半導体エネルギー研究所 半導体装置製造用基板の作製方法
US7939424B2 (en) * 2007-09-21 2011-05-10 Varian Semiconductor Equipment Associates, Inc. Wafer bonding activated by ion implantation
KR101499175B1 (ko) * 2007-10-04 2015-03-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판의 제조방법
US7989305B2 (en) * 2007-10-10 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate using cluster ion
JP5688203B2 (ja) * 2007-11-01 2015-03-25 株式会社半導体エネルギー研究所 半導体基板の作製方法
JP2009272471A (ja) * 2008-05-08 2009-11-19 Sumco Corp 貼り合わせウェーハの製造方法
US20100022070A1 (en) * 2008-07-22 2010-01-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
US8278187B2 (en) * 2009-06-24 2012-10-02 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate by stepwise etching with at least two etching treatments
SG178179A1 (en) * 2009-10-09 2012-03-29 Semiconductor Energy Lab Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate

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