JP2008181651A - Casレイテンシを利用してロッキングレゾリューション調節が可能な遅延同期ループ回路 - Google Patents
Casレイテンシを利用してロッキングレゾリューション調節が可能な遅延同期ループ回路 Download PDFInfo
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- JP2008181651A JP2008181651A JP2008029034A JP2008029034A JP2008181651A JP 2008181651 A JP2008181651 A JP 2008181651A JP 2008029034 A JP2008029034 A JP 2008029034A JP 2008029034 A JP2008029034 A JP 2008029034A JP 2008181651 A JP2008181651 A JP 2008181651A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
Abstract
【解決手段】遅延ライン、位相検出器、制御回路を備える。遅延ラインは、直列連結された多数の単位遅延器を含んで制御信号に応答して選択される単位遅延器を通じて外部クロック信号を遅延させる。位相検出器は、前記外部クロック信号の位相と前記遅延ラインから出力される内部クロック信号の位相とを比較し、外部クロック信号と遅延ラインから出力される内部クロック信号間の位相差を検出する。制御回路は、前記位相検出器の出力信号に応答して前記制御信号を発して遅延制御信号に応答して前記遅延ラインのロッキング位相ステップを可変にする。
【選択図】図7
Description
前述の如く、本発明による遅延同期ループ回路は単位遅延器の数を増やさなくとも広いロッキング範囲を有し、またロッキングサイクル時間を減らせる長所がある。
33…遅延ライン
35…制御回路
37…遅延補償器
38…単位遅延時間調節回路
39…モードレジスタセット
Claims (5)
- 直列連結された多数の単位遅延器を含んで制御信号に応答して選択される単位遅延器を通じて外部クロック信号を遅延させる遅延ラインと、
前記外部クロック信号の位相と前記遅延ラインから出力される内部クロック信号の位相とを比較する位相検出器と、
前記位相検出器の出力信号に応答して前記制御信号を発して遅延制御信号に応答して前記遅延ラインのロッキング位相ステップを可変にする制御回路と
を備えることを特徴とする遅延同期ループ回路。 - 前記遅延制御信号はCASレイテンシ信号である
ことを特徴とする請求項1に記載の遅延同期ループ回路。 - 前記遅延同期ループ回路は、前記CASレイテンシ信号を出力するモードレジスタセットをさらに備える
ことを特徴とする請求項2に記載の遅延同期ループ回路。 - 前記遅延同期ループ回路は、前記内部クロック信号が出力される前記遅延ラインの出力端と前記位相検出器間に連結され、前記内部クロック信号を所定時間遅延させ、遅延された信号を前記位相検出器に提供する遅延補償器をさらに備える
ことを特徴とする請求項1に記載の遅延同期ループ回路。 - 前記制御回路は、
多数のステージより構成され、各ステージの出力端から前記制御信号を出力するシフトレジスタと、
各ステージ間に連結されて対応する遅延制御信号に応答する多数のスイッチと、
前記位相検出器の出力信号に応答して前記シフトレジスタを制御するシフトレジスタ制御部と
を備えることを特徴とする請求項1に記載の遅延同期ループ回路。
Applications Claiming Priority (1)
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KR10-2001-0069229A KR100446291B1 (ko) | 2001-11-07 | 2001-11-07 | 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로 |
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JP2002309883A Division JP4562979B2 (ja) | 2001-11-07 | 2002-10-24 | Casレイテンシを利用してロッキングレゾリューション調節が可能な遅延同期ループ回路 |
Publications (1)
Publication Number | Publication Date |
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JP2008181651A true JP2008181651A (ja) | 2008-08-07 |
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JP2002309883A Expired - Fee Related JP4562979B2 (ja) | 2001-11-07 | 2002-10-24 | Casレイテンシを利用してロッキングレゾリューション調節が可能な遅延同期ループ回路 |
JP2008029034A Pending JP2008181651A (ja) | 2001-11-07 | 2008-02-08 | Casレイテンシを利用してロッキングレゾリューション調節が可能な遅延同期ループ回路 |
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JP2002309883A Expired - Fee Related JP4562979B2 (ja) | 2001-11-07 | 2002-10-24 | Casレイテンシを利用してロッキングレゾリューション調節が可能な遅延同期ループ回路 |
Country Status (5)
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US (1) | US6621315B2 (ja) |
JP (2) | JP4562979B2 (ja) |
KR (1) | KR100446291B1 (ja) |
DE (1) | DE10252491B4 (ja) |
TW (1) | TW578381B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101326117B1 (ko) | 2013-06-25 | 2013-11-06 | 홍익대학교 산학협력단 | 위상 반전 록킹 알고리즘을 이용한 디지털 지연 고정 루프 회로 및 제어방법 |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6081147A (en) * | 1994-09-29 | 2000-06-27 | Fujitsu Limited | Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof |
US7251305B2 (en) * | 2002-05-17 | 2007-07-31 | Sun Microsystems, Inc. | Method and apparatus to store delay locked loop biasing parameters |
US6891415B2 (en) * | 2002-06-11 | 2005-05-10 | Micron Technology, Inc. | Method and apparatus for enabling a timing synchronization circuit |
US6819599B2 (en) * | 2002-08-01 | 2004-11-16 | Micron Technology, Inc. | Programmable DQS preamble |
DE10330796B4 (de) * | 2002-10-30 | 2023-09-14 | Hynix Semiconductor Inc. | Registergesteuerter Delay Locked Loop mit Beschleunigungsmodus |
KR100500929B1 (ko) * | 2002-11-27 | 2005-07-14 | 주식회사 하이닉스반도체 | 지연 고정 루프 회로 |
KR100518548B1 (ko) * | 2002-12-30 | 2005-10-04 | 삼성전자주식회사 | 개선된 보상 지연 회로를 가지는 반도체 메모리 장치의dll 및 이에 대한 지연시간 보상방법 |
US8934597B2 (en) * | 2003-03-12 | 2015-01-13 | Infineon Technologies Ag | Multiple delay locked loop integration system and method |
US6865135B2 (en) * | 2003-03-12 | 2005-03-08 | Micron Technology, Inc. | Multi-frequency synchronizing clock signal generator |
US7477716B2 (en) * | 2003-06-25 | 2009-01-13 | Mosaid Technologies, Inc. | Start up circuit for delay locked loop |
KR100531457B1 (ko) * | 2003-07-23 | 2005-11-28 | (주)다윈텍 | 다 위상 클럭신호 발생을 위한 발진기가 배제된 지연 동기루프 |
KR100541548B1 (ko) * | 2003-09-08 | 2006-01-11 | 삼성전자주식회사 | 대역 확산 클럭 발생회로 및 방법 |
KR100542696B1 (ko) * | 2003-11-13 | 2006-01-11 | 주식회사 하이닉스반도체 | 반도체 장치의 리페어 퓨즈 박스 |
US7065666B2 (en) * | 2003-11-13 | 2006-06-20 | Micron Technology, Inc. | Apparatus and method for generating a delayed clock signal |
KR100514414B1 (ko) * | 2003-11-20 | 2005-09-09 | 주식회사 하이닉스반도체 | 지연 동기 루프 |
US6952127B2 (en) * | 2003-11-21 | 2005-10-04 | Micron Technology, Inc. | Digital phase mixers with enhanced speed |
US6982578B2 (en) * | 2003-11-26 | 2006-01-03 | Micron Technology, Inc. | Digital delay-locked loop circuits with hierarchical delay adjustment |
US6914467B2 (en) * | 2003-12-04 | 2005-07-05 | International Business Machines Corporation | Dual edge programmable delay unit |
KR100546215B1 (ko) * | 2003-12-05 | 2006-01-24 | 주식회사 하이닉스반도체 | 펄스 폭 제어 회로 |
US6982579B2 (en) * | 2003-12-11 | 2006-01-03 | Micron Technology, Inc. | Digital frequency-multiplying DLLs |
US7795934B2 (en) * | 2003-12-11 | 2010-09-14 | Micron Technology, Inc. | Switched capacitor for a tunable delay circuit |
US7009434B2 (en) * | 2003-12-12 | 2006-03-07 | Micron Technology, Inc. | Generating multi-phase clock signals using hierarchical delays |
US7222224B2 (en) * | 2004-05-21 | 2007-05-22 | Rambus Inc. | System and method for improving performance in computer memory systems supporting multiple memory access latencies |
JP4271623B2 (ja) * | 2004-06-17 | 2009-06-03 | 富士通株式会社 | クロック調整装置および方法 |
US7157952B2 (en) * | 2004-08-20 | 2007-01-02 | L-3 Integrated Systems Company | Systems and methods for implementing delay line circuitry |
US7920017B2 (en) * | 2004-12-16 | 2011-04-05 | Analog Devices, Inc. | Programmable clock booster system |
KR100713082B1 (ko) * | 2005-03-02 | 2007-05-02 | 주식회사 하이닉스반도체 | 클럭의 듀티 비율을 조정할 수 있는 지연 고정 루프 |
US7428284B2 (en) * | 2005-03-14 | 2008-09-23 | Micron Technology, Inc. | Phase detector and method providing rapid locking of delay-lock loops |
JP4667196B2 (ja) * | 2005-10-12 | 2011-04-06 | パナソニック株式会社 | 位相調整回路 |
KR100723511B1 (ko) * | 2005-11-14 | 2007-05-30 | 삼성전자주식회사 | 전하 펌프 회로, 이를 포함하는 위상 동기 루프 회로 및지연 동기 루프 회로 |
KR100656464B1 (ko) * | 2005-12-28 | 2006-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리의 출력 인에이블 신호 생성장치 및 방법 |
EP1806751A1 (en) * | 2005-12-30 | 2007-07-11 | STMicroelectronics Pvt. Ltd. | Programmable delay introducing circuit in self timed memory |
US7982511B2 (en) * | 2006-02-09 | 2011-07-19 | Hynix Semiconductor Inc. | DLL circuit and method of controlling the same |
US7716511B2 (en) * | 2006-03-08 | 2010-05-11 | Freescale Semiconductor, Inc. | Dynamic timing adjustment in a circuit device |
JP5143370B2 (ja) * | 2006-03-23 | 2013-02-13 | 富士通セミコンダクター株式会社 | 遅延制御回路 |
KR100807116B1 (ko) * | 2006-10-31 | 2008-02-26 | 주식회사 하이닉스반도체 | 지연 고정 루프 |
KR100795025B1 (ko) * | 2006-12-07 | 2008-01-16 | 주식회사 하이닉스반도체 | Dll 회로의 동작 모드 설정 장치 및 방법 |
US7755403B2 (en) | 2006-11-14 | 2010-07-13 | Hynix Semiconductor Inc. | Apparatus and method of setting operation mode in DLL circuit |
KR100784921B1 (ko) * | 2006-11-14 | 2007-12-11 | 주식회사 하이닉스반도체 | Dll 회로의 동작 모드 설정 장치 |
JP4774005B2 (ja) * | 2007-04-11 | 2011-09-14 | ザインエレクトロニクス株式会社 | 受信装置 |
KR100857446B1 (ko) * | 2007-05-11 | 2008-09-10 | 주식회사 하이닉스반도체 | Dll 회로의 동작 모드 설정 장치 |
TWI358902B (en) * | 2007-12-31 | 2012-02-21 | Ind Tech Res Inst | Signal delay circuit |
CN101562450B (zh) * | 2008-04-16 | 2012-07-18 | 北京兆易创新科技有限公司 | 逐位逼近延迟锁相环电路以及调整时钟信号的方法 |
JP2010028342A (ja) * | 2008-07-17 | 2010-02-04 | Sanyo Electric Co Ltd | Dll回路 |
US8181056B2 (en) * | 2008-09-30 | 2012-05-15 | Mosaid Technologies Incorporated | Serial-connected memory system with output delay adjustment |
US8161313B2 (en) * | 2008-09-30 | 2012-04-17 | Mosaid Technologies Incorporated | Serial-connected memory system with duty cycle correction |
US7864625B2 (en) * | 2008-10-02 | 2011-01-04 | International Business Machines Corporation | Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator |
KR101004665B1 (ko) * | 2009-06-12 | 2011-01-04 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 및 출력 인에이블 신호 생성 방법 |
US8531909B2 (en) | 2010-06-18 | 2013-09-10 | SK Hynix Inc. | Delay-locked loop having loop bandwidth dependency on operating frequency |
US8269535B1 (en) | 2011-07-15 | 2012-09-18 | Elite Semiconductor Memory Technology Inc. | Delay-locked loop and method of using the same |
US9225322B2 (en) | 2013-12-17 | 2015-12-29 | Micron Technology, Inc. | Apparatuses and methods for providing clock signals |
CN105610434B (zh) * | 2016-02-26 | 2018-08-10 | 西安紫光国芯半导体有限公司 | 一种自适应的延迟锁相环 |
CN108551342B (zh) * | 2018-03-20 | 2022-04-01 | 上海集成电路研发中心有限公司 | 一种具有宽频率输入范围的延迟锁相环 |
US10762947B2 (en) * | 2018-10-04 | 2020-09-01 | Samsung Electronics Co., Ltd. | Memory devices |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0246598A (ja) * | 1988-08-09 | 1990-02-15 | Matsushita Electric Ind Co Ltd | 可変長シフト・レジスタ |
JPH1013219A (ja) * | 1996-06-27 | 1998-01-16 | Mitsubishi Electric Corp | クロック信号のズレを防止する回路 |
JPH11205128A (ja) * | 1998-01-14 | 1999-07-30 | Toshiba Microelectronics Corp | 位相制御装置及びその方法 |
JPH11298307A (ja) * | 1998-04-09 | 1999-10-29 | Fujitsu Ltd | 半導体装置 |
JPH11355131A (ja) * | 1998-06-11 | 1999-12-24 | Fujitsu Ltd | Dll回路 |
JP2000101425A (ja) * | 1998-09-02 | 2000-04-07 | Samsung Electronics Co Ltd | 半導体メモリ装置の遅延同期ル―プ回路及びそれに対する制御方法 |
JP2000207052A (ja) * | 1998-12-30 | 2000-07-28 | Hyundai Electronics Ind Co Ltd | 遅延固定ル―プの初期ロックタイム短縮装置及び方法 |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2751819B2 (ja) | 1994-02-28 | 1998-05-18 | 松下電器産業株式会社 | テレビジョン信号処理装置 |
JP2771464B2 (ja) * | 1994-09-29 | 1998-07-02 | 日本電気アイシーマイコンシステム株式会社 | ディジタルpll回路 |
JPH08180678A (ja) * | 1994-12-27 | 1996-07-12 | Hitachi Ltd | ダイナミック型ram |
US5841707A (en) * | 1995-11-29 | 1998-11-24 | Texas Instruments Incorporated | Apparatus and method for a programmable interval timing generator in a semiconductor memory |
JPH1069769A (ja) | 1996-08-29 | 1998-03-10 | Fujitsu Ltd | 半導体集積回路 |
JPH10283779A (ja) * | 1997-04-09 | 1998-10-23 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP4040140B2 (ja) * | 1997-05-14 | 2008-01-30 | 富士通株式会社 | 半導体装置及びそのアクセスタイム調整方法 |
US6100736A (en) * | 1997-06-05 | 2000-08-08 | Cirrus Logic, Inc | Frequency doubler using digital delay lock loop |
JP3161377B2 (ja) | 1997-07-25 | 2001-04-25 | 日本電気株式会社 | 半導体記憶装置 |
JPH11120769A (ja) * | 1997-10-13 | 1999-04-30 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
KR100274602B1 (ko) * | 1997-11-20 | 2000-12-15 | 윤종용 | 동기형 메모리 장치 |
KR100264077B1 (ko) * | 1997-11-21 | 2000-08-16 | 김영환 | 반도체 소자의 클럭보상장치 |
JPH11203864A (ja) * | 1998-01-14 | 1999-07-30 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
KR100293448B1 (ko) * | 1998-03-28 | 2001-07-12 | 김영환 | 출력클럭의위상조절장치 |
KR100263483B1 (ko) * | 1998-05-14 | 2000-08-01 | 김영환 | 고속 위상 동기 회로 및 그를 이용한 위상 동기 방법 |
US6137334A (en) * | 1998-07-06 | 2000-10-24 | Micron Technology, Inc. | Logic circuit delay stage and delay line utilizing same |
JP3644827B2 (ja) * | 1998-08-14 | 2005-05-11 | 富士通株式会社 | 外部負荷を考慮したdll回路 |
JP4286933B2 (ja) | 1998-09-18 | 2009-07-01 | 富士通マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
JP3993717B2 (ja) | 1998-09-24 | 2007-10-17 | 富士通株式会社 | 半導体集積回路装置 |
KR100351889B1 (ko) * | 1998-11-13 | 2002-11-18 | 주식회사 하이닉스반도체 | 카스(cas)레이턴시(latency) 제어 회로 |
JP2000195263A (ja) | 1998-12-25 | 2000-07-14 | Nec Corp | 半導体記憶装置 |
US6177844B1 (en) * | 1999-01-08 | 2001-01-23 | Altera Corporation | Phase-locked loop or delay-locked loop circuitry for programmable logic devices |
JP3957421B2 (ja) | 1999-02-10 | 2007-08-15 | エルピーダメモリ株式会社 | 半導体記憶装置 |
JP2000231420A (ja) | 1999-02-10 | 2000-08-22 | Nippon Foundry Inc | タイミング信号発生回路 |
KR100304705B1 (ko) * | 1999-03-03 | 2001-10-29 | 윤종용 | 포스티드 카스 레이턴시 기능을 가지는 동기식 반도체 메모리 장치 및 카스 레이턴시 제어 방법 |
US6150856A (en) | 1999-04-30 | 2000-11-21 | Micron Technology, Inc. | Delay lock loops, signal locking methods and methods of implementing delay lock loops |
JP4190662B2 (ja) * | 1999-06-18 | 2008-12-03 | エルピーダメモリ株式会社 | 半導体装置及びタイミング制御回路 |
JP4397076B2 (ja) * | 1999-08-20 | 2010-01-13 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2001060392A (ja) * | 1999-08-24 | 2001-03-06 | Mitsubishi Electric Corp | 半導体装置 |
US6240042B1 (en) | 1999-09-02 | 2001-05-29 | Micron Technology, Inc. | Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal |
JP2001084763A (ja) * | 1999-09-08 | 2001-03-30 | Mitsubishi Electric Corp | クロック発生回路およびそれを具備した半導体記憶装置 |
JP3807593B2 (ja) * | 2000-07-24 | 2006-08-09 | 株式会社ルネサステクノロジ | クロック生成回路および制御方法並びに半導体記憶装置 |
-
2001
- 2001-11-07 KR KR10-2001-0069229A patent/KR100446291B1/ko not_active IP Right Cessation
-
2002
- 2002-05-01 US US10/135,454 patent/US6621315B2/en not_active Expired - Lifetime
- 2002-09-20 TW TW091121578A patent/TW578381B/zh not_active IP Right Cessation
- 2002-10-24 JP JP2002309883A patent/JP4562979B2/ja not_active Expired - Fee Related
- 2002-11-06 DE DE10252491A patent/DE10252491B4/de not_active Expired - Fee Related
-
2008
- 2008-02-08 JP JP2008029034A patent/JP2008181651A/ja active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0246598A (ja) * | 1988-08-09 | 1990-02-15 | Matsushita Electric Ind Co Ltd | 可変長シフト・レジスタ |
JPH1013219A (ja) * | 1996-06-27 | 1998-01-16 | Mitsubishi Electric Corp | クロック信号のズレを防止する回路 |
JPH11205128A (ja) * | 1998-01-14 | 1999-07-30 | Toshiba Microelectronics Corp | 位相制御装置及びその方法 |
JPH11298307A (ja) * | 1998-04-09 | 1999-10-29 | Fujitsu Ltd | 半導体装置 |
JPH11355131A (ja) * | 1998-06-11 | 1999-12-24 | Fujitsu Ltd | Dll回路 |
JP2000101425A (ja) * | 1998-09-02 | 2000-04-07 | Samsung Electronics Co Ltd | 半導体メモリ装置の遅延同期ル―プ回路及びそれに対する制御方法 |
JP2000207052A (ja) * | 1998-12-30 | 2000-07-28 | Hyundai Electronics Ind Co Ltd | 遅延固定ル―プの初期ロックタイム短縮装置及び方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101326117B1 (ko) | 2013-06-25 | 2013-11-06 | 홍익대학교 산학협력단 | 위상 반전 록킹 알고리즘을 이용한 디지털 지연 고정 루프 회로 및 제어방법 |
Also Published As
Publication number | Publication date |
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KR100446291B1 (ko) | 2004-09-01 |
JP2003203481A (ja) | 2003-07-18 |
DE10252491B4 (de) | 2008-09-11 |
US20030085744A1 (en) | 2003-05-08 |
KR20030037675A (ko) | 2003-05-14 |
US6621315B2 (en) | 2003-09-16 |
TW578381B (en) | 2004-03-01 |
DE10252491A1 (de) | 2003-05-28 |
JP4562979B2 (ja) | 2010-10-13 |
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