JP2007150242A - 半導体素子のキャパシタ製造方法 - Google Patents
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Abstract
【解決手段】下部電極15を形成するステップと、該下部電極上にALD法でジルコニウム、アルミニウム及び酸素がそれぞれ所定のモル分率x、y、zを有して混合されたZrxAlyOz誘電膜16を形成するステップと、該誘電膜上に上部電極17を形成するステップとを含む。
【選択図】図2C
Description
12 層間絶縁膜
13 コンタクトホール
14 ストレージノードコンタクト
15 下部電極
16 ZrxAlyOz誘電膜
17 上部電極
Claims (15)
- 半導体基板上に下部電極を形成するステップと、
前記下部電極上にALD法を利用して、ジルコニウム、アルミニウム及び酸素がそれぞれ所定のモル分率x、y、及びzを有して混合されたZrxAlyOz誘電膜を形成するステップと、
前記誘電膜上に上部電極を形成するステップと、を含むことを特徴とする半導体素子のキャパシタ製造方法。 - 前記ZrxAlyOz誘電膜において、
前記モル分率x、y及びzの合計が1であり、前記モル分率xを前記モル分率yで除した値が1〜10の範囲内の値であることを特徴とする請求項1に記載の半導体素子のキャパシタ製造方法。 - 前記ZrxAlyOz誘電膜を形成する前記ステップが、
Zrソースガスを用いて前記下部電極にZrソースを吸着させるステップと、
第1のパージガスを供給して未吸着の前記Zrソースガスを除去するステップと、
前記下部電極上に吸着された前記Zrソース上に、Alソースガスを用いてAlソースを吸着させるステップと、
第2のパージガスを供給して未吸着の前記Alソースガスを除去するステップと、
反応ガスを供給し、前記下部電極上に吸着された前記Zrソース及びAlソースと反応させて前記ZrxAlyOz誘電膜を形成するステップと、
第3のパージガスを供給して未反応の前記反応ガスを除去するステップと、を含むことを特徴とする請求項1に記載の半導体素子のキャパシタ製造方法。 - 前記Zrソースガスが、
ZrCl4、Zr[N(CH3)C2H5]4、Zr(O−tBu)4、 Zr[N(CH3)2]4、Zr[N(C2H5)(CH3)]4、Zr[N(C2H5)2)]4、Zr(tmhd)4、Zr(OiC3H7)3(tmtd)、Zr(OtBu)4、及びZrを含有した化合物からなる群の中から選択されるいずれか1つを含むことを特徴とする請求項3に記載の半導体素子のキャパシタ製造方法。 - 前記Alソースガスが、
Al(CH3)3、Al(C2H5)3、及びAlを含有した化合物からなる群の中から選択されるいずれか1つを含むことを特徴とする請求項3に記載の半導体素子のキャパシタ製造方法。 - 前記反応ガスが、濃度が100〜500g/m3であるO3、O2、プラズマO2、 N2O、プラズマN2O、及びH2O蒸気からなる群の中から選択されるいずれか1つを含み、0.1〜1slmの範囲の流量で3〜10秒間供給され、
前記第1、第2、及び第3のパージガスが、N2ガス又はArガスを含むことを特徴とする請求項3に記載の半導体素子のキャパシタ製造方法。 - 前記ZrxAlyOz誘電膜が、50Å〜100Åの範囲の厚さに形成されることを特徴とする請求項1又は3に記載の半導体素子のキャパシタ製造方法。
- 前記ZrxAlyOz誘電膜を形成する際、前記半導体基板の温度を200℃〜500℃の範囲内の温度にし、反応チャンバーの圧力を13.3〜133.3Pa(0.1〜1Torr)の範囲内の圧力にすることを特徴とする請求項1又は3に記載の半導体素子のキャパシタ製造方法。
- 前記ZrxAlyOz誘電膜を形成する前記ステップの後に、アニーリングを行うステップをさらに含むことを特徴とする請求項1又は3に記載の半導体素子のキャパシタ製造方法。
- 前記アニーリングが、
200℃〜500℃の温度、13.3〜1333Pa(0.1〜10Torr)の圧力、及び5sccm〜5slmの流量で供給される、N2、H2、N2/H2、NH3、N2O、N2/O2及びO3からなる群の中から選択されるいずれか1つのガスの雰囲気で、プラズマを用いた1〜5分間のアニーリングであり、且つ、前記プラズマが、100〜500Wの範囲のRFパワーを有することを特徴とする請求項9に記載の半導体素子のキャパシタ製造方法。 - 前記アニーリングが、500℃〜800℃の温度を有する933〜1013hPa(700〜760Torr)の常圧又は1.3〜133.3hPa(1〜100Torr)の減圧のチャンバー内で、N2、H2、N2/H2、NH3、N2O、N2/O2、及びO3からなる群の中から選択されるいずれか1つのガスを5sccm〜5slmの範囲内の流量でフローさせながら、RTP法によって行われることを特徴とする請求項9に記載の半導体素子のキャパシタ製造方法。
- 前記アニーリングが、
600℃〜800℃の範囲の温度でN2、H2、N2/H2、NH3、N2O、N2/O2及びO3からなる群の中から選択されるいずれか1つのガスを5sccm〜5slmの範囲内の流量でフローさせながら、電気炉で行われるアニーリングであることを特徴とする請求項9に記載の半導体素子のキャパシタ製造方法。 - 前記下部電極及び前記上部電極が、TiN、TaN、W、WN、Ru、RuO2、Ir、IrO2、及びPtからなる群の中から選択されるいずれか1つの物質を含んで形成されることを特徴とする請求項1に記載の半導体素子のキャパシタ製造方法。
- 前記下部電極を形成する前記ステップの後に、N2、H2、N2/H2、O2、O3、及びNH3からなる群の中から選択されるいずれか1つのガスの雰囲気でアニーリングを行うステップをさらに含むことを特徴とする請求項1に記載の半導体素子のキャパシタ製造方法。
- 前記上部電極を形成する前記ステップの後に、前記上部電極が形成された基板上にAl2O3、HfO2、Ta2O5、ZrO2、TiO2及びLa2O3からなる群の中から選択されるいずれか1つの酸化膜又は金属膜からなる保護膜をALD法で50〜200Åの厚さに形成するステップをさらに含むことを特徴とする請求項1に記載の半導体素子のキャパシタ製造方法。
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US7825043B2 (en) | 2010-11-02 |
TW200721389A (en) | 2007-06-01 |
JP5094057B2 (ja) | 2012-12-12 |
CN100514606C (zh) | 2009-07-15 |
KR100670747B1 (ko) | 2007-01-17 |
DE102006030707A1 (de) | 2007-05-31 |
CN1976008A (zh) | 2007-06-06 |
DE102006030707B4 (de) | 2011-06-22 |
TWI322487B (en) | 2010-03-21 |
US20070122967A1 (en) | 2007-05-31 |
ITMI20061269A1 (it) | 2007-05-29 |
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