CN1976008A - 半导体器件中电容器的制造方法 - Google Patents

半导体器件中电容器的制造方法 Download PDF

Info

Publication number
CN1976008A
CN1976008A CNA2006101523079A CN200610152307A CN1976008A CN 1976008 A CN1976008 A CN 1976008A CN A2006101523079 A CNA2006101523079 A CN A2006101523079A CN 200610152307 A CN200610152307 A CN 200610152307A CN 1976008 A CN1976008 A CN 1976008A
Authority
CN
China
Prior art keywords
gas
dielectric layer
annealing process
supply
yue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006101523079A
Other languages
English (en)
Other versions
CN100514606C (zh
Inventor
李起正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN1976008A publication Critical patent/CN1976008A/zh
Application granted granted Critical
Publication of CN100514606C publication Critical patent/CN100514606C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02189—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing zirconium, e.g. ZrO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02192—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

一种制造半导体器件中电容器的方法，包括：形成底电极；利用原子层沉积(ALD)法在底电极上形成ZrxAlyOz介电层，其中ZrxAlyOz介电层包含分别以预定摩尔分数x、y和z混合的锆(Zr)组分、铝(Al)组分和氧(O)组分；以及在ZrxAlyOz介电层上形成顶电极。

Description

半导体器件中电容器的制造方法
技术领域
本发明涉及制造半导体器件的方法，更具体涉及制造半导体器件中电容器的方法。
背景技术
随着半导体器件例如DRAM变得高度集成，单元尺寸和工作电压减小。因此，器件刷新时间通常被缩短，并且可经常发生软错误。为了克服这些缺点，需要研制具有25fF/单元或更高电容量并且漏电流减少的电容器。
通常，利用Si3N4作为介电材料形成在氮化物和氧化物(NO)结构中的电容器在大规模集成时在电容量方面是不利的。没有足够的面积以获得所需的电容。为了获得足够的电容，研制在单介电层中使用高K介电材料(例如氧化钽(Ta2O5)、氧化镧(La2O3)或氧化铪(HfO2))而不使用Si3N4的电容器结构。这种特定电容器结构被称为多晶硅-绝缘体-多晶硅(SIS)结构。
但是，使用Al2O3介电材料的SIS电容器结构在512M水平或更高水平的动态随机存取存储器(DRAMs)中可存在电容限制。因此，许多研究人员致力于研发其它电容器结构，例如使用氮化钛(TiN)电极的金属-绝缘体-金属(MIM)结构和HfO2/Al2O3或HfO2/Al2O3/HfO2介电结构。
当使用上述电容器结构时，期望的等价氧化物厚度(Tox)是约12。为了增加电容量而不减少氧化物厚度，可以利用3D电极结构增加电容器面积。在采用亚70nm水平金属互连技术的DRAM产品中，获得约25fF/单元或更高的单元电容量可以导致复杂的底电极结构。因此，如果不增大底电极结构的面积，则可能难以获得所需的电容。
近来，对MIM电容器结构的许多研究已经取得进展。这些MIM电容器结构利用贵金属例如钌(Ru)作为电极材料以及Ta2O5或HfO2作为单介电材料。
但是，如果等价氧化物厚度减小到约12或更小同时又采用Ru电极，则MIM电容器可能具有高漏电流，在某些情况下约为1fA/单元。因此，可能难以在采用亚70nm水平互连技术的具有512M或更高容量的RDAM中实现这种MIM电容器。
发明内容
本发明的实施方案涉及半导体器件中电容器的制造方法，其中使利用亚70nm水平互连技术实现的RDAM产品中的漏电流减少并且电容量增加。
根据本发明的实施方案，提供一种用于制造半导体器件中电容器的方法，包括：形成底电极；利用原子层沉积(ALD)法在底电极上形成ZrxAlyOz介电层，其中ZrxAlyOz介电层包含分别以预定摩尔分数x、y和z混合的锆(Zr)组分、铝(Al)组分和氧(O)组分；以及在ZrxAlyOz介电层上形成顶电极。
附图说明
图1是说明根据本发明实施方案的电容器结构的图示；
图2A-2C是说明根据本发明实施方案制造半导体器件中电容器的方法的横截面图；
图3是描述根据本发明实施方案基于原子层沉积(ALD)法形成ZrxAlyOz介电层的顺序操作的图示。
具体实施方式
下面将参考附图详细说明本发明的具体实施方案，其中在不同的附图中相同的标记数字表示相同的元件。
参考图1，ZrxAlyOz介电层16和顶电极17顺序形成在底电极15上。ZrxAlyOz介电层16含有受控摩尔分数的锆(Zr)、铝(Al)和氧(O)。而且，利用原子层沉积(ALD)法形成厚度约50-100的ZrxAlyOz介电层16。
在ZrxAlyOz介电层16中，“ZrxAlyOz”中的下标x、y和z表示Zr、Al和O的摩尔分数。当相加到一起时(即x+y+z)，这些摩尔分数约为1。而且，x与y的比大约为1∶1-10∶1。这种比值表示ZrxAlyOz介电层16中Zr组分的摩尔分数范围可以从等于Al组分至10倍于Al组分。
参考图2A，在衬底11上形成层间绝缘层12，在该衬底11中已经形成包括位线和晶体管的底结构。蚀刻层间绝缘层12以形成暴露衬底11的结合区或连接塞多晶硅(landing plug polys(LPPs))的接触孔13。导电材料填充接触孔以形成存储节点接触14。
底电极材料形成在层间绝缘层12和存储节点接触14上。然后在底电极材料上实施化学机械抛光(CMP)工艺或回蚀刻工艺，以隔离并产生接触存储节点接触14的各个底电极15。
底电极15包括由下列任一物质构成的金属基材料：氮化钛(TiN)、氮化钽(TaN)、钨(W)、氮化钨(WN)、钌(Ru)、氧化钌(RuO2)、铱(Ir)、氧化铱(IrO2)或铂(Pt)。而且，形成厚度为约200-500的底电极15。除了如图2A中所示的圆柱形结构之外，底电极15还可以形成为其它的结构，例如凹形结构或叠层结构。
作为实例，如果底电极15采用TiN，则将TiCl4用作源材料和NH3作为反应气体。以约10sccm-1000sccm的流量分别提供源材料和反应气体。此时，反应室保持在约0.1Torr-10Torr，衬底11保持在约500℃-700℃。底电极15(即TiN层)形成约200-500的厚度。
在形成底电极15之后，在环境气体中实施退火过程，所述环境气体选自氮气(N2)、氢气(H2)、N2/H2、氧气(O2)、臭氧(O3)和氨(NH3)。实施退火过程以使底电极15致密化；去除底电极15中经常导致漏电流增加的残留物杂质；以及消除可引起不均匀电场分布的表面粗糙。
利用等离子体退火法、炉退火法或快速热退火法(RTP)来实施退火过程。在以下条件下实施等离子体退火过程约1-5分钟：以约100W-500W的射频(RF)功率产生等离子体；约0.1Torr-10Torr的压力；约5sccm-5000sccm的所选环境气体。炉退火过程利用约5sccm-5000sccm的所选环境气体在约200℃-500℃下实施。在约500℃-800℃的温度下、利用约5sccm-5000sccm的所选环境气体在腔室中实施RTP，其中腔室保持有约700torr-约760torr的上升压力或约1torr-约100torr的下降压力。
参考图2B，ZrxAlyOz介电层16形成在底电极15上。氧化锆(ZrO2)薄膜和氧化铝(Al2O3)薄膜混合在一起以形成ZrxAlyOz介电层16。具体地，通过实施原子层沉积(ALD)法获得ZrxAlyOz介电层16，这将参考图3详细说明。
参考图2C，顶电极17形成在ZrxAlyOz介电层16上。顶电极17包括TiN、TaN、W、WN、Ru、RuO2、Ir、IrO2或Pt。所示的电容器结构是MIM电容器结构。
作为实例，顶电极17可以是通过实施化学气相沉积(CVD)或物理气相沉积(PVD)获得的TiN层。对于CVD法，分别将TiCl4和NH3用作源材料和反应气体。分别以约10sccm-1000sccm的流量提供源材料和反应气体。此时，反应室保持在约0.1Torr-10Torr，衬底11保持在约500℃-600℃。TiN层(即顶电极17)形成约200-400的厚度。
之后，可以形成厚度约50-200的氧化物层或金属层。氧化物层通过实施ALD法形成并且可以包括诸如Al2O3、HfO2、Ta2O5、ZrO2、TiO2或La2O3的材料，金属层可以包括TiN。氧化物层或金属层形成为钝化层或缓冲层，以提高抵抗在实施后续集成过程的热处理和固化处理(末端加工)、湿蚀刻过程、封装过程和可靠性环境测试时可能产生的湿度、温度或电冲击的结构稳定性。例如，在环境气体例如H2、N2或N2/H2中实施热处理和固化处理。
图3是说明根据本发明实施方案基于原子层沉积(ALD)法形成ZrxAlyOz介电层的过程的图示。
如图所示，ALD法包括供应源气体、清除未反应部分的源气体、供应反应气体和清除未反应部分的反应气体。重复实施ALD法，直到形成预定厚度的ZrxAlyOz介电层。
更具体而言，供应源气体以吸附到目标物中，供应吹扫气体以清除未被吸附的过量源气体。然后，供应反应气体并使其与吸附的源气体反应，从而沉积所需的薄层。然后再次供应吹扫气体以清除未反应的部分反应气体。
通过实施ALD法的上述单元循环以获得ZrxAlyOz介电层，该单元循环包括供应Zr源气体、Al源气体，供应吹扫气体，供应反应气体，再次供应吹扫气体。重复单元循环直到ZrxAlyOz介电层的厚度为约50-100。此时，衬底保持约200℃-500℃，反应室保持约0.1Torr-1Torr。
Zr源气体选自ZrCl4、Zr[N(CH3)C2H5]4、Zr(O-tBu)4、Zr[N(CH3)2]4、Zr[N(C2H5)(CH3)]4、Zr[N(C2H5)2]4、Zr(TMHD)4、Zr(OiC3H7)3(TMTD)、Zr(OtBu)4或含Zr的化合物。利用载气例如氩气(Ar)将Zr源气体供应到反应室中，其中载气以约150sccm-250sccm的流量持续供应约0.1秒-10秒。
供应吹扫气体例如N2或Ar以清除未吸附的部分Zr源气体。吹扫气体以约200sccm-400sccm的流量持续供应约3秒-10秒。
Al源气体选自Al(CH3)3、Al(C2H5)3或含Al的化合物。利用载气例如氩气将Al源气体供应到反应室中。氩气以约20sccm-100sccm的流量持续供应约0.1秒-5秒。
再次供应吹扫气体例如N2或Ar以清除未反应的部分Al源气体。吹扫气体以约200sccm-400sccm的流量持续供应约3秒-10秒。
反应气体选自O3(浓度约100g/m3-500g/m3)、O2、O2等离子体、N2O、N2O等离子体或水蒸气。反应气体与Zr源气体和Al源气体反应，形成ZrxAlyOz介电层。反应气体以约100sccm-1000sccm的流量持续供应约3秒-10秒。
供应吹扫气体例如N2或Ar以清除残留在腔室中的未反应部分反应气体。吹扫气体以约50sccm-200sccm的流量持续供应约3秒-10秒。
重复实施上述ALD法单元循环直到ZrxAlyOz介电层达到约50-100的厚度。
在形成ZrxAlyOz介电层之后，在选自N2、H2、N2/H2、O2、O3和NH3的环境气体中实施退火过程。实施退火过程以使ZrxAlyOz介电层致密化；获得均匀的ZrxAlyOz介电层或使可引起漏电流的残留杂质挥发。还实施退火过程以减少其它介电层的表面粗糙度并去除微晶。
退火过程涉及等离子体退火过程、炉退火过程或RTP。等离子体退火过程在以下条件下实施约1-5分钟：以约100W-500W的射频(RF)功率产生等离子体；约0.1Torr-10Torr的压力；和约5sccm-5000sccm的所选环境气体。炉退火过程利用约5sccm-5000sccm的所选环境气体在约600℃-800℃下实施。RTP在约500℃-800℃的温度下、利用约5sccm-5000sccm的所选环境气体在腔室中实施，其中腔室保持有约700torr-约760torr的升压或约1torr-约100torr的降压。炉退火过程和RTP进一步增加ZrxAlyOz介电层的介电常数。
根据本发明的实施方案，ZrxAlyOz介电层被用作电容器的介电材料，并且这种方法在亚70nm级的DRAM电容器中实现了所需的电容量(例如约25fF/单元)、所需的漏电流(例如约0.5fF/单元或更低)和所需的击穿电压(例如约2.0V(1pA/单元时)或更高)。
通常，ZrO2薄层具有比Ta2O5薄层和HfO2薄层更高的带隙能(Eg)和介电常数(ε)。例如，ZrO2薄层具有约7.8eV的带隙能和约20-25的介电常数(ε)；Ta2O5薄层具有约4.5eV的带隙能和约25的介电常数；HfO2薄层具有约5.7eV的带隙能和约20的介电常数。Al2O3薄层具有约8.7eV的带隙能和约9的介电常数并且具有比HfO2薄层更好的热稳定性。基于这些事实，与单介电结构的电容器相比，ZrxAlyOz介电层可以改进漏电流和热稳定性方面的缺陷，这是由于ZrxAlyOz介电层具有ZrO2薄层和Al2O3薄层的特征。
结果，ZrxAlyOz介电层的等价氧化物层厚度可以减少至约12或更小。因此。具有ZrxAlyOz介电层的电容器可以在亚70nm级DRAM产品中获得约30fF/单元或更高的高电容量。而且，如上所述，根据本发明实施方案的电容器可以获得更低的漏电流和所需的击穿电压，因此能够大规模生产。
另外，由于ZrxAlyOz介电层具有比单介电层例如HfO2更好的热稳定性，因此在形成电容器之后的集成过程中实施的高热处理期间，电特性退化的可能性更小。因此，电容器的耐久性和可靠性可以在利用亚70nm半导体技术(例如金属互连技术)实现的下一代存储器件中得到改进。
本申请包含与韩国专利申请No.KR 2005-0114367相关的主题，该申请于2005年11月28日提交韩国专利局，其全部内容通过引用并入本文。
虽然已经相对于一些实施方案描述了本发明，但是可以在不偏离如所附权利要求中限定的本发明精神和范围的情况下做出各种变化和修改，这对本领域技术人员而言是显而易见的。

Claims (20)

1.一种用于制造半导体器件中电容器的方法，该方法包括：
在半导体衬底上形成底电极；
利用原子层沉积(ALD)法在底电极上形成ZrxAlyOz介电层，其中ZrxAlyOz介电层包含分别以预定摩尔分数x、y和z混合的锆(Zr）组分、铝(Al)组分和氧(O)组分；和
在ZrxAlyOz介电层上形成顶电极。
2.权利要求1的方法，其中ZrxAlyOz介电层中摩尔分数x、y和z的总和约为1，其中Zr组分摩尔分数(x)与Al组分摩尔分数(y)之比为约1∶1-10∶1。
3.权利要求1的方法，其中形成ZrxAlyOz介电层包括：
在底电极上吸附Zr源气体；
供应第一吹扫气体以清除未吸附的部分Zr源气体；
使Al源气体吸附到提供在目标物上的Zr源气体上；
供应第二吹扫气体以清除未吸附的部分Al源气体；
供应反应气体，使其与提供在目标物上的Zr和Al源气体反应，由此形成ZrxAlyOz介电层；和
供应第三吹扫气体以清除未反应的部分反应气体。
4.权利要求3的方法，其中Zr源气体包括选自ZrCl4、Zr[N(CH3)C2H5]4、Zr(O-tBu)4、Zr[N(CH3)2]4、Zr[N(C2H5)(CH3)]4、Zr[N(C2H5)2]4、Zr(TMHD)4、Zr(OiC3H7)3(TMTD)、Zr(OtBu)4和含Zr的化合物中的一种。
5.权利要求3的方法，其中Al源气体包括选自Al(CH3)3、Al(C2H5)3或含Al的化合物中的一种。
6.权利要求3的方法，其中反应气体包括选自浓度约100gm-3-500gm-3的O3、O2、O2等离子体、N2O、N2O等离子体和水蒸气中的一种，其中所选反应气体以约100sccm-约1000sccm的流量持续供应约3秒-约10秒。
7.权利要求3的方法，其中第一、第二和第三吹扫气体包括N2气和Ar气中的一种。
8.权利要求3的方法，其中ZrxAlyOz介电层形成约50-约100的厚度。
9.权利要求3的方法，其中ZrxAlyOz介电层在约200℃-约500℃的衬底温度和约0.1Torr-约1Torr的腔室压力的条件下形成。
10.权利要求3的方法，还包括在形成ZrxAlyOz介电层之后实施退火过程。
11.权利要求10的方法，其中利用在下列条件下实施约1-约5分钟的等离子体退火过程来进行所述退火过程：环境气体包括选自N2、H2、N2/H2、NH3、N2O、N2/O2、O2和O3中的一种并以约5sccm-约5000sccm的流量供应；约200℃-约500℃的温度；以约100W-约500W的射频功率产生的等离子体；和约0.1Torr-约1Torr的压力。
12.权利要求10的方法，其中利用在下列条件下实施的快速热处理来进行所述退火过程：约500℃-约800℃的温度；约700torr-约760torr的上升腔压和约1torr-约100torr的下降腔压之一；以及以约5sccm-约5000sccm的流量供应选自N2、H2、N2/H2、NH3、N2O、N2/O2、O2和O3中的气体。
13.权利要求10的方法，其中利用在下列条件下实施的炉退火过程来进行所述退火过程：以约5sccm-约5000sccm的流量供应选自N2、H2、N2/H2、NH3、N2O、N2/O2、O2和O3中的气体；和约600℃-约800℃的温度。
14.权利要求1的方法，其中底电极和顶电极包括选自TiN、TaN、W、WN、Ru、RuO2、Ir、IrO2和Pt中的一种。
15.权利要求1的方法，还包括在形成底电极之后，在选自N2、H2、N2/H2、O2、O3和NH3的环境气体中实施退火过程。
16.权利要求1的方法，还包括在形成顶电极之后，利用ALD法在顶电极上形成钝化层。
17.权利要求16的方法，其中钝化层形成约50-约200的厚度。
18.权利要求16的方法，其中钝化层包括氧化物基材料和金属基材料中的一种。
19.权利要求18的方法，其中氧化物基材料包括选自Al2O3、HfO2、Ta2O5、ZrO2、TiO2和La2O3中的一种。
20.权利要求18的方法，其中金属基材料包括TiN。
CNB2006101523079A 2005-11-28 2006-09-21 半导体器件中电容器的制造方法 Expired - Fee Related CN100514606C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050114367A KR100670747B1 (ko) 2005-11-28 2005-11-28 반도체소자의 캐패시터 제조 방법
KR1020050114367 2005-11-28

Publications (2)

Publication Number Publication Date
CN1976008A true CN1976008A (zh) 2007-06-06
CN100514606C CN100514606C (zh) 2009-07-15

Family

ID=38014072

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101523079A Expired - Fee Related CN100514606C (zh) 2005-11-28 2006-09-21 半导体器件中电容器的制造方法

Country Status (7)

Country Link
US (1) US7825043B2 (zh)
JP (1) JP5094057B2 (zh)
KR (1) KR100670747B1 (zh)
CN (1) CN100514606C (zh)
DE (1) DE102006030707B4 (zh)
IT (1) ITMI20061269A1 (zh)
TW (1) TWI322487B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107527806A (zh) * 2017-09-29 2017-12-29 睿力集成电路有限公司 介电薄膜、介电层结构及制作方法
CN112086456A (zh) * 2019-06-14 2020-12-15 三星电子株式会社 半导体存储器装置和制造该半导体存储器装置的方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8203176B2 (en) 2007-03-08 2012-06-19 Renesas Electronics Corporation Dielectric, capacitor using dielectric, semiconductor device using dielectric, and manufacturing method of dielectric
JP5133643B2 (ja) * 2007-09-28 2013-01-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
WO2009057589A1 (ja) * 2007-10-30 2009-05-07 Nec Corporation キャパシタとそれを有する半導体装置およびキャパシタの製造方法
JP5262233B2 (ja) * 2008-03-27 2013-08-14 日本電気株式会社 窒化ジルコニウム界面層を有するキャパシター構造
US7704884B2 (en) 2008-04-11 2010-04-27 Micron Technology, Inc. Semiconductor processing methods
US7820506B2 (en) * 2008-10-15 2010-10-26 Micron Technology, Inc. Capacitors, dielectric structures, and methods of forming dielectric structures
JP5504663B2 (ja) * 2009-03-25 2014-05-28 富士通セミコンダクター株式会社 半導体装置の製造方法
WO2011074604A1 (ja) * 2009-12-18 2011-06-23 株式会社日立国際電気 半導体装置の製造方法、基板処理装置及び半導体装置
JP5587716B2 (ja) 2010-09-27 2014-09-10 マイクロンメモリジャパン株式会社 半導体装置及びその製造方法、並びに吸着サイト・ブロッキング原子層堆積法
JP2014017354A (ja) * 2012-07-09 2014-01-30 Tokyo Electron Ltd 成膜方法
JP2014218691A (ja) * 2013-05-07 2014-11-20 エア・ウォーター株式会社 層状構造体の製造方法
KR102364708B1 (ko) * 2017-07-12 2022-02-21 삼성디스플레이 주식회사 표시 장치의 제조 방법
KR20210012808A (ko) 2019-07-26 2021-02-03 삼성전자주식회사 2종 물질 산화막의 형성 방법, 반도체 소자의 제조 방법, 유전막 형성 방법, 및 반도체 소자
US20220216297A1 (en) * 2021-01-05 2022-07-07 Changxin Memory Technologies, Inc. Electrode layer, capacitor and methods for electrode layer and capacitor manufacture
WO2023163499A1 (ko) * 2022-02-24 2023-08-31 주성엔지니어링(주) 유전막과 그를 포함한 커패시터 및 그들의 제조 방법

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297539B1 (en) * 1999-07-19 2001-10-02 Sharp Laboratories Of America, Inc. Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same
KR100363084B1 (ko) * 1999-10-19 2002-11-30 삼성전자 주식회사 박막 구조를 위한 다중막을 포함하는 커패시터 및 그 제조 방법
US6407435B1 (en) 2000-02-11 2002-06-18 Sharp Laboratories Of America, Inc. Multilayer dielectric stack and method
US6984591B1 (en) 2000-04-20 2006-01-10 International Business Machines Corporation Precursor source mixtures
DE10034003A1 (de) 2000-07-07 2002-01-24 Infineon Technologies Ag Grabenkondensator mit Isolationskragen und entsprechendes Herstellungsverfahren
KR100663341B1 (ko) 2000-08-11 2007-01-02 삼성전자주식회사 원자층 증착 캐패시터 제조방법 및 장치
US6664186B1 (en) 2000-09-29 2003-12-16 International Business Machines Corporation Method of film deposition, and fabrication of structures
US6660660B2 (en) 2000-10-10 2003-12-09 Asm International, Nv. Methods for making a dielectric stack in an integrated circuit
US6486080B2 (en) * 2000-11-30 2002-11-26 Chartered Semiconductor Manufacturing Ltd. Method to form zirconium oxide and hafnium oxide for high dielectric constant materials
KR20020049875A (ko) 2000-12-20 2002-06-26 윤종용 반도체 메모리 소자의 강유전체 커패시터 및 그 제조방법
WO2002059956A1 (fr) * 2001-01-25 2002-08-01 Tokyo Electron Limited Procede de fabrication d'un materiau de dispositif electronique
JP2002222934A (ja) 2001-01-29 2002-08-09 Nec Corp 半導体装置およびその製造方法
US6858865B2 (en) 2001-02-23 2005-02-22 Micron Technology, Inc. Doped aluminum oxide dielectrics
US6486057B1 (en) * 2001-04-12 2002-11-26 National Science Council Process for preparing Cu damascene interconnection
JP2002314072A (ja) 2001-04-19 2002-10-25 Nec Corp 高誘電体薄膜を備えた半導体装置及びその製造方法並びに誘電体膜の成膜装置
US20020168840A1 (en) * 2001-05-11 2002-11-14 Applied Materials, Inc. Deposition of tungsten silicide films
JP3863391B2 (ja) 2001-06-13 2006-12-27 Ｎｅｃエレクトロニクス株式会社 半導体装置
US6797525B2 (en) 2002-05-22 2004-09-28 Agere Systems Inc. Fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant, annealed with a buffered anneal process
KR100476926B1 (ko) 2002-07-02 2005-03-17 삼성전자주식회사 반도체 소자의 듀얼 게이트 형성방법
KR100542736B1 (ko) * 2002-08-17 2006-01-11 삼성전자주식회사 원자층 증착법을 이용한 산화막의 형성방법 및 이를이용한 반도체 장치의 캐패시터 형성방법
TWI223329B (en) 2002-09-10 2004-11-01 Samsung Electronics Co Ltd Method for forming high dielectric layer in semiconductor device
JP2004111447A (ja) 2002-09-13 2004-04-08 Handotai Rikougaku Kenkyu Center:Kk 半導体装置及びその製造方法
US6940117B2 (en) 2002-12-03 2005-09-06 International Business Machines Corporation Prevention of Ta2O5 mim cap shorting in the beol anneal cycles
US6753224B1 (en) 2002-12-19 2004-06-22 Taiwan Semiconductor Manufacturing Company Layer of high-k inter-poly dielectric
JP4290421B2 (ja) 2002-12-27 2009-07-08 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
KR20040059536A (ko) 2002-12-27 2004-07-06 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조방법
KR100493040B1 (ko) 2002-12-30 2005-06-07 삼성전자주식회사 반도체 소자의 커패시터 및 그 제조방법
EP1591527B1 (en) 2003-01-23 2015-08-26 Ono Pharmaceutical Co., Ltd. Substance specific to human pd-1
US7135369B2 (en) * 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US7092234B2 (en) 2003-05-20 2006-08-15 Micron Technology, Inc. DRAM cells and electronic systems
KR100555543B1 (ko) 2003-06-24 2006-03-03 삼성전자주식회사 원자층 증착법에 의한 고유전막 형성 방법 및 그고유전막을 갖는 커패시터의 제조 방법
US20050054156A1 (en) 2003-09-10 2005-03-10 International Business Machines Corporation Capacitor and fabrication method using ultra-high vacuum cvd of silicon nitride
KR20050028749A (ko) 2003-09-19 2005-03-23 삼성전자주식회사 다층 구조의 커패시터들 갖는 반도체 장치
KR20050075790A (ko) 2004-01-16 2005-07-22 (주)바이오빈 키토산과 게장이 혼합된 된장의 제조방법
KR100542675B1 (ko) 2004-02-06 2006-01-11 허차순 합성수지 하수관용 고무패킹 소켓 성형장치
US20050196917A1 (en) * 2004-03-03 2005-09-08 Jingyu Lian Method for forming a (111) oriented BSTO thin film layer for high dielectric constant capacitors
KR100587071B1 (ko) 2004-03-30 2006-06-07 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
KR100579869B1 (ko) 2004-04-21 2006-05-22 김상국 다중구동원을 구비한 하부 방류형 어도 겸용 가동보 수문및 그 구동방법
KR20050103065A (ko) 2004-04-24 2005-10-27 삼성전자주식회사 Ｕｍｔｓ 망에서의 통합된 ｓｇｓｎ 및 ｇｇｓｎ에서의터널 설정 방법 및 장치
KR20050123428A (ko) 2004-06-25 2005-12-29 엘지전자 주식회사 컨트롤 패널과 메탈 시트의 결합구조
US7492006B2 (en) * 2004-08-30 2009-02-17 Samsung Electronics Co., Ltd. Semiconductor transistors having surface insulation layers and methods of fabricating such transistors
KR100587086B1 (ko) 2004-10-29 2006-06-08 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
KR100713906B1 (ko) 2004-11-08 2007-05-07 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
DE102005053322A1 (de) 2004-11-08 2006-06-08 Hynix Semiconductor Inc., Ichon Kondensator mit Zirkondioxid und Verfahren zur Herstellung desselben
KR20060072338A (ko) 2004-12-23 2006-06-28 주식회사 하이닉스반도체 유전체막 형성방법 및 이를 이용한 반도체 소자의캐패시터 형성방법
KR100772099B1 (ko) 2005-06-28 2007-11-01 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
KR100744026B1 (ko) 2005-06-28 2007-07-30 주식회사 하이닉스반도체 플래시 메모리 소자의 제조방법
KR100670726B1 (ko) 2005-06-29 2007-01-17 주식회사 하이닉스반도체 반도체 소자의 캐패시터 및 그 형성방법
KR100596805B1 (ko) 2005-06-30 2006-07-04 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
KR100717813B1 (ko) 2005-06-30 2007-05-11 주식회사 하이닉스반도체 나노믹스드 유전막을 갖는 캐패시터 및 그의 제조 방법
KR100772101B1 (ko) 2005-06-30 2007-11-01 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
KR100655139B1 (ko) 2005-11-03 2006-12-08 주식회사 하이닉스반도체 캐패시터 제조 방법
KR100655140B1 (ko) 2005-11-10 2006-12-08 주식회사 하이닉스반도체 캐패시터 및 그 제조 방법
KR100656283B1 (ko) 2005-12-14 2006-12-11 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조 방법
KR100672766B1 (ko) 2005-12-27 2007-01-22 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조 방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107527806A (zh) * 2017-09-29 2017-12-29 睿力集成电路有限公司 介电薄膜、介电层结构及制作方法
CN112086456A (zh) * 2019-06-14 2020-12-15 三星电子株式会社 半导体存储器装置和制造该半导体存储器装置的方法

Also Published As

Publication number Publication date
JP5094057B2 (ja) 2012-12-12
DE102006030707A1 (de) 2007-05-31
KR100670747B1 (ko) 2007-01-17
DE102006030707B4 (de) 2011-06-22
TW200721389A (en) 2007-06-01
US20070122967A1 (en) 2007-05-31
ITMI20061269A1 (it) 2007-05-29
CN100514606C (zh) 2009-07-15
US7825043B2 (en) 2010-11-02
JP2007150242A (ja) 2007-06-14
TWI322487B (en) 2010-03-21

Similar Documents

Publication Publication Date Title
CN100514606C (zh) 半导体器件中电容器的制造方法
CN100481461C (zh) 具有纳米复合电介质结构的电容器及其制造方法
CN1270352C (zh) 形成方法以及包含钌和包含钨层的集成电路结构
CN1790674B (zh) 具有氧化锆的电容器及其制造方法
US7297591B2 (en) Method for manufacturing capacitor of semiconductor device
US7446053B2 (en) Capacitor with nano-composite dielectric layer and method for fabricating the same
CN1187810C (zh) 半导体器件的电容器的制造方法
KR20040093255A (ko) Ａｌｄ에 의한 금속 박막 형성 방법, 란탄 산화막 형성방법 및 반도체 소자의 고유전막 형성 방법
US7499259B2 (en) Capacitor with hafnium, lanthanum and oxygen mixed dielectric and method for fabricating the same
US7531422B2 (en) Method for fabricating capacitor in semiconductor device using hafnium terbium oxide dielectric layer
US20020160565A1 (en) Capacitor for semiconductor devices and a method of fabricating such capacitors
KR100772099B1 (ko) 반도체 소자의 캐패시터 형성방법
KR100716642B1 (ko) 캐패시터의 유전막 및 그의 제조방법
KR100713906B1 (ko) 반도체 소자의 캐패시터 형성방법
KR100596805B1 (ko) 반도체 소자의 캐패시터 형성방법
KR20070106289A (ko) 이트륨티타늄산화막을 구비한 반도체소자의 캐패시터 및 그제조 방법
KR20070002579A (ko) 반도체 소자의 캐패시터 형성방법
KR20080062726A (ko) 높은 커패시턴스를 갖는 금속-절연체-금속 커패시터 및 그제조방법
KR20040060416A (ko) 반도체소자의 캐패시터 제조방법
KR100713922B1 (ko) 반도체 소자의 캐패시터 형성방법
KR20080032599A (ko) 캐패시터 유전막 제조방법
KR20070106290A (ko) 니오비윰이트륨산화막을 구비한 반도체소자의 캐패시터 및그 제조 방법
KR20080062742A (ko) 높은 커패시턴스를 갖는 금속-절연체-금속 커패시터 및 그제조방법
KR20080062735A (ko) 높은 커패시턴스를 갖는 금속-절연체-금속 커패시터 및 그제조방법
KR20070000708A (ko) 반도체 소자의 캐패시터 형성방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090715

Termination date: 20130921