JP2005503660A - フリップチップ用の自己平面保持バンプの形状 - Google Patents

フリップチップ用の自己平面保持バンプの形状 Download PDF

Info

Publication number
JP2005503660A
JP2005503660A JP2002568401A JP2002568401A JP2005503660A JP 2005503660 A JP2005503660 A JP 2005503660A JP 2002568401 A JP2002568401 A JP 2002568401A JP 2002568401 A JP2002568401 A JP 2002568401A JP 2005503660 A JP2005503660 A JP 2005503660A
Authority
JP
Japan
Prior art keywords
bump
leg
base
stud
structure according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002568401A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005503660A5 (enExample
Inventor
ヤンドー クゥエオン
ラジェンドラ ペンデス
ナジール アーマッド
キョンムン キム
Original Assignee
チップパック,インク.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by チップパック,インク. filed Critical チップパック,インク.
Publication of JP2005503660A publication Critical patent/JP2005503660A/ja
Publication of JP2005503660A5 publication Critical patent/JP2005503660A5/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/11831Reworking, e.g. shaping involving a chemical process, e.g. etching the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/1184Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
JP2002568401A 2001-02-27 2002-02-25 フリップチップ用の自己平面保持バンプの形状 Pending JP2005503660A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US27224001P 2001-02-27 2001-02-27
US10/080,384 US6940178B2 (en) 2001-02-27 2002-02-22 Self-coplanarity bumping shape for flip chip
PCT/US2002/005394 WO2002069372A2 (en) 2001-02-27 2002-02-25 Self-coplanarity bumping shape for flip chip

Publications (2)

Publication Number Publication Date
JP2005503660A true JP2005503660A (ja) 2005-02-03
JP2005503660A5 JP2005503660A5 (enExample) 2005-12-22

Family

ID=26763444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002568401A Pending JP2005503660A (ja) 2001-02-27 2002-02-25 フリップチップ用の自己平面保持バンプの形状

Country Status (7)

Country Link
US (3) US6940178B2 (enExample)
EP (1) EP1382057A2 (enExample)
JP (1) JP2005503660A (enExample)
KR (1) KR20030080033A (enExample)
AU (1) AU2002244124A1 (enExample)
TW (1) TWI279881B (enExample)
WO (1) WO2002069372A2 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009041044A1 (ja) * 2007-09-26 2009-04-02 Sanyo Electric Co., Ltd. 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP2011218682A (ja) * 2010-04-09 2011-11-04 Konica Minolta Holdings Inc インクジェットヘッド、インクジェットヘッドの製造方法及びインクジェット描画装置
JP2014132635A (ja) * 2012-12-05 2014-07-17 Murata Mfg Co Ltd バンプ付き電子部品及びバンプ付き電子部品の製造方法

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW584950B (en) 2001-12-31 2004-04-21 Megic Corp Chip packaging structure and process thereof
TW517361B (en) * 2001-12-31 2003-01-11 Megic Corp Chip package structure and its manufacture process
US6673698B1 (en) 2002-01-19 2004-01-06 Megic Corporation Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
TW544882B (en) 2001-12-31 2003-08-01 Megic Corp Chip package structure and process thereof
TW503496B (en) 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6959134B2 (en) * 2003-06-30 2005-10-25 Intel Corporation Measuring the position of passively aligned optical components
JP4083638B2 (ja) * 2003-07-30 2008-04-30 東北パイオニア株式会社 フレキシブル配線基板、半導体チップ実装フレキシブル配線基板、表示装置、半導体チップ実装方法
TWI273664B (en) * 2004-03-26 2007-02-11 Advanced Semiconductor Eng Bumping process, bump structure, packaging process and package structure
KR100597993B1 (ko) * 2004-04-08 2006-07-10 주식회사 네패스 반도체 패키지용 범프, 그 범프를 적용한 반도체 패키지 및 제조방법
JP4768343B2 (ja) * 2005-07-27 2011-09-07 株式会社デンソー 半導体素子の実装方法
KR20080037681A (ko) * 2005-08-23 2008-04-30 로무 가부시키가이샤 반도체 칩 및 그 제조 방법 및 반도체 장치
US9847309B2 (en) * 2006-09-22 2017-12-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
US8133762B2 (en) 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
US8193034B2 (en) * 2006-11-10 2012-06-05 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure using stud bumps
US8174119B2 (en) 2006-11-10 2012-05-08 Stats Chippac, Ltd. Semiconductor package with embedded die
US20090014852A1 (en) * 2007-07-11 2009-01-15 Hsin-Hui Lee Flip-Chip Packaging with Stud Bumps
JP5058714B2 (ja) * 2007-08-21 2012-10-24 スパンション エルエルシー 半導体装置及びその製造方法
FR2954588B1 (fr) * 2009-12-23 2014-07-25 Commissariat Energie Atomique Procede d'assemblage d'au moins une puce avec un element filaire, puce electronique a element de liaison deformable, procede de fabrication d'une pluralite de puces, et assemblage d'au moins une puce avec un element filaire
JP5481249B2 (ja) * 2010-03-26 2014-04-23 富士通株式会社 半導体装置及びその製造方法
US9142533B2 (en) * 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8657596B2 (en) 2011-04-26 2014-02-25 The Procter & Gamble Company Method and apparatus for deforming a web
US9324667B2 (en) 2012-01-13 2016-04-26 Freescale Semiconductor, Inc. Semiconductor devices with compliant interconnects
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
JP6154995B2 (ja) * 2012-06-20 2017-06-28 新光電気工業株式会社 半導体装置及び配線基板、並びにそれらの製造方法
US8970035B2 (en) * 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
CN104798187B (zh) * 2012-11-16 2017-07-25 夏普株式会社 倒装接合方法、和特征在于包含该倒装接合方法的固体摄像装置的制造方法
US9385098B2 (en) * 2012-11-21 2016-07-05 Nvidia Corporation Variable-size solder bump structures for integrated circuit packaging
DE102013104407B4 (de) 2013-04-30 2020-06-18 Tdk Corporation Auf Waferlevel herstellbares Bauelement und Verfahren zur Herstellung
US20150279793A1 (en) * 2014-03-27 2015-10-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9859200B2 (en) 2014-12-29 2018-01-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof
JP2019060817A (ja) * 2017-09-28 2019-04-18 日本特殊陶業株式会社 電子部品検査装置用配線基板
KR102574452B1 (ko) 2018-07-03 2023-09-04 삼성전자 주식회사 반도체 칩 및 이를 포함하는 반도체 패키지
KR102724556B1 (ko) 2019-06-04 2024-10-30 삼성전자주식회사 본딩 장치 및 그를 포함하는 반도체 패키지의 제조 설비

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4000842A (en) * 1975-06-02 1977-01-04 National Semiconductor Corporation Copper-to-gold thermal compression gang bonding of interconnect leads to semiconductive devices
JPS54105774A (en) 1978-02-08 1979-08-20 Hitachi Ltd Method of forming pattern on thin film hybrid integrated circuit
JPH07112041B2 (ja) 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
JPH02110950A (ja) 1988-10-19 1990-04-24 Matsushita Electric Ind Co Ltd 半導体装置
JP2836027B2 (ja) 1989-12-18 1998-12-14 カシオ計算機株式会社 半田バンプの形成方法
JPH03209725A (ja) 1990-01-11 1991-09-12 Matsushita Electric Ind Co Ltd 半導体装置の突起電極形成方法
JPH0429338A (ja) 1990-05-24 1992-01-31 Nippon Mektron Ltd Icの搭載用回路基板及びその搭載方法
US5865365A (en) 1991-02-19 1999-02-02 Hitachi, Ltd. Method of fabricating an electronic circuit device
US5686317A (en) 1991-06-04 1997-11-11 Micron Technology, Inc. Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die
JP3225062B2 (ja) 1991-08-05 2001-11-05 ローム株式会社 熱硬化性樹脂シート及びそれを用いた半導体素子の実装方法
JPH05166811A (ja) 1991-12-19 1993-07-02 Fujitsu General Ltd 半田バンプの形成方法
US5346857A (en) 1992-09-28 1994-09-13 Motorola, Inc. Method for forming a flip-chip bond from a gold-tin eutectic
US5914614A (en) * 1996-03-12 1999-06-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US5386624A (en) 1993-07-06 1995-02-07 Motorola, Inc. Method for underencapsulating components on circuit supporting substrates
US5592736A (en) 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
JPH07122562A (ja) 1993-10-20 1995-05-12 Tanaka Denshi Kogyo Kk バンプ形成方法及びワイヤボンディング方法並びにバンプ構造及びワイヤボンディング構造
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
JPH07142490A (ja) 1993-11-17 1995-06-02 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2664878B2 (ja) 1994-01-31 1997-10-22 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体チップパッケージおよびその製造方法
DE19524739A1 (de) * 1994-11-17 1996-05-23 Fraunhofer Ges Forschung Kernmetall-Lothöcker für die Flip-Chip-Technik
JP2735022B2 (ja) 1995-03-22 1998-04-02 日本電気株式会社 バンプ製造方法
JP3209875B2 (ja) 1995-03-23 2001-09-17 株式会社日立製作所 基板の製造方法及び基板
JPH08288424A (ja) 1995-04-18 1996-11-01 Nec Corp 半導体装置
JP2796070B2 (ja) 1995-04-28 1998-09-10 松下電器産業株式会社 プローブカードの製造方法
US5874780A (en) 1995-07-27 1999-02-23 Nec Corporation Method of mounting a semiconductor device to a substrate and a mounted structure
DE19527661C2 (de) 1995-07-28 1998-02-19 Optrex Europ Gmbh Elektrische Leiter aufweisender Träger mit einem elektronischen Bauteil und Verfahen zum Kontaktieren von Leitern eines Substrates mit Kontaktwarzen eines elektronischen Bauteils
KR100186752B1 (ko) * 1995-09-04 1999-04-15 황인길 반도체 칩 본딩방법
US5889326A (en) * 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JP2951882B2 (ja) * 1996-03-06 1999-09-20 松下電器産業株式会社 半導体装置の製造方法及びこれを用いて製造した半導体装置
JP2828021B2 (ja) 1996-04-22 1998-11-25 日本電気株式会社 ベアチップ実装構造及び製造方法
JP2842378B2 (ja) * 1996-05-31 1999-01-06 日本電気株式会社 電子回路基板の高密度実装構造
JP3326466B2 (ja) 1996-10-15 2002-09-24 松下電器産業株式会社 半導体素子の電極形成方法
JP2924830B2 (ja) 1996-11-15 1999-07-26 日本電気株式会社 半導体装置及びその製造方法
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
US5931371A (en) 1997-01-16 1999-08-03 Ford Motor Company Standoff controlled interconnection
JP3267181B2 (ja) 1997-01-28 2002-03-18 松下電器産業株式会社 金属突起電極形成装置及び金属突起電極形成方法
JP3070514B2 (ja) 1997-04-28 2000-07-31 日本電気株式会社 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造
JP3564944B2 (ja) 1997-05-22 2004-09-15 松下電器産業株式会社 チップの実装方法
US6337522B1 (en) 1997-07-10 2002-01-08 International Business Machines Corporation Structure employing electrically conductive adhesives
JP3420917B2 (ja) * 1997-09-08 2003-06-30 富士通株式会社 半導体装置
JP2997231B2 (ja) * 1997-09-12 2000-01-11 富士通株式会社 マルチ半導体ベアチップ実装モジュールの製造方法
SG71734A1 (en) 1997-11-21 2000-04-18 Inst Materials Research & Eng Area array stud bump flip chip and assembly process
US6037192A (en) 1998-01-22 2000-03-14 Nortel Networks Corporation Process of assembling an integrated circuit and a terminal substrate using solder reflow and adhesive cure
US5953814A (en) 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability
JP3975569B2 (ja) * 1998-09-01 2007-09-12 ソニー株式会社 実装基板及びその製造方法
JP2000124348A (ja) 1998-10-14 2000-04-28 Oki Electric Ind Co Ltd Vlsiパッケージ
US6376352B1 (en) * 1998-11-05 2002-04-23 Texas Instruments Incorporated Stud-cone bump for probe tips used in known good die carriers
JP3209725B2 (ja) 1999-02-15 2001-09-17 株式会社シンワコーポレーション 梱包輸送容器の製品受け台
SG88747A1 (en) 1999-03-01 2002-05-21 Motorola Inc A method and machine for underfilling an assembly to form a semiconductor package
JP2000299338A (ja) 1999-04-14 2000-10-24 Sony Corp 突起電極を有するベアチップic及び突起電極の形成方法
US6173887B1 (en) 1999-06-24 2001-01-16 International Business Machines Corporation Method of making electrically conductive contacts on substrates
US6372622B1 (en) * 1999-10-26 2002-04-16 Motorola, Inc. Fine pitch bumping with improved device standoff and bump volume
JP3672297B2 (ja) * 1999-11-10 2005-07-20 セイコーインスツル株式会社 半導体装置の製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009041044A1 (ja) * 2007-09-26 2009-04-02 Sanyo Electric Co., Ltd. 半導体モジュール、半導体モジュールの製造方法および携帯機器
JP2009081310A (ja) * 2007-09-26 2009-04-16 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法および携帯機器
US8362611B2 (en) 2007-09-26 2013-01-29 Sanyo Electric Co., Ltd. Semiconductor module, method for manufacturing semiconductor module, and portable device
JP2011218682A (ja) * 2010-04-09 2011-11-04 Konica Minolta Holdings Inc インクジェットヘッド、インクジェットヘッドの製造方法及びインクジェット描画装置
JP2014132635A (ja) * 2012-12-05 2014-07-17 Murata Mfg Co Ltd バンプ付き電子部品及びバンプ付き電子部品の製造方法

Also Published As

Publication number Publication date
EP1382057A2 (en) 2004-01-21
WO2002069372A2 (en) 2002-09-06
WO2002069372A8 (en) 2003-02-20
TWI279881B (en) 2007-04-21
US20020151228A1 (en) 2002-10-17
US7211901B2 (en) 2007-05-01
US7407877B2 (en) 2008-08-05
US20050221535A1 (en) 2005-10-06
WO2002069372A3 (en) 2003-10-30
KR20030080033A (ko) 2003-10-10
AU2002244124A1 (en) 2002-09-12
US6940178B2 (en) 2005-09-06
US20050218515A1 (en) 2005-10-06

Similar Documents

Publication Publication Date Title
JP2005503660A (ja) フリップチップ用の自己平面保持バンプの形状
US20080111233A1 (en) Semiconductor package with embedded die
US7064425B2 (en) Semiconductor device circuit board, and electronic equipment
US20110045641A1 (en) Semiconductor Device Having Solder-Free Gold Bump Contacts for Stability in Repeated Temperature Cycles
JP2005503660A5 (enExample)
JP2738568B2 (ja) 半導体チップモジュール
TWI546911B (zh) 封裝結構及封裝方法
US20070222072A1 (en) Chip package and fabricating method thereof
US6612024B1 (en) Method of mounting a device to a mounting substrate
CN102473591B (zh) 互连封装结构及制造和使用该互连封装结构的方法
JP2002324821A (ja) 電子部品の圧着装置及び圧着方法
JP3965354B2 (ja) 素子パッケージ及びその製造方法
JP4374040B2 (ja) 半導体製造装置
TW200532751A (en) Semiconductor device and multilayer substrate therefor
US20100269333A1 (en) Method for Mounting Flip Chip and Substrate Used Therein
JP4318893B2 (ja) 半導体装置及び半導体装置の製造方法
JP4729438B2 (ja) 半導体装置、およびその製造方法
JPH11204572A (ja) 半導体装置の実装構造体及びその製造方法
TWI541920B (zh) 打線結構之製法
JP2002299374A (ja) 半導体装置及びその製造方法
JP2002076048A (ja) フリップチップ接続によるバンプの配置方法
US20040203187A1 (en) Method for manufacturing semiconductor wafer
JP2004014637A (ja) 半導体装置及びワイヤボンディング方法
JP2000150556A (ja) バンプ電極形成方法
TW200933755A (en) Chip package process and structure thereof

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050223

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050223

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070824

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071106

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071130

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080226

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080304

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080328

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080404

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080430

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080509

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080530

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080704