JP4768343B2 - 半導体素子の実装方法 - Google Patents
半導体素子の実装方法 Download PDFInfo
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- JP4768343B2 JP4768343B2 JP2005216944A JP2005216944A JP4768343B2 JP 4768343 B2 JP4768343 B2 JP 4768343B2 JP 2005216944 A JP2005216944 A JP 2005216944A JP 2005216944 A JP2005216944 A JP 2005216944A JP 4768343 B2 JP4768343 B2 JP 4768343B2
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- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
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Description
図1は、本発明の第1実施形態に係る半導体素子の実装構造の概略断面構成を示す図である。基板10は、たとえば一般的なシリコンIC基板であり、半導体プロセスによって図示しないトランジスタ素子などが形成されたものである。
図6は、本発明の第2実施形態に係る半導体素子の実装方法を示す概略断面図である。本実施形態は、上記第1実施形態において、さらに樹脂部材40を付加した形で超音波接合を行うものである。なお、図6では、ステージ100およびツール110は省略してある。
なお、上述したように、バンプの超音波接合は、ツール110によって超音波を印加し両バンプ31、32を金属接合させるものであるが、可能ならば、上記実施形態において、両バンプ31、32の接合が完了した瞬間に、ツール110による超音波の印加を停止するか、もしくは、低減するようにしてもよい。
20…半導体素子、21…半導体素子の一面、31…第1のバンプ、
31a第1のバンプの接触面、32…第2のバンプ、
32a…第2のバンプの先端面、40…樹脂部材、
d1…第1のバンプの接触面の径、d2…第2のバンプの先端面の径。
Claims (3)
- 一面(11)側にアルミニウムを主成分とするパッド(13)を有し、このパッド(13)の表面に金を主成分とする第1のバンプ(31)を備える基板(10)と、一面(21)側に金を主成分とする第2のバンプ(32)を有する半導体素子(20)とを用意し、
前記基板(10)の一面(11)上に、前記半導体素子(20)の一面(21)を対向させ前記第1のバンプ(31)と前記第2のバンプ(32)とを接触させた状態で、これら両バンプ(31、32)に超音波を印加して超音波接合を行う半導体素子の実装方法において、
前記基板(10)は、前記第1のバンプ(31)との間に補強層(200)を有さない前記パッド(13)の下地としてシリコン酸化膜系絶縁層(12)を有するものであり、
前記第1のバンプ(31)として、前記第2のバンプ(32)の先端面(32a)が接触する接触面(31a)の面積が前記第2のパンプ(32)の先端面(32a)の面積よりも大きいものを用いて、前記両バンプ(31、32)の接触および超音波接合を行うことを特徴とする半導体素子の実装方法。 - 前記第2のバンプ(32)と接触する前に、前記第1のバンプ(31)における前記接触面(31a)を、塑性変形により平坦化することを特徴とする請求項1に記載の半導体素子の実装方法。
- 前記第1のバンプ(31)の前記接触面(31a)の面積は、前記第2のパンプ(32)の先端面(32a)の面積よりも1.4倍以上大きいことを特徴とする請求項1または2に記載の半導体素子の実装方法。
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US11672158B2 (en) | 2019-04-01 | 2023-06-06 | Samsung Display Co., Ltd. | Display device and manufacturing method thereof |
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US20080116552A1 (en) * | 2006-11-17 | 2008-05-22 | James Rose | Electronic System With Lead Free Interconnections And Method of Fabrication |
KR101025349B1 (ko) | 2007-07-25 | 2011-03-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그의 제조 방법 |
US9142533B2 (en) | 2010-05-20 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate interconnections having different sizes |
JP5645592B2 (ja) | 2010-10-21 | 2014-12-24 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US9646923B2 (en) | 2012-04-17 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices |
US9425136B2 (en) | 2012-04-17 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conical-shaped or tier-shaped pillar connections |
US9299674B2 (en) | 2012-04-18 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace interconnect |
US9111817B2 (en) * | 2012-09-18 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structure and method of forming same |
WO2014045828A1 (ja) * | 2012-09-24 | 2014-03-27 | 独立行政法人産業技術総合研究所 | 半導体装置の製造方法、及び半導体製造装置 |
US9780065B2 (en) * | 2013-10-08 | 2017-10-03 | Kulicke And Soffa Industries, Inc. | Systems and methods for bonding semiconductor elements |
US9136240B2 (en) | 2013-10-08 | 2015-09-15 | Kulicke And Soffa Industries, Inc. | Systems and methods for bonding semiconductor elements |
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JPH11121458A (ja) * | 1997-10-21 | 1999-04-30 | Nec Kyushu Ltd | 半導体装置 |
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JP2000311921A (ja) * | 1999-04-27 | 2000-11-07 | Sony Corp | 半導体装置およびその製造方法 |
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DE10163799B4 (de) * | 2000-12-28 | 2006-11-23 | Matsushita Electric Works, Ltd., Kadoma | Halbleiterchip-Aufbausubstrat und Verfahren zum Herstellen eines solchen Aufbausubstrates |
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US11672158B2 (en) | 2019-04-01 | 2023-06-06 | Samsung Display Co., Ltd. | Display device and manufacturing method thereof |
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