WO2014045828A1 - 半導体装置の製造方法、及び半導体製造装置 - Google Patents
半導体装置の製造方法、及び半導体製造装置 Download PDFInfo
- Publication number
- WO2014045828A1 WO2014045828A1 PCT/JP2013/073205 JP2013073205W WO2014045828A1 WO 2014045828 A1 WO2014045828 A1 WO 2014045828A1 JP 2013073205 W JP2013073205 W JP 2013073205W WO 2014045828 A1 WO2014045828 A1 WO 2014045828A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- substrate
- semiconductor chip
- manufacturing
- semiconductor
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/10—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating making use of vibrations, e.g. ultrasonic welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/0347—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11472—Profile of the lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13012—Shape in top view
- H01L2224/13014—Shape in top view being circular or elliptic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13017—Shape in side view being non uniform along the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/1356—Disposition
- H01L2224/13562—On the entire exposed surface of the core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/1357—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/13599—Material
- H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75343—Means for applying energy, e.g. heating means by means of pressure by ultrasonic vibrations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75743—Suction holding means
- H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75753—Means for optical alignment, e.g. sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/81399—Material
- H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/81444—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/81895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/37—Effects of the manufacturing process
- H01L2924/37001—Yield
Definitions
- the present invention relates to a method for manufacturing a semiconductor device formed by connecting a semiconductor chip and a substrate, or between semiconductor chips, and a semiconductor manufacturing apparatus.
- connection structure between a semiconductor chip and a substrate, or between semiconductor chips a structure in which a semiconductor chip is mounted face-down on a wiring substrate or another semiconductor chip and both electrodes are connected via bump electrodes is known. Yes.
- Patent Document 1 describes forming a conical recess on the inner surface on one electrode.
- the bump electrode is guided while sliding on the inner side surface of the concave portion in the process of approaching both electrodes. .
- the central axis of the bump electrode and the central axis of the concave portion can be easily matched, and high-precision alignment can be realized.
- the present invention has been made in view of such problems, and its purpose is to firmly bond the electrode of the semiconductor chip and the electrode of the substrate or the like at a relatively low temperature while performing alignment with high accuracy. It is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus.
- a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device in which a semiconductor chip and a substrate or semiconductor chips are connected to each other.
- the first electrode and the second electrode are pressurized in a direction to bring them close to each other, so that the central axis of the first electrode and the central axis of the recess are aligned.
- a pressurizing step, and an ultrasonic bonding step in which at least one of the first electrode and the second electrode is vibrated by ultrasonic waves to bond the first electrode and the second electrode.
- a semiconductor manufacturing apparatus for connecting a semiconductor chip and a substrate or between semiconductor chips by the above manufacturing method.
- a semiconductor manufacturing apparatus for manufacturing a semiconductor device in which a semiconductor chip and a substrate or semiconductor chips are connected to each other, and the first semiconductor chip or the substrate protrudes in a substantially conical shape.
- One electrode is formed, and the other semiconductor chip or substrate is provided with a second electrode having a concave portion with an inner side surface of a substantially pyramid shape or a prism shape, and the first electrode is the same as the second electrode.
- a pressurizing device that pressurizes the first electrode and the second electrode in a direction approaching each other in a state of being inserted into the recess, and makes the center axis of the first electrode coincide with the center axis of the recess;
- a semiconductor manufacturing apparatus comprising: an ultrasonic device that vibrates at least one of the first electrode and the second electrode with ultrasonic waves.
- FIG. 20 is a perspective view illustrating an appearance of a pad electrode having a shape different from that of FIG. 19. It is the figure which showed typically the structure of the semiconductor manufacturing apparatus which concerns on this invention.
- a method for manufacturing a semiconductor device includes a bump forming step of forming a first electrode protruding in a substantially conical shape on one semiconductor chip or substrate, and an inner surface on the other semiconductor chip or substrate.
- the first electrode formed in the bump forming process and having a shape protruding in a substantially conical shape on one semiconductor chip or substrate constitutes a so-called bump electrode (or protruding electrode).
- the second electrode formed by the pad forming process and having a concave portion having a substantially pyramid or prismatic inner surface on the other semiconductor chip or substrate constitutes a so-called pad electrode joined to the bump electrode. .
- the first electrode and the second electrode are in a state where the first electrode is inserted into the recess of the second electrode in the subsequent pressurizing step (or it can be said that the recess of the second electrode is covered with the first electrode).
- pressure is applied in a direction approaching each other.
- the first electrode and the second electrode approach each other, the first electrode is guided while sliding on the inner surface of the concave portion of the second electrode.
- the central axis of the first electrode and the central axis of the concave portion that is, the second axis
- the center axis of the electrode coincides.
- the shape of the side surface of the first electrode that is, the conical side surface
- the inner surface of the concave portion of the second electrode that is, the inner surface of the substantially pyramid shape or the prism shape
- the first and second electrodes are in a state in which the center axes of the first and second electrodes coincide with each other and at least a part of their side surfaces are in contact with each other.
- the first and second electrodes in this state are joined to each other in a subsequent ultrasonic bonding step, with at least one of the first electrode and the second electrode being vibrated by ultrasonic waves.
- a relatively large force is applied to the contact portion between the first electrode and the second electrode by ultrasonic vibration.
- the surface layers of both electrodes at the contact portion are slightly broken by this force, and the active surface is newly exposed.
- the first electrode and the second electrode come into contact again with each other on the active surfaces, and are firmly metal-bonded. Thereafter, the metal-bonded portion spreads starting from the portion, and finally, the first electrode and the second electrode are in a state of being metal-bonded on almost the entire contact surface.
- the initial contact portion between the first electrode and the second electrode is in a very narrow state such as a line or a point. For this reason, even if the energy of ultrasonic vibration is low, it acts on the portion in a concentrated manner, and the portion becomes a starting point for strong metal bonding in the initial stage of the ultrasonic process. As a result, it is possible to firmly bond the first electrode and the second electrode while reducing the energy of ultrasonic vibration to such an extent that the first electrode does not jump out of the recess of the second electrode.
- a first flat surface is formed at the tip of the first electrode, and the first angle formed by the side surface of the first electrode with respect to the central axis of the first electrode is It is smaller than the second angle formed by the inner surface of the recess with respect to the central axis of the recess of the second electrode.
- the first angle formed by the side surface with respect to the central axis is relative to the central axis of the concave portion of the opposing second electrode. It forms so that it may become smaller than the 2nd angle which an inner surface forms.
- the metal bond between the first electrode and the second electrode is from the tip of the first electrode toward the root, in other words, from the bottom side of the recess of the second electrode to the open end. It will progress toward the club side.
- bubbles confined between the first electrode and the second electrode are prevented from interfering with the formation of the metal bonding surface, and both can be metal-bonded over the entire range of the contact surface.
- a second flat surface is formed at the bottom of the second electrode.
- the diameter of a circle inscribed in the peripheral portion of the second flat surface is smaller than the diameter of the peripheral portion of the first flat surface.
- the positional relationship between the central axis of the first electrode and the central axis of the recess of the second electrode Is not fully regulated.
- the positional relationship may be slightly shifted.
- the first electrode and the second electrode are brought close to each other in the pressurizing step.
- the peripheral edge of the first flat surface i.e., the apex, points to the inner surface of the recess of the second electrode. It will come into contact. For this reason, it is possible to shift to the ultrasonic bonding step in a state where the positional relationship between the central axis of the first electrode and the central axis of the second electrode is completely regulated. As a result, the alignment accuracy between the electrodes can be further improved.
- At least the surfaces of the first electrode and the second electrode are gold.
- the first electrode is chamfered at the periphery of the tip.
- the peripheral portion is compared in the pressurizing step and the ultrasonic bonding step. Will collapse greatly. As a result, a part of the crushed first electrode protrudes from the recessed portion of the second electrode to the periphery, and there is a possibility that the first electrode (or the second electrode) adjacent on the semiconductor chip may come into contact. is there. That is, there is a possibility that adjacent electrodes become conductive, which may cause damage to the semiconductor chip or malfunction. Such contact is particularly likely to occur in a fine-pitch semiconductor chip where the distance between the electrodes is short.
- the first electrode is chamfered at the periphery of the tip.
- it will suppress that the front-end
- the crushed first electrode is suppressed from protruding from the concave portion of the second electrode.
- the semiconductor chips can be bonded while reliably preventing conduction between adjacent electrodes.
- the second electrode formed in the pad forming step is formed so as to protrude entirely from a flat surface of a semiconductor chip or a substrate.
- the second electrode As a specific method for forming the second electrode, for example, it is conceivable to form a recess by etching the surface of the substrate and form an insulating layer or a conductor layer on the surface. Such a method can be easily performed if the material of the substrate or the like is silicon. However, when the material of the substrate or the like is other than silicon, it is generally not easy to form the concave portion directly on the surface of the substrate or the like.
- the second electrode is formed so as to protrude entirely from the flat surface of the semiconductor chip or substrate.
- the second electrode is formed on the surface of the substrate or the semiconductor chip without forming a recess, in other words, the surface of the substrate or the semiconductor chip is kept flat. be able to. Therefore, even when the material of the substrate or the like is other than silicon, it is possible to firmly bond the electrode of the semiconductor chip and the electrode of the substrate or the like using the method according to the present invention.
- a semiconductor device manufacturing method capable of firmly bonding an electrode of a semiconductor chip and an electrode of a substrate or the like at a relatively low temperature while performing alignment with high accuracy, and A semiconductor manufacturing apparatus can be provided.
- the present invention is not limited to a method for manufacturing a semiconductor device in which a semiconductor chip and a substrate are connected as described below, and is also applicable to a method for manufacturing a semiconductor device in which semiconductor chips are connected to each other. can do.
- FIG. 1 is a cross-sectional view showing an example of a semiconductor chip 1 on which a plurality of bump electrodes 100 are formed by a bump forming process according to the first embodiment of the present invention.
- the semiconductor chip 1 is a plate-like body made of silicon, and a plurality of bump electrodes 100 are formed on one surface side thereof.
- the semiconductor chip 1 is referred to as a so-called “bare chip” in a state of being cut out from a wafer on which a semiconductor device is formed. It is mounted in a state of joining.
- the process for forming the bump electrode 100 will be briefly described.
- the insulating layer 2 made of SiO is formed on one surface of the semiconductor chip 1 (upper surface in FIG. 1).
- the insulating layer 2 can be formed by PVD or CVD.
- the insulating layer 2 is patterned in accordance with the arrangement of the metal layer 3 formed on the semiconductor chip 1 by using a photoresist film.
- the metal layer 3 is a layer formed so as to cover the insulating layer 2 and is formed by vapor-depositing a metal mainly composed of gold.
- the metal layer 3 is formed on the insulating layer 2 after the insulating layer 2 is formed and before the photoresist film is removed. Thereafter, the insulating film 2 and the metal layer 3 are simultaneously patterned by removing the photoresist film.
- a plurality of bump electrodes 100 are formed so as to protrude from a part of the metal layer 3.
- the bump electrode 100 has a shape protruding from the metal layer 3 in a substantially conical shape, and a flat surface 101 is formed at the tip thereof.
- the flat surface 101 is substantially parallel to the metal layer 3, and the diameter D ⁇ b> 1 is smaller than the diameter D ⁇ b> 2 of the other end of the bump electrode 100, that is, the portion in contact with the metal layer 3.
- the bump electrode 100 having the shape as shown in FIGS. 1 and 3
- a photoresist film is formed on the surface of the semiconductor chip 1 on which the metal layer 3 is formed.
- the thickness of the photoresist film is set to be substantially the same as the height of the bump electrode 100 (to be formed from now on).
- holes having a diameter D2 are formed by etching at a plurality of locations corresponding to the bump electrodes 100 in the photoresist film.
- the entire bump electrode 100 is formed of gold.
- the substantially conical bump electrode 100 may be formed of copper instead of gold, and then the entire surface thereof may be coated with gold.
- the present invention is particularly effective when at least the surface layer of the bump electrode 100 is made of a relatively soft metal such as gold.
- FIG. 2 is a cross-sectional view showing an example of the substrate 10 on which a plurality of pad electrodes 200 are formed by the pad forming process of the present invention.
- the substrate 10 is a plate-like body made of silicon, and a plurality of pad electrodes 200 are formed on one side thereof. These pad electrodes 200 are formed at positions corresponding to the bump electrodes 100 when the semiconductor chip 1 is connected to the substrate 10.
- the process for forming the pad electrode 200 will be briefly described. First, after masking one surface (upper surface in FIG. 2) of the substrate 10, a rectangular hole is formed at a position where the pad electrode 200 is formed in the masking. That is, only the portion of the surface of the substrate 10 where the pad electrode 200 is formed is exposed.
- the exposed portion is etched.
- etching By etching, a concave portion is formed in the exposed portion.
- the inner surface of the recess is not perpendicular to the surface of the substrate 10, that is, the surface to be masked, and is inclined so as to descend toward the center of the recess. It becomes a surface.
- the inner surface of the recess has a substantially quadrangular pyramid shape with a flat bottom.
- the recess grows deeper while gradually reducing the bottom flat surface. After that, when the depth of the concave portion becomes a predetermined depth smaller than the height of the bump electrode 100, the etching is finished and the masking is removed. Even at this time, a flat surface is formed at the bottom of the recess.
- the insulating layer 12 and the pad electrode 200 are formed so as to cover the entire inner surface of the recess and the portion of the surface of the substrate 10 near the recess.
- the insulating layer 12 is a layer made of SiO like the insulating layer 2 formed on the semiconductor chip 1.
- the pad electrode 200 is a layer formed so as to cover the insulating layer 2 and is formed by depositing gold on a PVD film. Since the formation method of the insulating layer 12 and the pad electrode 200 is the same as the formation method of the insulating layer 2 and the metal layer 3 already described, the description thereof is omitted.
- the entire pad electrode 200 is formed of gold.
- the pad electrode 200 is formed of copper instead of gold, the entire surface thereof may be coated with gold.
- the present invention is particularly effective when at least the surface layer of the pad electrode 200 is made of a relatively soft metal such as gold.
- the pad electrode 200 formed on the substrate 10 through the above steps has a substantially quadrangular pyramid shape with a flat bottom portion (also referred to as a top portion) as a whole, and substantially the same inside.
- a concave portion 210 having a shape is formed. That is, the recess 210 is a surface inclined so that its four inner side surfaces 211 are lowered toward the center, and a flat surface 212 is formed at the bottom.
- the flat surface 212 is a square plane, and the length of one side thereof is smaller than the diameter D1 of the tip of the bump electrode 100. As a result, the diameter of the circle inscribed in the peripheral portion of the flat surface 212 is smaller than the diameter D1 of the peripheral portion of the flat surface 101.
- the bonding is performed by a semiconductor manufacturing apparatus (bonding apparatus BE) including a stage 500 and a pickup apparatus 600.
- bonding apparatus BE semiconductor manufacturing apparatus
- FIG. 5 the joining device BE is schematically drawn.
- the substrate 10 is mounted on the stage 500. At this time, the substrate 10 is in a state where the surface on which the pad electrode 200 is formed faces upward, and the lower surface thereof is fixed to the stage 500 by vacuum suction.
- the pickup device 600 has a flat holding surface 601.
- the surface of the semiconductor chip 1 opposite to the surface on which the bump electrode 100 is formed is brought into contact with the holding surface 601, and the semiconductor chip 1 is held and fixed by vacuum suction.
- a suction hole 602 is formed at substantially the center of the holding surface 601, and air interposed between the holding surface 601 and the semiconductor chip 1 can be exhausted through the suction hole 602 to vacuum-suck the semiconductor chip 1. It has become.
- the pickup device 600 moves the semiconductor chip 1 above the stage 500 so that the semiconductor chip 1 and the substrate 10 face each other in a parallel state.
- the pickup device 600 further adjusts its position so that the positions of all the bump electrodes 100 formed on the semiconductor chip 1 are directly above the (corresponding) pad electrodes 200 formed on the substrate 10.
- alignment marks 4 and 14 are formed on the semiconductor chip 1 and the substrate 10, respectively.
- the stage 500 has a window 510 formed below the alignment mark 14 of the substrate 10. By irradiating infrared rays through the window 510, the positional relationship between the alignment mark 4 and the alignment mark 14 is confirmed by a camera (not shown). It can be done. Note that when the stage 500 is formed of a material transparent to infrared rays (for example, glass), the formation of the window 510 is unnecessary.
- the pickup device 600 finely adjusts the position of the held semiconductor chip 1 based on the information regarding the positional relationship between the alignment marks 4 and 14 obtained from the camera.
- the adjustment at this time is not necessarily performed until the central axis of the bump electrode 100 and the central axis of the concave portion 210 completely coincide with each other, and may be finished when the positional deviation between the central axes is within about 2 ⁇ m.
- the misalignment between the central axes is such that the flat surface 101 at the tip of the bump electrode 100 is reliably inserted into the recess 210 when the pickup device 600 is lowered along the direction perpendicular to the holding surface 601. I just need it. In other words, it is only necessary that the initial contact between the bump electrode 100 and the pad electrode 200 occurs reliably between the outer edge of the flat surface 101 and the inner surface 211.
- the pickup device 600 is lowered along the direction perpendicular to the holding surface 601 while maintaining the semiconductor chip 1 and the substrate 10 in parallel with each other.
- the tip of the bump electrode 100 is inserted into the recess 210, the outer edge of the flat surface 101 contacts the inner surface 211 of the recess 210.
- the central axis of the bump electrode 100 and the central axis of the recess 210 are completely coincident with each other, the outer edge of the circular flat surface 101 is simultaneously in contact with the four inner surfaces 211 at four locations. Will be. However, when the displacement of the stop axis has occurred, the outer edge of the flat surface 101 comes into contact with one inner surface 211 first.
- the outer edge of the flat surface 101 receives a reaction force (that is, a force along the normal direction of the inner side surface 211) from the inner side surface 211 that is in contact. Due to the reaction force, the semiconductor chip 1 translates in a direction in which the central axis of the bump electrode 100 and the central axis of the recess 210 coincide. The semiconductor chip 1 is further lowered while accompanying the parallel movement, and finally, the outer edge of the flat surface 101 is in point contact with the four inner side surfaces 211 (considering distortion of the bump electrode 100 and the like, This may be referred to as line contact or surface contact in a minute area (the same applies hereinafter) (FIG. 6). At this point, the central axis of the bump electrode 100 and the central axis of the recess 210 are completely coincident with each other.
- the pickup device 600 and the semiconductor chip 1 are lowered, the pickup device continues to pressurize the semiconductor chip 1 downward with a predetermined amount of force.
- the ultrasonic vibration is applied to the pickup device 600 from the outside while the bump electrode 100 and the pad electrode 200 are pressed in a direction in which they are brought close to each other. As a result, the pickup device 600 vibrates along a direction (horizontal direction) parallel to the holding surface 601.
- the bump electrode 100 and the pad electrode 200 are in point contact at four places as described above, a relatively large force is applied to the contact portion by ultrasonic vibration.
- the surface layer at the contact portion that is, the surface layer of the bump electrode 100 and the surface layer of the pad electrode 200 is slightly broken by this force, and the active surface is newly exposed.
- the bump electrode 100 and the pad electrode 200 come into contact with each other again on the active surfaces and are firmly metal-bonded. Thereafter, the metal-bonded portions spread starting from these four point contact portions, and finally, the contact surfaces of the bump electrode 100 and the pad electrode 200 are almost entirely metal-bonded (FIG. 7). ).
- the bump electrode 100 and the pad electrode 200 at the beginning that is, before the start of ultrasonic vibration.
- the contact area is very narrow. For this reason, in an ultrasonic vibration process, even if the energy of ultrasonic vibration is low, energy concentrates and acts on a contact part, and a contact part becomes a starting point of a strong metal bond.
- the bump electrode 100 and the pad electrode 200 are strengthened while maintaining the state in which the bump electrode 100 is inserted into the recess 210 and the alignment is performed with high accuracy. Can be joined.
- the entire bump electrode 100 or the like may be formed of copper, or only the surface of the bump electrode 100 or the like may be formed of copper.
- the heating to 400 ° C. is usually performed. Compared to this, it is possible to realize a strong bonding at a very low temperature, for example, 120 to 150 ° C.
- FIG. 8 is an enlarged cross-sectional view of a part of FIG. 6 and shows a state in which at least a part is in contact with each other in the pressurizing step.
- the angle formed by the side surface 102 of the bump electrode 100 with respect to the central axis AX1 of the bump electrode 100 is the inclination angle ⁇ 1, and the central axis of the recess 210 (corresponds to AX1 in FIG. 8).
- ⁇ 1 is smaller than ⁇ 2.
- the dotted lines LN1 and LN2 depicted in FIG. 8 are both straight lines parallel to the central axis AX1.
- the bump electrode 100 By forming the bump electrode 100 in such a shape, the outer peripheral portion of the flat surface 101 at the tip of the bump electrode 100 is in contact with the inner side surface 211 of the recess 210 in the pressurizing step. Therefore, in the subsequent ultrasonic bonding process, the metal bond between the bump electrode 100 and the pad electrode 200 is directed from the tip of the bump electrode 100 to the root, that is, the portion in contact with the metal layer 3, in other words, the pad electrode 200. It proceeds from the flat surface 212 side of the bottom of the recess 210 of the electrode 200 toward the opening end side. As a result, bubbles confined between the bump electrode 100 and the pad electrode 200 are prevented from interfering with metal bonding, and both can be metal-bonded in a wide range.
- a flat surface 212 is formed at the bottom of the recess 210 of the pad electrode 200. Therefore, even if the bump electrode 100 is not formed high, it is possible to prevent a wide space from being formed between the flat surface 101 at the tip of the bump electrode 100 and the flat surface 212 at the bottom of the recess 210. In addition, the time required for the pad forming process is shorter compared to the case where the inner surface of the recess 210 has a complete quadrangular pyramid shape without the flat surface 212.
- the embodiment of the present invention is not limited to the above.
- the shapes of the bump electrode 100 and the pad electrode 200 are as shown in FIG. 9, they are included in the scope of the present invention. That is, a conical shape in which the flat surface 101 is not formed at the tip of the bump electrode 100 or a pyramid shape in which the flat surface 212 is not formed at the bottom of the recess 210 of the pad electrode may be used.
- FIG. 9 is a diagram for explaining the second embodiment of the present invention, and shows a state at a time point before the pressurizing process is performed and the ultrasonic bonding process is started. Show.
- the bump electrode 100 according to the present embodiment has a complete conical shape without the flat surface 101 at the tip.
- the recess 210 of the pad electrode has a complete pyramid shape with no flat surface 212 at the bottom.
- an angle formed by the side surface 102 of the bump electrode 100 with respect to the central axis AX1 of the bump electrode 100 is an inclination angle ⁇ 1
- the recess 210 has a central axis (corresponding to AX1 in FIG. 9).
- ⁇ 1 is larger than ⁇ 2.
- FIG. 10 shows a state where the ultrasonic bonding process is performed from the state shown in FIG. 9 and the bonding between the bump electrode 100 and the pad electrode 200 is completed.
- a gap was formed between the bump electrode 100 and the pad electrode 200 inside the recess 210.
- the gap was formed. Is gone.
- the contact surface between the bump electrode 100 and the pad electrode 200 is in a state of being metal-bonded on almost the entire surface.
- the bump electrode 100 is formed on the semiconductor chip 1 and the pad electrode 200 is formed on the substrate 10.
- the bump electrode 100 is formed on the substrate 10 and the pad electrode 200 is formed on the semiconductor chip 1. It may be formed.
- the inner surface of the recess 210 of the pad electrode 200 may have an arbitrary polygonal pyramid shape such as a substantially pentagonal pyramid shape.
- a semiconductor device capable of firmly bonding the electrode of the semiconductor chip and the electrode of the substrate or the like while performing the alignment with high accuracy is realized as in the above-described embodiments. Can do.
- the inner surface of the recess 210 of the pad electrode 200 may have an arbitrary prismatic shape such as a quadrangular prism shape. That is, the inner surface 211 of the recess 210 may be formed perpendicular to the surface of the substrate 10.
- FIG. 11 is a diagram for explaining the third embodiment of the present invention, and shows a state at a time point before the pressurization process is performed and the ultrasonic bonding process is started.
- the bump electrode 100 according to the present embodiment has a complete conical shape in which the flat surface 101 is not formed at the tip.
- the recess 210 of the pad electrode 200 has an inner surface 211 that is perpendicular to the surface of the substrate 10. In other words, the inner surface 211 is not a pyramid shape but a quadrangular prism shape.
- FIG. 12 shows a state where the ultrasonic bonding process is performed from the state shown in FIG. 11 and the bonding between the bump electrode 100 and the pad electrode 200 is completed.
- a gap was formed between the bump electrode 100 and the pad electrode 200 inside the recess 210.
- the gap was formed. Is gone.
- the contact surface between the bump electrode 100 and the pad electrode 200 is in a state of being metal-bonded on almost the entire surface.
- FIG. 13 is a view for explaining the fourth embodiment of the present invention, and shows a state before the pressurization process is started and the ultrasonic bonding process is started.
- the shape of the bump electrode 100 according to this embodiment is the same as that of the bump electrode 100 according to the first embodiment shown in FIG. That is, it is conical and has a flat surface 101 at its tip.
- the inner surface 211 of the recess 210 of the pad electrode is perpendicular to the surface of the substrate 10. In other words, the inner surface 211 is not a pyramid shape but a quadrangular prism shape.
- FIG. 14 shows a state in which the ultrasonic bonding process is performed from the state shown in FIG. 13 and the bonding between the bump electrode 100 and the pad electrode 200 is completed.
- a gap was formed between the bump electrode 100 and the pad electrode 200 inside the recess 210.
- the gap was formed. Is gone.
- the contact surface between the bump electrode 100 and the pad electrode 200 is in a state of being metal-bonded on almost the entire surface.
- the bump electrode 100 has a shape in which corners are formed in the peripheral portion of the flat surface 101 as shown in FIG. As apparent from FIG. 6, in the pressurizing step, the corner first hits the inner surface 211 of the recess 210. As for the bump electrode 100, the peripheral part of the flat surface 101 will be crushed comparatively greatly. As a result, in the pressurization process and the ultrasonic process, a part of the bump electrode 100 that is crushed and deformed may protrude from the recess 210 to the periphery.
- FIG. 15 shows a state when the ultrasonic process is completed, and schematically shows a state in which a part of the crushed bump electrode 100 protrudes from the recess 210 as described above.
- a protrusion 110 that protrudes outward from the recess 210 is formed.
- the protruding portion 110 extends toward the adjacent bump electrode (reference numeral 100a) and pad electrode (reference numeral 200a).
- the protrusion 110 may come into contact with the bump electrode 100a or the pad electrode 200a. That is, there is a possibility that the adjacent electrodes become conductive and cause damage or malfunction of the semiconductor chip 1.
- FIG. 16 shows a bump electrode 100 according to the fifth embodiment of the present invention.
- the bump electrode 100 according to this embodiment is chamfered along the periphery of the flat surface 101, thereby forming a C surface 120.
- the shape of the pad electrode 200 is the same as in the case of the first embodiment (see FIG. 2 and the like).
- FIG. 17 shows a step of bonding the bump electrode 100 and the pad electrode 200 shown in FIG. 16, and schematically shows a state immediately before the transition from the pressurizing step to the ultrasonic bonding step.
- a C surface 120 is formed on a portion of the bump electrode 100 that first contacts the inner surface 211 of the pad electrode 200. For this reason, it is suppressed that the bump electrode 100 is largely crushed in the pressurization process and the ultrasonic bonding process. As a result, the crushed bump electrode 100 is prevented from protruding from the recess 210 to the periphery. That is, the formation of the protrusion 110 shown in FIG. 15 is suppressed. Therefore, even if the semiconductor chip 1 has a fine pitch, it is possible to reliably prevent conduction between adjacent electrodes.
- the pad electrode 200 is formed by etching a part of the surface of the substrate 10 made of silicon. That is, the concave portion was formed directly on the surface of the substrate 10 itself.
- the material of the substrate 10 is silicon, such a forming method can be adopted.
- the material of the substrate 10 is other than silicon, it is easy to form the recesses directly on the surface of the substrate 10. is not.
- the pad electrode 200 having the recess 210 may be formed so that the whole or substantially the whole protrudes from the flat surface of the substrate 10.
- a sixth embodiment of the present invention will be described as an example of the pad electrode 200 formed in this way.
- FIG. 18 is a cross-sectional view showing the shape of the pad electrode 200 according to the sixth embodiment of the present invention.
- FIG. 19 is a perspective view showing the external appearance of the pad electrode 200.
- no recess is formed on the upper surface of the substrate 10, and the entire upper surface is flat. It is a surface.
- the pad electrode 200 is formed so as to protrude entirely from the flat surface of the substrate 10.
- the pad electrode 200 has only a peripheral edge along the rectangle protruding from the surface of the substrate 10, and as a result, a recess 210 is formed at the center.
- the recesses 210 are inclined so that the four inner side surfaces 211 are lowered toward the center.
- a flat surface 212 is formed. Note that the flat surface 212 in the present embodiment is the insulating layer 12 formed on the surface of the substrate 10.
- an insulating layer 12 made of SiO is formed at a position below the pad electrode 200 on the upper surface of the substrate 10. Then, after masking 250 is applied to the entire top surface of the insulating layer 12, a rectangular hole HL is formed in the masking 250 at a position where the pad electrode 200 is to be formed. That is, only the portion of the surface of the insulating layer 12 where the pad electrode 200 is formed is exposed. Incidentally, the masking 250 is left without being removed in the portion where the recess 210 is formed.
- a metal layer 260 is formed on the entire top surface of the substrate 10 using an NPD method (Nano-Particles-Deposition). As shown in FIG. 20B, the metal layer 260 is formed not only on the upper surface of the masking 250 but also inside the hole HL.
- the portion of the metal layer 260 formed inside the hole HL (that is, the upper surface of the insulating layer 12) has a cross section that protrudes from the insulating layer 12 in a substantially trapezoidal shape. This portion of the metal layer 260 is a portion that becomes the pad electrode 200.
- the masking 250 is removed from the upper surface of the substrate 10. Only the portion of the metal layer 260 that was formed inside the hole HL remains. As a result, the pad electrode 200 having the shape shown in FIGS. 18 and 19 is formed.
- the entire pad electrode 200 (metal layer 260) is formed of gold.
- the pad electrode 200 is formed of copper instead of gold, the entire surface thereof may be coated with gold.
- the present invention is particularly effective when at least the surface layer of the pad electrode 200 is made of a relatively soft metal such as gold.
- the pad electrode 200 formed on the substrate 10 through the above steps has a recess 210 formed in the center.
- the recess 210 is a surface inclined so that its four inner side surfaces 211 are lowered toward the center, and a flat surface 212 is formed at the bottom.
- FIG. 21 is a photograph of the pad electrode 200 actually formed by the method described above and taken.
- FIG. 21A is a photograph taken when the pad electrode 200 is seen from obliquely above
- FIG. 21B is a photograph taken when the pad electrode 200 is seen from above (directly above).
- the pad electrode 200 can be formed on the surface of the substrate 10 without forming a recess, in other words, with the surface of the substrate 10 kept flat. . Therefore, even when the material of the substrate 10 is other than silicon, the pad electrode 200 having the recess 210 can be formed on the substrate 10.
- the shape of the pad electrode 200 formed by the above method is not limited to the substantially rectangular shape as shown in FIG.
- it may be formed in a ring shape as shown in FIG.
- the ultrasonic device USE is disposed on the upper surface side of the pickup device 600, that is, on the opposite side of the holding surface 601 that adsorbs the semiconductor chip 1.
- the ultrasonic device USE is a device for applying ultrasonic vibration to the pickup device 600 in the ultrasonic bonding process.
- the shape of the ultrasonic device USE is substantially flat, and is fixed to the pickup device 600 while being in contact with the entire top surface of the pickup device 600.
- a sheet-like heat insulating material 701 is interposed between the ultrasonic device USE and the pickup device 600.
- the heat insulating material 701 prevents the heat of the heater HT1 described later from being transmitted from the pickup device 600 to the ultrasonic device USE.
- An ultrasonic horn USH which is a transmission source of ultrasonic vibrations, is disposed on the side surface of the ultrasonic apparatus USE.
- the movable unit 810 of the cylinder device 800 is disposed on the upper surface side of the ultrasonic device USE.
- the cylinder device 800 is a device that pressurizes between the semiconductor chip 1 and the substrate 10 by moving the pickup device 600 downward in the pressurizing step.
- the upper surface of the ultrasonic device USE is fixed with respect to the lower end of the movable part 810.
- a load cell LC is disposed between the ultrasonic device USE and the movable unit 810.
- the load applied between the semiconductor chip 1 and the substrate 10 can be detected by the load cell LC.
- the operation of the cylinder device 800 is controlled based on the magnitude of the load detected by the load cell LC.
- the semiconductor chip 1 is translated in a direction (horizontal direction) in which the central axis of the bump electrode 100 and the central axis of the recess 210 coincide.
- a direction for enabling such movement it is conceivable to have mechanical play (backlash) so that the movable portion 810 can easily move along the horizontal direction.
- all of the movable portion 810, the ultrasonic device USE, the pickup device 600, and the semiconductor chip 1 are moved in the horizontal direction as a unit.
- the central axis of the bump electrode 100 and the central axis of the pad electrode 200 cannot be matched.
- the joining device BE is configured such that the semiconductor chip 1 can move in the horizontal direction without depending on the mechanical play of the cylinder device 800. Specifically, the magnitude of the vacuum suction force acting between the semiconductor chip 1 and the pickup device 600 is adjusted (weakly), and the semiconductor chip 1 slides along the holding surface 601 of the pickup device 600. It is the structure to obtain.
- the semiconductor chip 1 slides without any mechanical play regardless of the positional deviation between the bump electrode 100 and the pad electrode 200, and the central axis of the bump electrode 100 and the pad electrode 200. It is possible to match the central axis of the.
- the ultrasonic vibration of the ultrasonic device USE may not be sufficiently transmitted to the semiconductor chip 1. It is done. For this reason, when adjusting the magnitude of the vacuum suction force, it is necessary to pay attention to the fact that the semiconductor chip 1 can be easily moved and that sufficient ultrasonic vibration is transmitted to the semiconductor chip. There is.
- a plurality of suction holes 502 are formed on the upper surface of the stage 500, that is, the surface on which the substrate 10 is placed. Each suction hole 502 communicates with a vacuum exhaust path 503 formed inside the stage 500. Through the suction hole 502 and the vacuum exhaust path 503, the air interposed between the stage 500 and the substrate 10 can be exhausted and the substrate 10 can be vacuum-sucked.
- the holding plates 901 and 902 are arranged around the substrate 10 on the upper surface of the stage 500.
- the holding plate 901 is a plate that is fixed to the upper surface of the stage 500.
- the holding plate 902 is a plate that is vacuum-sucked with respect to the upper surface of the stage 500.
- a suction hole 504 communicating with the vacuum exhaust path 503 is formed below the holding plate 902 in the stage 500.
- the bonding apparatus BE it is possible to bond the semiconductor chip 1 and the substrate 10 without heating them. However, it goes without saying that both may be joined while heating.
- the heater HT1 and the temperature sensor TS1 are embedded in the pickup device 600.
- a heater HT2 and a temperature sensor TS2 are also embedded in the stage 500.
- the semiconductor chip 1 and the substrate 10 can be more reliably connected.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Mechanical Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
2:絶縁層
3:メタル層
4,14:アラインメントマーク
10:基板
12:絶縁層
100,100a:バンプ電極
101:平坦面
110:突出部
102:側面
120:C面
200,200a:パッド電極
210:凹部
211:内側面
212:平坦面
250:マスキング
260:金属層
BE:接合装置
500:ステージ
502,504:吸着穴
503:真空排気路
510:窓
600:ピックアップ装置
601:保持面
602:吸着穴
701:断熱材
800:シリンダー装置
810:可動部
901,902:保持板
AX1:中心軸
D1,D2:直径
LN1,LN2:点線
θ1,θ2:傾斜角
HL:孔
HT1,HT2:ヒーター
LC:ロードセル
TS1,TS2:温度センサ
USE:超音波装置
USH:超音波ホーン
Claims (12)
- 半導体チップと基板、又は半導体チップ同士を接続してなる半導体装置の製造方法であって、
一方の半導体チップ又は基板に、略円錐形状に突出した第一電極を形成するバンプ形成工程と、
他方の半導体チップ又は基板に、内側面が略角錐形状又は角柱形状の凹部を有する第二電極を形成するパッド形成工程と、
前記第一電極を前記第二電極の前記凹部に挿入した状態で、前記第一電極と前記第二電極とを互いに近づける方向に加圧し、前記第一電極の中心軸と前記凹部の中心軸とを一致させた状態とする加圧工程と、
前記第一電極及び前記第二電極の少なくとも一方を超音波により振動させ、前記第一電極と前記第二電極とを接合させる超音波接合工程と、
を備える、半導体装置の製造方法。 - 前記第一電極の先端には第一平坦面が形成されており、
前記第一電極の中心軸に対して前記第一電極の側面が成す第一角度は、前記第二電極の前記凹部の中心軸に対して前記凹部の内側面が成す第二角度よりも小さい、請求項1に記載の半導体装置の製造方法。 - 前記第二電極の底部に第二平坦面が形成されている、請求項2に記載の半導体装置の製造方法。
- 前記第二平坦面の周縁部に内接する円の直径は、前記第一平坦面の周縁部の直径よりも小さい、請求項3に記載の半導体装置の製造方法。
- 前記第一電極の中心軸に対して前記第一電極の側面が成す第一角度は、前記第二電極の前記凹部の中心軸に対して前記凹部の内側面が成す第二角度よりも大きい、請求項1に記載の半導体装置の製造方法。
- 前記第一電極及び前記第二電極は、少なくともその表面が金である、請求項1乃至請求項5のいずれか一項に記載の半導体装置の製造方法。
- 前記第一電極及び前記第二電極は、銅の表面に金のコーティングを施してなる、請求項6に記載の半導体装置の製造方法。
- 前記第一電極及び前記第二電極は、少なくともその表面が銅である、請求項1乃至請求項5のいずれか一項に記載の半導体装置の製造方法。
- 前記第一電極には、その先端部の周縁に面取りが施されている、請求項1乃至8のいずれか一項に記載の半導体装置の製造方法。
- 前記パッド形成工程において形成された前記第二電極は、
半導体チップ又は基板のうち平坦な表面から突出するように形成されている、請求項1乃至9のいずれか一項に記載の半導体装置の製造方法。 - 請求項1乃至10のいずれかに記載された半導体装置の製造方法によって、半導体チップと基板、又は半導体チップ同士の接続を行う、半導体製造装置。
- 半導体チップと基板、又は半導体チップ同士を接続してなる半導体装置を製造する半導体製造装置であって、
一方の半導体チップ又は基板には、略円錐形状に突出した第一電極が形成されており、
他方の半導体チップ又は基板には、内側面が略角錐形状又は角柱形状の凹部を有する第二電極が形成されており、
前記第一電極を前記第二電極の前記凹部に挿入した状態で、前記第一電極と前記第二電極とを互いに近づける方向に加圧し、前記第一電極の中心軸と前記凹部の中心軸とを一致させた状態とする加圧装置と、
前記第一電極と前記第二電極とを接合させるために、前記第一電極及び前記第二電極の少なくとも一方を超音波により振動させる超音波装置と、
を備える、半導体製造装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/428,635 US9627347B2 (en) | 2012-09-24 | 2013-08-29 | Method of manufacturing semiconductor device and semiconductor device manufacturing apparatus |
JP2014536718A JP5967678B2 (ja) | 2012-09-24 | 2013-08-29 | 半導体装置の製造方法、及び半導体製造装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012-210008 | 2012-09-24 | ||
JP2012210008 | 2012-09-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014045828A1 true WO2014045828A1 (ja) | 2014-03-27 |
Family
ID=50341150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2013/073205 WO2014045828A1 (ja) | 2012-09-24 | 2013-08-29 | 半導体装置の製造方法、及び半導体製造装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9627347B2 (ja) |
JP (1) | JP5967678B2 (ja) |
WO (1) | WO2014045828A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101818918B1 (ko) | 2016-06-10 | 2018-01-18 | 크루셜머신즈 주식회사 | 레이저 리플로우 방법 및 이의 방법으로 제조된 기판구조체 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150124201A (ko) * | 2014-04-28 | 2015-11-05 | 삼성전자주식회사 | 반도체 패키지의 진공 흡착 장치 및 방법 |
US11018099B2 (en) * | 2014-11-26 | 2021-05-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure having a conductive bump with a plurality of bump segments |
JP6660687B2 (ja) * | 2015-07-30 | 2020-03-11 | シチズン電子株式会社 | 半導体素子および発光装置 |
EP3185290A1 (en) * | 2015-12-24 | 2017-06-28 | IMEC vzw | Method for self-aligned solder reflow bonding and devices obtained therefrom |
JP6793388B2 (ja) * | 2016-07-12 | 2020-12-02 | 株式会社アルテクス | 接合方法 |
US10750614B2 (en) | 2017-06-12 | 2020-08-18 | Invensas Corporation | Deformable electrical contacts with conformable target pads |
US20190237420A1 (en) * | 2018-01-26 | 2019-08-01 | Facebook Technologies, Llc | Interconnect using nanoporous metal locking structures |
CN112385025B (zh) | 2018-11-21 | 2024-01-30 | 东北微科技株式会社 | 层叠型半导体装置及用于其的多个芯片 |
US11114406B2 (en) * | 2019-01-31 | 2021-09-07 | Sandisk Technologies Llc | Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip |
US10847408B2 (en) | 2019-01-31 | 2020-11-24 | Sandisk Technologies Llc | Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip |
KR20240036725A (ko) * | 2019-07-24 | 2024-03-20 | 보에 테크놀로지 그룹 컴퍼니 리미티드 | 디스플레이 기판 및 그 제조 방법 |
CN113133327B (zh) * | 2019-10-31 | 2024-01-26 | 京东方科技集团股份有限公司 | 承接背板及其制备方法、背板 |
TWI726685B (zh) * | 2020-04-16 | 2021-05-01 | 錼創顯示科技股份有限公司 | 微型發光元件顯示裝置 |
KR20210157787A (ko) | 2020-06-22 | 2021-12-29 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
TWI817052B (zh) | 2020-11-09 | 2023-10-01 | 欣興電子股份有限公司 | 均溫板裝置及其製作方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041611A (ja) * | 1996-07-18 | 1998-02-13 | Matsushita Electric Ind Co Ltd | プリント配線板の製造方法及びプリント配線板 |
JP2008117828A (ja) * | 2006-11-01 | 2008-05-22 | Matsushita Electric Ind Co Ltd | 半導体装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5329423A (en) * | 1993-04-13 | 1994-07-12 | Scholz Kenneth D | Compressive bump-and-socket interconnection scheme for integrated circuits |
US7557452B1 (en) * | 2000-06-08 | 2009-07-07 | Micron Technology, Inc. | Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same |
TW544826B (en) * | 2001-05-18 | 2003-08-01 | Nec Electronics Corp | Flip-chip-type semiconductor device and manufacturing method thereof |
JP2003273160A (ja) | 2002-03-15 | 2003-09-26 | Matsushita Electric Ind Co Ltd | 半導体実装モジュール |
JP3764450B2 (ja) * | 2003-07-28 | 2006-04-05 | Tdk株式会社 | 表面弾性波素子、表面弾性波装置、表面弾性波デュプレクサ、及び表面弾性波素子の製造方法 |
JP4768343B2 (ja) * | 2005-07-27 | 2011-09-07 | 株式会社デンソー | 半導体素子の実装方法 |
JP4813255B2 (ja) * | 2006-05-23 | 2011-11-09 | パナソニック株式会社 | 配線基板及びその製造方法ならびに半導体装置 |
JP4247690B2 (ja) * | 2006-06-15 | 2009-04-02 | ソニー株式会社 | 電子部品及その製造方法 |
US7652374B2 (en) * | 2006-07-31 | 2010-01-26 | Chi Wah Kok | Substrate and process for semiconductor flip chip package |
JP2009098407A (ja) * | 2007-10-17 | 2009-05-07 | Hitachi Displays Ltd | 表示装置 |
US7642135B2 (en) * | 2007-12-17 | 2010-01-05 | Skyworks Solutions, Inc. | Thermal mechanical flip chip die bonding |
MY149251A (en) * | 2008-10-23 | 2013-07-31 | Carsem M Sdn Bhd | Wafer-level package using stud bump coated with solder |
JP2010109032A (ja) * | 2008-10-29 | 2010-05-13 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法 |
US20100133671A1 (en) * | 2008-12-02 | 2010-06-03 | Chung Hsing Tzu | Flip-chip package structure and the die attach method thereof |
JP2011165862A (ja) * | 2010-02-09 | 2011-08-25 | Sony Corp | 半導体装置、チップ・オン・チップの実装構造、半導体装置の製造方法及びチップ・オン・チップの実装構造の形成方法 |
JP2013145932A (ja) * | 2010-05-07 | 2013-07-25 | Murata Mfg Co Ltd | 弾性表面波装置及びその製造方法 |
-
2013
- 2013-08-29 WO PCT/JP2013/073205 patent/WO2014045828A1/ja active Application Filing
- 2013-08-29 US US14/428,635 patent/US9627347B2/en active Active
- 2013-08-29 JP JP2014536718A patent/JP5967678B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041611A (ja) * | 1996-07-18 | 1998-02-13 | Matsushita Electric Ind Co Ltd | プリント配線板の製造方法及びプリント配線板 |
JP2008117828A (ja) * | 2006-11-01 | 2008-05-22 | Matsushita Electric Ind Co Ltd | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101818918B1 (ko) | 2016-06-10 | 2018-01-18 | 크루셜머신즈 주식회사 | 레이저 리플로우 방법 및 이의 방법으로 제조된 기판구조체 |
Also Published As
Publication number | Publication date |
---|---|
JP5967678B2 (ja) | 2016-08-10 |
US20150235984A1 (en) | 2015-08-20 |
JPWO2014045828A1 (ja) | 2016-08-18 |
US9627347B2 (en) | 2017-04-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5967678B2 (ja) | 半導体装置の製造方法、及び半導体製造装置 | |
JP5187714B2 (ja) | 半導体チップの電極接続構造 | |
KR100927120B1 (ko) | 반도체 소자 패키징 방법 | |
JP2007250886A (ja) | 半導体装置の製造方法 | |
TW201935576A (zh) | 半導體裝置之製造方法 | |
WO2014054451A1 (ja) | 半導体装置及びその製造方法 | |
US6841860B2 (en) | Flip-chip bonding structure and method for making the same | |
JP4620939B2 (ja) | 複合素子の製造方法 | |
CN105575889A (zh) | 制造三维集成电路的方法 | |
KR20050033000A (ko) | 반도체 장치의 제조 방법, 반도체 장치의 제조 장치 및접착 필름 | |
TWI539586B (zh) | 覆晶接合方法、及特徵爲包含該覆晶接合方法之固體攝像裝置之製造方法 | |
US20130094800A1 (en) | Optical device and method for manufacturing the optical device | |
JP2001110946A (ja) | 電子デバイスおよびその製造方法 | |
JP2010092931A (ja) | 半導体装置の製造方法及び半導体装置の製造装置 | |
TW201250810A (en) | Wafer and method of manufacturing package product | |
JP5022093B2 (ja) | 実装方法 | |
JP2012186761A (ja) | 電子部品およびその製造方法 | |
JP2010228029A (ja) | Memsデバイスの実装構造 | |
JP2007115789A (ja) | 積層型半導体装置および積層型半導体装置の製造方法 | |
JP2010258667A (ja) | 電子部品およびその製造方法、圧電振動子およびその製造方法 | |
JP2005284302A (ja) | 光部品の実装構造 | |
JP6343980B2 (ja) | 半導体デバイスの製造方法 | |
JP7237666B2 (ja) | パッケージ及びパッケージの製造方法 | |
JP2011187699A (ja) | 半導体装置およびその製造方法 | |
JP2000164636A (ja) | 半導体発光素子の実装方法及びこれに用いるボンディングツール |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13839623 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2014536718 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14428635 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 13839623 Country of ref document: EP Kind code of ref document: A1 |