JP5152157B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5152157B2 JP5152157B2 JP2009260673A JP2009260673A JP5152157B2 JP 5152157 B2 JP5152157 B2 JP 5152157B2 JP 2009260673 A JP2009260673 A JP 2009260673A JP 2009260673 A JP2009260673 A JP 2009260673A JP 5152157 B2 JP5152157 B2 JP 5152157B2
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- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor chip
- semiconductor device
- bump
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
また、半導体チップのバンプに予め熱可塑性樹脂をコーティングしたものを、回路基板に対してフリップチップ接続する技術が、例えば、特開平6−151502号公報に記載されている。(特許文献2)
複数の突起金属電極を有する半導体素子を、回路基板にフェイスダウン実装する半導体装置の製造方法において、
該突起金属電極の頭頂部を平坦かつ平滑にする工程と、少なくとも該突起金属電極の表面部全面を固化した絶縁膜により被覆する工程と、半導体素子の突起金属電極と回路基板上に形成された電極端子を対向配置する工程と、該半導体素子に荷重を印加して該突起金属電極と該回路基板の電極端子とを接合する工程を含むことを特徴とする半導体装置の製造方法。
(付記2)
複数の突起金属電極を有する半導体素子を、回路基板にフェイスダウン実装する半導体装置の製造方法において、
少なくとも該突起金属電極の表面部全面を固化した絶縁膜により被覆する工程と、絶縁膜により被覆された該突起金属電極の頭頂部を平坦かつ平滑にする工程と、半導体素子の突起金属電極と、回路基板上に形成された電極端子を対向配置する工程と、該半導体素子に荷重を印加して該突起金属電極と該回路基板上の電極端子とを接合する工程を含むことを特徴とする半導体装置の製造方法。
(付記3)
前記絶縁膜とポリパラキシリレン樹脂を使用することを特徴とする付記1または2記載の半導体装置の製造方法。
(付記4)
半導体素子の突起金属電極と回路基板上の電極端子とを接合する際に、少なくとも超音波振動と荷重とを半導体素子に印加する工程を含むことを特徴とする付記1〜3の何れかに記載の半導体装置の製造方法。
(付記5)
半導体素子に荷重を印加する前に、半導体素子と回路基板との間に熱硬化性樹脂接着材を介在させる工程を含むことを特徴とする付記1〜4の何れかに記載の半導体装置の製造方法。
2 半導体回路形成部
3 電極パッド
4 パッシベーション膜
5 アンダーバンプメタル
6 フォトレジスト
7 めっき金属バンプ
8 絶縁膜
9 スタッドバンプ
10 半導体チップ
11 ボンディングツール
12 回路基板
13 電極端子
14 アンダーフィル樹脂
Claims (3)
- 複数の突起金属電極を有する半導体素子を、回路基板にフェイスダウン実装する半導体装置の製造方法において、
化学蒸着法により、少なくとも前記突起金属電極の表面部全面を、厚さが0.2μm〜2.0μmの固化した絶縁膜により被覆する工程と、
前記絶縁膜により被覆された前記突起金属電極の頭頂部を硬質バイトを用いて研削加工して、前記突起金属電極を露出させると共に、平坦かつ平滑にする工程と、
前記突起金属電極と、回路基板上に形成された電極端子を対向配置する工程と、
前記半導体素子に荷重を印加して前記突起金属電極と前記電極端子とを接合する工程を含み、
前記絶縁膜の材料としてポリパラキシリレン樹脂を使用することを特徴とする半導体装置の製造方法。 - 前記突起金属電極と前記電極端子とを接合する際に、少なくとも超音波振動と荷重とを前記半導体素子に印加する工程を含むことを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記半導体素子に荷重を印加する前に、前記半導体素子と前記回路基板との間に熱硬化性樹脂接着材を介在させる工程を含むことを特徴とする請求項1又は2に記載の半導体装置の製造方法。
Priority Applications (1)
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JP2009260673A JP5152157B2 (ja) | 2009-11-16 | 2009-11-16 | 半導体装置の製造方法 |
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JP2009260673A JP5152157B2 (ja) | 2009-11-16 | 2009-11-16 | 半導体装置の製造方法 |
Related Parent Applications (1)
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JP2004194016A Division JP4444022B2 (ja) | 2004-06-30 | 2004-06-30 | 半導体装置の製造方法 |
Publications (2)
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JP2010034601A JP2010034601A (ja) | 2010-02-12 |
JP5152157B2 true JP5152157B2 (ja) | 2013-02-27 |
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Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP6004441B2 (ja) | 2013-11-29 | 2016-10-05 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | 基板接合方法、バンプ形成方法及び半導体装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH05267303A (ja) * | 1992-03-17 | 1993-10-15 | Nec Corp | 半導体装置 |
US6225206B1 (en) * | 1999-05-10 | 2001-05-01 | International Business Machines Corporation | Flip chip C4 extension structure and process |
CN1270375C (zh) * | 2000-10-17 | 2006-08-16 | 3M创新有限公司 | 集成电路芯片与电路基片的连接方法及其应用 |
JP2004095923A (ja) * | 2002-09-02 | 2004-03-25 | Murata Mfg Co Ltd | 実装基板およびこの実装基板を用いた電子デバイス |
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