CN1853451B - 用于制造电子模块的方法 - Google Patents
用于制造电子模块的方法 Download PDFInfo
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- CN1853451B CN1853451B CN2004800267977A CN200480026797A CN1853451B CN 1853451 B CN1853451 B CN 1853451B CN 2004800267977 A CN2004800267977 A CN 2004800267977A CN 200480026797 A CN200480026797 A CN 200480026797A CN 1853451 B CN1853451 B CN 1853451B
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- conductive layer
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- conductive
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Abstract
本发明公开了一种制造电子模块的方法,其中从绝缘材料薄片(1)开始制造。在薄片(1)中形成至少一个凹槽(2),并且该凹槽(2)延伸穿过绝缘材料层(1),直到相对表面(1a)上的导电层。元件(6)安装在凹槽中,其接触表面朝向导电层,并且将元件(6)贴附到导电层。此后,由封闭该凹槽的导电图案形成导电图案(14),其与安装在凹槽中的元件(6)的至少某些接触区域或接触突起形成电连接。
Description
技术领域
本发明涉及一种用于制造电子模块的方法。
本发明尤其涉及一种电子模块,其中一个或多个元件嵌入安装基座中。制造的电子模块可以是类似于电路板的模块,其包括几个通过模块中制造的导电结构彼此电连接的元件。本发明尤其涉及一种含有微电路的电子模块,几个接触端子连接于此。除了该微电路之外,或者代替该微电路,其它元件例如无源元件当然也可以嵌入在安装基座中。因此,意图在于将通常以未封装的形式贴附于电路板(电路板的表面)的这种元件嵌入在电子模块中。另一组重要的元件是通常为了与电路板相连接而被封装的元件。本发明涉及的电子模块当然还可包括其它类型的元件。
背景技术
安装基座可以是类似于通常在电子工业中用作电气元件安装基座的基座类型。基座的任务是提供具有机械附着基板的元件以及基座上和基座外部元件间必要的电连接。安装基座可以是电路板,在这种情况下,本发明所涉及的结构和方法与电路板的制造技术紧密相关。安装基座还可以是一些其它基座,例如用于封装一个元件或多个元件的基座,或者用于整体功能模块的基座。
用于电路板的制造技术不同于微电路的制造技术之处特别在于,实际上微电路制造技术中的安装基座,即基板,是半导体材料,而电路板的安装基座的原材料是绝缘材料的某种形式。微电路的制造技术也典型地比电路板的制造技术昂贵得多。
用于外壳以及元件封装,特别是半导体元件的封装的结构和制造技术不同于电路板的结构和制造技术,因为元件封装主要用于形成围绕元件的外壳,其在机械上保护元件并便于处理元件。在元件表面上具有连接器部件,典型为突起,使封装元件易于设置在电路板的恰当位置,并制作与其希望的连接。此外,元件的外壳内部有导体,其将外壳外的连接器部件与实际元件表面的连接区域相连接,并且通过其可以将元件如期望的那样与其外围设备相连接。
然而,使用传统技术制造的元件外壳需要相当大的空间。由于电子设备变得越来越小,存在有减小占用不必要空间以及产生不必要成本的元件外壳的趋势。为了解决这个问题,已经开发了各种结构和方法,借助于此,可以将元件放在电路板结构的内部。
美国专利US4246595公开了一种解决方案,其中在安装基座中形成用于元件的凹槽。凹槽的底部以两层的绝缘层为边界,其中制作有连接该元件的孔。相对于元件放置的绝缘层的层是由粘合剂制成的。此后,将元件嵌入凹槽中,它们的连接区域面对凹槽的底部,通过绝缘层中的孔形成与元件的电接触。如果希望结构在机械上持久耐用,还必须将元件贴附于安装基座上,以至于该方法非常复杂。使用复杂的方法来有利地制造廉价产品是特别困难的,这需要几种不同的材料和处理阶段。
日本专利JP2001-53447公开了第二种解决方案,其中在安装基座中制作用于元件的凹槽。该元件置于凹槽中,元件的接触区域面对安装基座的表面。接着,在安装基座的表面上和元件上制作绝缘层。在绝缘层中制作元件的接触开口,并通过接触开口制作与元件的电接触。在这种方法中,制造凹槽以及将元件设置于凹槽中需要相当大的精确度,以便将元件相对于安装板的宽度和厚度准确定位来确保成功的馈通。
国际专利申请WO 03/065778公开了一种方法,其中在基座中制作了至少一个导电图案,如用于半导体元件的通孔。此后,将半导体元件置于孔中,相对于导体图案对准。半导体元件贴附于基座的结构上,且在基座中制造一个或多个导电图案层,以这种方式至少一个导电图案形成了与半导体元件表面上接触区域的电接触。
国际专利申请WO 03/065779公开了一种方法,其中在基座中制作用于半导体元件的通孔,以使该孔在基座的第一和第二表面之间延伸。制成孔后,聚合物膜在基座结构的第二表面上展开,以使聚合物膜还覆盖基座结构的第二侧面上为半导体元件而制作的通孔。在硬化聚合物膜之前,或者在其部分硬化之后,从基座第一表面的方向将半导体元件置于基座中制作的孔中。相对于聚合物膜按压半导体元件,以便使它们贴附于聚合物膜上。此后,执行聚合物膜的最后硬化并且制造附加的导电图案层,从而至少一个导电图案形成了与半导体元件表面上接触区域的电接触。
发明内容
本发明旨在建立一种采用低制造成本在安装基座中嵌入元件的简单可靠的方法。
本发明基于从绝缘板开始制造,其在至少一侧上用导电层形成表面。此后,在该绝缘上制造凹槽,其开口到板的一个表面,但不穿透板的相对表面上的导电层。元件贴附于凹槽,并且在导电层和接触区域之间或元件的接触突起之间形成电接触。在元件贴附后,由导电层形成导电图案,其变成部分的电路板结构或其它电子模块。
更具体来说,根据本发明的方法其特征在于权利要求1中所描述的内容。
借助于本发明获得了相当多的优点。这是因为本发明可以用来以低制造成本设计简单可靠的方法,这可以用于制造含有嵌入元件的电子模块。作为基本材料所使用的表面导电绝缘板是电路板工业的基本原材料之一,并且这种板可以便宜可靠地得到。该方法中,由于使用表面导电绝缘板来制造电子模块的导电图案,因此原材料的使用特别高效。即使嵌入绝缘板内部的电路也可以与该导电图案层电连接。
本发明具有实施例,根据该实施例,在制造过程中需要相对少的处理阶段。具有较少处理阶段的实施例也相应需要更少的处理设备和各种制造方法。借助于这些实施例,在许多情况下相比更复杂的过程可以减少制造成本。
电子模块的导电图案层的数目也可根据本实施例进行选择。例如,可以是一个或两个导电图案层。此外,还可以电路板工业公知的方式在它们的顶部制造附加的导电图案层。因此,在模块中可以总共有例如三个、四个或五个导电图案层。在最简单的实施例中,仅有单个导电图案层,以及实际上任一导电层。在某些实施例中,电子模块中包含的每个导电层可以用于形成导电图案。
本发明还有一些实施例,在这些实施例中可在元件的位置处制造导电图案。这将增加该结构的布线容量,这由此将使元件更紧密地配置在一起。也可以通过将一些元件“颠倒”放置来提高布线容量,从而使元件的有效表面将面对板的两个表面。下面,借助示例和参考附图来检验本发明。
附图说明
图1-17示出本发明一个实施例中制造方法的一系列横截面。
图18-27示出根据第二实施例的制造方法的一系列横截面。
图28和29示出根据第三实施例的制造方法中电子模块制造的两个中间阶段。
图30和31示出根据第四实施例的制造方法中电子模块制造的两个中间阶段。
具体实施方式
在示例的方法中,该制造是由制造绝缘材料的安装基座开始的,其在至少一个表面上具有导电层。典型地,市场上可获得的由绝缘材料制成的的片1被选作安装基板,其两个表面1a、1b以导电层4形成表面。绝缘材料1可以是例如玻璃纤维加强环氧树脂(例如,FR4)。导电材料4其部分通常是铜。
典型地以这样的方式选择安装基座,即,使绝缘材料层1的厚度大于之后将要贴附于基座上的元件6的厚度,尽管这不是必须的。凹槽2的尺寸根据安装的元件6的尺寸来选择,且凹槽2是以合适的方法在绝缘材料层1中制造的。以这样的方式制造凹槽2,即,使得绝缘材料层1表面上的导电层4封闭凹槽的一端或另一端。这可以通过例如去除围绕凹槽2的安装基座第一表面上的导电材料4而实现。与去除导电材料4相关的,也可以在导电图案层4中形成其它图案,例如将要形成的电路的导体图案。此后,使用合适的选择性方法继续制造凹槽2,这将影响绝缘材料1,而不影响导电层4。由此制造的凹槽2将延伸穿过整个绝缘材料层1,而在凹槽2另一端的导电层4保持完整无损。可以从两个表面的方向以相应的方式制造凹槽2。
还需要合适的对准标记来对准元件6,对于形成对准标记,几种不同的方法都是可用的。一种可能的方法是在元件6的安装孔2附近中形成小通孔。
元件6借助于对准孔或其它对准标记在其安装孔2中对准,且元件贴附于导电层4。元件6可以采用允许在导电层4和元件的接触区域之间形成电接触的方法贴附于导电层4。该方法例如是超声波接合法、热压方法、和用导电粘合剂的粘合。可选择地,可以采用在导电层4和元件的接触区域之间形成电接触的方法。这种方法是例如用绝缘粘合剂粘合。下面将联系上述的贴附方法详细描述该处理过程步骤。
术语超声波方法指的是这样一种方法,其中将含有金属的两片压在一起且以超声波频率将振动能量引入贴附区域。在贴附的表面之间产生的超声波和压力使贴附的片之间彼此冶金地接合在一起。用于产生超声波连接(超声波接合)的方法和装置是市场上可得到的。超声波接合具有的优点在于不需高温就可形成连接。
术语热压方法指的是这样一种方法,其中将含有金属的两片相互挤压并将热能施加在连接区域。在贴附的表面之间产生的热能和压力使贴附的片之间彼此冶金地接合在一起。用于产生热压连接(热压接合)的方法和装置也是市场上可得到的。
术语粘合剂指的是一种材料,借助于这种材料可将元件贴附于导电层。粘合剂的一种特性是粘合剂可以在导电层和/或元件的表面上以相对流体的形式、或反之以与表面形状一致的形式被扩散。粘合剂的另一特性在于,扩散后粘合剂会变硬或至少部分变硬,从而使粘合剂能够将元件保持在合适的位置(相对于导电层),至少直到元件以某些别的方式固定到结构上为止。粘合剂的第三种特性是它的粘合能力,即它粘住被胶粘的表面的能力。
术语胶粘指的是借助于粘合剂将元件和导电层彼此贴附。因此,在胶粘中,在元件和导电层之间引入粘合剂,且元件相对于导电层置于合适的位置,其中粘合剂与元件和导电层相接触,且至少部分地填充元件和导电层之间的空间。此后,使粘合剂(至少部分)变硬,或者使粘合剂(至少部分)主动地变硬,从而使元件借助于粘合剂粘住导电层。在某些实施例中,在胶粘期间,元件的接触突起可以延伸穿过粘合剂层,从而与导电层接触。
元件6由此可以借助于导电粘合剂贴附到导电层4的表面。适于该目的的导电粘合剂通常在两个基本类型中是可用的:各向同性导电粘合剂和各向异性导电粘合剂。各向同性导电粘合剂在所有方向均导电,而各向异性导电粘合剂具有导电方向和与其在直径上相对的方向,在该相对方向上粘合剂的导电性特别低。例如,可以由混入适当导电颗粒的绝缘粘合剂形成各向异性导电粘合剂。如果使用各向异性导电胶合剂,那么该胶合剂可以在被粘合的元件的整个表面上配料。当使用各向同性导电胶合剂时,应当按区域进行配料,使得在接触区域之间不会产生短路。
在元件贴附后,在安装凹槽2中剩下的空间通常被填充以填充物8。此后,可以将导电层4图案化,以便形成导电图案14,其中至少一些导电图案连接到元件6中某些的接触区域。此后,通过制造另外的导电图案层以及制造所需的通孔来继续该过程。
使用超声波方法和热压方法的制造过程详细公开于同一申请人已完成的专利申请FI20030292中,该申请提交于2003年2月26日,在提交本申请时仍然是未公开的。
使用导电胶合剂的制造过程依次详细公开于同一申请人已完成的专利申请FI20031201中,该申请提交于2003年8月26日,在提交本申请时仍然是未公开的。
因此,代替形成电接触的贴附方法,还可以使用其中不形成电接触的方法。例如,可以通过借助于绝缘粘合剂将元件6胶粘到导电层4的表面来制造这种连接。胶粘后,安装凹槽2可填充以填充物8和制造的馈通,通过其可以在元件6和导电层4的接触区域之间形成电接触。用于馈通的孔17在导电层4中元件6的接触区域处制作。以如下方式制造孔17,即,使他们还可以穿破已保留在接触区域顶部上的粘合剂层,或者接触突起。由此孔17延伸直到元件6的接触突起或其它接触区域的材料。例如,可以通过用激光装置打孔或者使用一些其它合适方法来形成孔17。此后,以在元件6和导电层4之间形成电接触的方式将导电材料引入孔17。
此后,可将导电层4图案化,以便形成导电图案14,其中至少一些连接到元件6的某些接触区域。此后,可以通过制造另外的导电图案层和制造所需的馈通来继续该过程。
使用绝缘粘合剂的制造过程详细公开于同一申请人已完成的专利申请FI20030493,该申请提交于2003年4月1日,在提交本申请时仍然是未公开的。
可以采用对电路板制造领域的熟练技术人员来说通常是公知的制造方法来实施根据该示例的制造过程。
下面,详细检验图1-17所示方法的阶段。
阶段A(图1):
在阶段A,选择通过其形成安装基座主体的合适的绝缘材料片1,用于电子模块制造过程。在使用单个绝缘材料层的实施例中,绝缘材料层1应优选厚于安装的元件。接着,可以将元件整体地嵌入安装基座内部,且电子模块在两侧是平滑的。其后表面突出超过绝缘材料层1的更厚的特定元件当然也可以嵌入安装基座中。这是该实施例中优选的特定程序,其中采用几个绝缘材料层,在加工期间将它们连接在一起。在该情况下,如果绝缘材料层的总厚度超过元件的厚度,则该元件可以整体地嵌入结构中。鉴于结构的持久性,已完成的电子模块中的元件优选整体地位于安装基座内部。
例如,绝缘材料层1可以是聚合物基座,例如玻璃纤维加强环氧树脂FR4。适于绝缘材料层1的其它材料为PI(聚酰亚胺)、FR5、芳族聚酰胺、聚四氟乙烯、特氟LCP(液晶聚合物)以及预硬化粘合剂层,即预浸渍制品。
预浸渍制品指的是电路板工业的基本材料之一,其通常是浸有B阶段树脂的玻璃纤维加强绝缘垫。当制造多层电路板时,将预硬化粘合剂层典型地用作贴附绝缘材料。其B阶段树脂借助于温度和压力,例如挤压或层压,以受控的方式交联,以至于树脂变硬并变成C阶段。在受控的硬化周期中,温度上升期间,树脂软化并且它的粘性消失。通过施加压力,流体树脂填充其边界表面中的孔和开口。当使用预硬化粘合剂层时,利用该特性来填充元件周围剩余的空闲空间。以这种方式,可以进一步简化示例中所描述的电子模块制造方法,这是因为元件的安装凹槽不需要用单独的填充物填充。
绝缘材料层1在两个侧面1a、1b上以例如金属层的导电层4形成表面。电子模块的制造者也可以选择现成的表面化绝缘片作为基本材料。
阶段B(图2):
在阶段B,采用某些合适的方法由导电层4形成导电图案14。例如,可以使用激光汽化、或某些在电路板工业广泛使用和公知的选择性蚀刻方法进行导电材料的去除。以如下方式制成导电图案14,即,使绝缘材料层1的表面暴露在为元件6制作的安装凹槽2处,或者表面1a或1b的侧面。
相应地,在绝缘材料层1的相对表面1a或1b上的导电材料层14保持完好无损。
阶段C(图3):
在阶段C,在绝缘材料层1中制作合适尺寸和形状的凹槽2,用于嵌入元件。可以例如使用某些电路板制造中已知的方法按要求制造凹槽2。例如,可以使用CO2制造凹槽。从第二表面1b的方向制造凹槽2,并且延伸通过整个绝缘材料层1,直到在该层的相对表面上的导电材料层14的表面1a。
阶段D(图4):
在阶段D,将电子模块的坯件相反地旋转。
阶段E(图5):
在阶段E,制作绝缘材料层1中另外的安装凹槽2,用于第一表面1a方向上的元件。另外,可以用与阶段C中相同的方式制造凹槽2。
阶段F(图6):
在阶段F,粘结剂层5在安装凹槽2的底部和导电层14的顶部上扩散。当之后将元件6按压在粘结剂层5上时,选择粘合层5的厚度,使得粘合剂适当地填充元件6和导电层14之间的空间。如果元件6包括接触突起7,则粘结剂层5的厚度比接触突起的高度大例如约1.5-10倍是很好的,以便很好地填充元件6和导电层14之间的空间。为元件6形成的粘结剂层5的表面区域还可以稍大于元件6的相应表面区域,这同时也有助于避免不充分填充的危险。
可以用如下方式对阶段F进行修改,即,使粘结剂层5在元件6的贴附表面上扩散,而不是导电层14的贴附区域。例如,可以在将其放在电子模块中的合适位置之前,通过将元件浸入粘合剂中来执行这一阶段。也可以通过在导电层14的贴附区域上和元件6的贴附表面上扩散粘合剂来进行。
因此,该示例中使用的粘合剂是电绝缘体,以使得粘结剂层5自身不形成元件6的接触区域之间的电接触。
阶段G(图7):
在阶段G,将要从第一表面1a的方向安装的元件6被放在电子模块中合适的位置。例如这可以通过借助于装配机将元件6压入粘结剂层5中来完成。
阶段H(图8):
在阶段H,电子模块的坯件相反地旋转(见阶段D)。
阶段I(图8):
在阶段I,将粘结剂层5在开口到第二表面1b上的安装槽2的底部上扩散。相应于阶段F执行阶段I,但是是从电子模块的相对表面的方向。
如果采用的制造装置允许从两个方向进行工作阶段,那么由电子模块的相对侧形成的工作阶段(例如阶段F和I)原则上也可以同时进行或者连续进行,而无需旋转坯件。
阶段J(图9):
在阶段J,将要从第二表面1b的方向安装的元件6被放在合适的位置中,相应于电子模块的阶段G。
阶段K(图10):
在阶段K,元件6和安装基座之间余下的空间被完全填充以填充物8,其例如是某些合适的聚合物。如果绝缘材料1是预硬化粘接剂层(预浸渍制品),则可以省略这个阶段。
阶段L(图11):
在阶段L,制造孔17用于元件6的电接触。以这样的方式穿过导电层14和粘结剂层5来制造孔17,即,使得接触突起的材料或者元件6的相应接触区域被暴露。例如可以通过借助激光打孔来制造孔17。在元件6的接触区域制造足够大量的孔17。在该过程中,如果意图不仅穿过导电层14而且穿过一些其它导电层而形成与元件6的直接接触,那么孔17不必必须制作在参与这种接触的接触区域处。典型地,例如,为了形成元件6的接触区域和导电层24之间的可靠接触,孔28形成为两部分;首先在元件6和导电层14之间制作孔17,接着直接在其顶部制作孔27。
阶段M(图12):
在阶段M中,在模块中制作用于馈通的孔11。例如,通过机械打孔来制作孔11。
阶段N(图13):
在阶段N,导电材料15生长为在阶段L中制作的孔17和在阶段M中制作的通孔11。在示例过程中,导电材料15还可以在基座顶部的其他地方生长,以使得还能够增加导电层14的厚度。
生长的导电材料15可以例如是铜或某些其它充分导电的材料。在选择导电材料15时,必须注意与元件6的接触突起7或其它接触区域的材料形成电接触的材料性能。在一示例过程中,导电材料15主要是铜。通过用化学铜薄层形成孔11和17的表面,在此后用电化学铜生长法继续形成表面,从而可以制作铜金属化。例如,采用化学铜,因为它也在粘合剂顶部形成表面,并作为电化学表面化中的电导体。因此,可以采用湿化学法进行金属的生长,以使得该生长很廉价。
阶段N旨在形成元件6和导电层14之间的电接触。在阶段N,增加导电层14的厚度不是必须的,相反可以以这种方式等效地设计该阶段,即,在阶段I仅用合适的材料填充孔17和11。例如,可以通过用导电胶填充孔17和11,或者采用某些其它适于微馈通的金属化方法来制造导电层15。
在后图中,示出导电层15与导电层14融合在一起。
阶段O(图14):
在阶段O,导电层14以这样的方式进行构图,即,使得导电图案14在薄片1的两表面上形成。例如,可以用图B中描述的方式进行图案化。
在阶段O之后,电子模块含有元件6或几个元件6以及导电图案14,借助于其,元件或多个元件6可以连接到外部电路或彼此连接。于是,为了制造操作整体而存在有预处理。因此,可以用电子模块在阶段O之后就绪的方式设计该过程,且图14实际上示出一种可能的电子模块。如果期望的话,还可以在阶段O之后继续该过程,例如用保护性物质覆盖电子模块,或者在第一和/或第二表面上制造另外的导电图案层。
阶段P(图15):
在阶段P,在薄片1的两表面上形成绝缘材料层21,以及在绝缘材料层21的顶部上形成导电层24。例如,可以采用在薄片1的两表面上按压合适的RCF箔来进行阶段P。于是,RCF箔包括绝缘材料层21和导电层24。当借助于热和压力将RCF箔按压在薄片1上时,层21的聚合物在导电层14和24之间形成统一的且紧密的绝缘材料层。借助于该过程,导电层24也变得相对平整且光滑。
阶段Q(图16):
在阶段Q,制造孔27用于在导电层14和24之间形成馈通。例如,可以在阶段L中可以用激光制造孔。在一些实施例中,还可以制造孔28,借助于该其可以用导电层24和元件6的接触突起或接触区域形成直的馈通。
阶段R(图17):
在阶段R,在孔27(和孔28)中生长导电材料15,而同时还可以增加导电层24的厚度。可以相应于阶段N进行阶段R。
在阶段R之后,可以通过将导电层24图案化和可能地通过在任一或两个表面上制造另外的导电层来继续该过程。还能够以电路板技术的常规方式将单独的元件连接到电子模块表面上的导电层。
借助于图18-27,下面将处理制造过程的一些可能的改动。
阶段A2(图18):
在阶段A2,正如在阶段A那样,选择由其形成安装基座主体的合适的绝缘材料薄片1用于电子模块的制造过程。在示例的过程中,用例如金属层的导电层4从第一表面1a形成绝缘材料层1的表面。
阶段B2(图19):
在阶段B2,正如在阶段C那样,在绝缘材料层1中制造合适尺寸和形状的凹槽2,用于将元件嵌入薄片中。从第二表面1b的方向制造凹槽2,且延伸穿过整个绝缘材料层1,直到该层的相对表面上的导电材料层4的表面。
阶段C2(图20):
在阶段C2,将要从第二表面1b的方向安装的元件6被放在凹槽2中合适的位置,并连接到导电层4。于是,还在元件的接触突起或接触区域与导电层4之间形成电接触。例如可以用各向同性或各向异性的导电粘合剂进行胶粘,来制作元件6的连接。还可以采用某些其它适用的方法,例如超声波或热压方法来实行该贴附。
阶段D2(图20):
在阶段D2,元件6和安装基座之间余下的空间用填充物8来完全填充,其例如是一些合适的聚合物。
阶段E2(图21):
在阶段E2,采用某些合适的方法由导电层4形成导电图案14。例如,可以通过激光汽化、或采用在电路板工业广泛使用和公知的选择性蚀刻方法中的其中一种来进行导电材料的去除。
阶段F2(图22):
在阶段F2,在薄片1的第二表面1b上形成导电层9。例如,通过将RCF箔层叠在第二表面1b上而进行阶段F2。
阶段G2(图23):
在阶段G2,在绝缘材料层1中制造用于元件的凹槽2,正如阶段B2中一样。现从第一表面1a的方向制造凹槽2,并延伸直到导电材料层9的表面。
阶段H2(图24):
在阶段H2,将要从第一表面1a的方向安装的元件6被连接到导电层9。可以正如阶段C2中那样进行该阶段。
阶段I2(图20):
在阶段I2,元件6和安装基座之间余下的空间被填充物8完全填充,例如某些合适的聚合物。
阶段J2(图25):
在阶段J2,采用合适的方法由导电层9形成导电图案19。
阶段K2(图26):
在阶段K2,制造孔27,用于在导电图案层14和19之间形成馈通。
阶段L2(图27):
在阶段L2,在孔27中生长导电材料。可以如阶段N那样相应地进行阶段L2。
在阶段L2之后,电子模块包括两个导电图案层和连接于其的嵌入元件6。如果在制造的电子模块中不需要几个导电层,那么可以例如在阶段L2之后用保护性物质来保护该模块。在阶段L2之后,如果期望的话,也可以在模块中制造另外的导电层,或者将表面组装的元件与其相连接。该模块也可以彼此连接,以制造多层结构。
以上所描述的是这样的实施例,其中由单个统一的绝缘材料薄片例如玻璃纤维加强环氧树脂薄片、或预浸渍制薄片形成绝缘材料层1。然而,绝缘材料层1可以同样由多于一个部分制造。于是,还可以使得绝缘材料层1由多于一种绝缘材料形成的方式进行该过程。图28-31示出两个这种实施例。
图28示出包括第一绝缘材料层1的部件,具有元件6设置在其中制作的凹槽中。此外,该元件包括在绝缘材料层1表面上的导电层4。第一绝缘材料层1的厚度优选大于元件6的高度。例如,可以通过结合前述一系列图的子过程来制造类似于图中所示的部件。除了该部件以外,图中还示出第二绝缘材料层11,其中凹槽22用于元件6,以及还制作第二导电层9。
在上述实施例中,第二绝缘材料层11是预浸渍制品。于是,第一绝缘材料层1还可以是某些绝缘材料,例如,玻璃纤维加强环氧树脂薄片。此后,该层结合在一起,形成图29中描述的部件。从图28中可以看出,预浸渍制品中含有的树脂填充元件6和其周围物之间的空间。此后,可以借助于上述子过程继续电子模块的制造。
图30示出第一和第二部件,两者均包括第一绝缘材料层1和在绝缘材料层1中制造的凹槽中的元件6。此外,该部件包括在绝缘材料层1的第一表面上的导电层4和在绝缘材料层1的第二表面上的导电图案19。在两个部件中,第一绝缘材料层的厚度大于元件6的高度。第二部件相对于第一部件以这样的方式进行旋转,即,使得导电图案19彼此面对以及第二绝缘材料层11置于两部件之间,其中在第二绝缘材料层11中形成用于元件6的凹槽22。此后,第二绝缘材料层11彼此贴附于一起,形成图31中所示的模块结构。图31的结构紧凑而薄,并且在该过程阶段,其已经包括4个导电层(层4、4、19和19)。
在图30和31所示的实施例中,预浸渍制品也可用作第二绝缘材料层11。于是,两个部件的第一绝缘材料层1还可以是一些其它绝缘材料,例如玻璃纤维加强环氧树脂薄片。借助于该预浸渍制品,使得两部件之间的空间实现良好的填充,如图29的示例所示。例如,可以借助于上述子过程来制造图30和31中所示的模块。例如,也可以用如图10或图24中所示元件的相应方式继续电子模块的制造,这些方式允许选择的连接技术、导电层4的图案需求以及过程中其它类似的特殊需求。
借助于前述图案序列示出的一些可能过程的实例可以充分利用我们的本发明。然而,本发明不仅仅限于上述公开的过程,而是考虑到权利要求的完整范围和其等效解释,本发明还覆盖其它不同的过程和其最终产品。本发明同样不限于实例中描述的构造和方法,本领域专业技术人员显而易见的是,本发明的各种应用可用于制造许多不同的电子模块和电路板,这甚至在很大程度上不同于上述实例。因此,图中的元件和连接仅用于解释该制造过程。因此,可以对上述给出的实例中的过程作出许多改变,只要齐不偏离根据本发明的基本思想。例如,这些改变可以涉及不同阶段中描述的制造技术或者过程阶段中彼此之间的序列。
在上述过程中,可以用如下方式采用几种技术来贴附元件,例如从第一表面的方向贴附的元件采用某第一技术被贴附,而从第二表面的方向贴附的元件采用不同于所述第一技术的某第二技术被贴附。
在上述给定的实例中,可以制造包括从第一和第二方向嵌入的元件的电子模块。当然,在本发明的范围之内,同样可以制造仅包括从一个方向嵌入的元件的更简单模块。借助于这种更简单模块,可以制造包括从两个方向嵌入元件的模块。可以用这样的方式制作模块,例如,使两个模块从其“后”侧层叠在一起的方式,从而使得包含在子模块中的主动表面与层叠在一起的模块的相对外表面相面对。
Claims (11)
1.一种制造电子模块的方法,其特征在于:
-采用薄片,其具有第一(1a)和第二(1b)表面,并且该薄片包括在第一(1a)和第二(1b)表面之间的绝缘材料层(1),以及在至少第一表面(1a)上的第一导电层(4;9),
-在薄片(1)中制造至少一个第一凹槽(2),其延伸穿过第二表面(1b)和绝缘材料层(1)直到第一表面(1a)上的第一导电层(4;9),所述第一导电层从第一表面(1a)的方向覆盖第一凹槽(2),
-采用具有接触表面的第一元件(6),所述接触表面具有接触区域或接触突起,
-将第一元件(6)置于第一凹槽(2)中,其接触表面面对第一表面(1a),并将第一元件(6)贴附于第一导电层(4;9),所述第一导电层从第一表面(1a)的方向覆盖第一凹槽(2),以及
-由所述第一导电层(4)形成第一导电图案(14),所述第一导电图案电连接到置于第一凹槽(2)中的第一元件(6)的至少一些接触区域或接触突起,
其中通过借助于电绝缘粘合剂的胶粘,将至少一个第一元件(6)贴附于第一导电层(4,9),并且其中通过制作馈通,在第一元件(6)与第一导电层(4;9)之间形成电接触,所述馈通将期望的接触区域连接到第一导电层(4;9)。
2.根据权利要求1的方法,在所述至少一个第一元件(6)已经贴附到第一导电层(4)并且从第二表面(1b)的方向封闭所述至少一个第一凹槽之后,包括执行下列步骤:
-在薄片的第二表面(1b)上制造第二导电层(9),
-在薄片(1)中制造至少一个第二凹槽(2),其延伸穿过第一表面(1a)和绝缘材料层(1)直到第二表面(1b)上的第二导电层(9),所述第二导电层从第二表面(1b)的方向覆盖第二凹槽(2),
-采用具有接触表面的第二元件(6),所述接触表面具有接触区域或接触突起,
-将第二元件(6)置于第二凹槽(2)中,其接触表面朝向第二表面(1b),并将第二元件(6)贴附于第二导电层(9),所述第二导电层从第二表面(1b)的方向覆盖第二凹槽(2),以及
-由第二导电层(9)形成第二导电图案(19),该第二导电图案电连接到置于第二凹槽(2)中的第二元件(6)的至少一些接触区域或接触突起。
3.根据权利要求1的方法,其中使用薄片,其利用两个表面上的导电层(4)形成表面,且其中
-至少一个第二凹槽(2)制作在薄片(1)中,并且延伸穿过第一表面(1a)和绝缘材料层(1)直到第二表面(1b)上的第二导电层(4),所述第二导电层从第二表面(1b)的方向覆盖所制造的凹槽(2),
-采用具有接触表面的第二元件(6),所述接触表面具有接触区域或接触突起,
-将第二元件(6)置于第二凹槽(2)中,其接触表面面对第二表面(1b),并将第二元件(6)贴附于第二导电层(4),所述第二导电层从第二表面(1b)的方向覆盖第二凹槽(2),以及
-由第二导电层(4)形成第二导电图案(14),该第二导电图案电连接到设置于第二凹槽(2)中的第二元件(6)的至少一些接触区域或接触突起。
4.根据权利要求1的方法,其中绝缘材料层(1)的厚度小于贴附于第一导电层的至少一个第一元件(6)的厚度,且其中:
-采用至少一个第二绝缘材料薄片(11),
-在第二绝缘材料薄片(11)中制作用于贴附于导电层(4)的所述至少一个第一元件(6)的至少一个凹槽(22),并且
-第二绝缘材料薄片(11)从第二表面(1b)的方向贴附于第一绝缘材料层(1)。
5.根据权利要求1的方法,其中制造第一和第二部件,这两者都包括绝缘材料层(1)、在绝缘材料层(1)的至少第一表面(1a)上的第一导电层(4)、以及在至少一个第一凹槽(2)中的至少一个第一元件(6),其中该方法:
-采用至少一个第二绝缘材料薄片(11),以及
-借助于所述第二绝缘材料薄片(11),以使得部件中包含的绝缘材料层(1)的第二表面(1b)彼此面对的方式将第一和第二部件彼此贴附。
6.根据权利要求4或5的方法,其中第一绝缘材料层(1)是第一绝缘材料,且第二绝缘材料薄片(11)是不同于第一绝缘材料的第二绝缘材料。
7.根据权利要求1的方法,其中贴附到导电层(4;9)的至少一个第一元件(6)是未封装的微电路芯片。
8.根据权利要求1的方法,其中为了制造多层电路板结构,在第一(1a)和/或第二(1b)表面上制造另外的绝缘层和导电层。
9.根据权利要求1的方法,其中该电子模块包括至少两个薄片,第一元件(6)嵌入在该至少两个薄片(1)中,所述至少两个薄片随后贴附于彼此的顶部。
10.根据权利要求1的方法,其中在绝缘材料层(1)的第二(1b)表面上制造第二导电图案层(14;19)。
11.一种电子模块,包括:
薄片,其具有第一(1a)和第二(1b)表面,并且该薄片包括在第一(1a)和第二(1b)表面之间的绝缘材料层(1),
在薄片的第一表面(1a)上的第一导电图案(14),
在薄片(1)中的至少一个第一凹槽(2),其延伸穿过第二表面(1b)和绝缘材料层(1)直到第一表面(1a)上的第一导电图案(14),
具有接触表面的至少一个第一元件(6),所述接触表面具有接触区域或接触突起,该至少一个第一元件(6)置于第一凹槽(2)中,其接触表面面对第一表面(1a),并且借助于绝缘粘合剂层(5)将该至少一个第一元件(6)贴附于第一导电图案(14),
借助于延伸穿过绝缘粘合剂层(5)的馈通将第一导电图案(14)电连接到置于第一凹槽(2)中的第一元件(6)的至少一些接触区域或接触突起,
在薄片的第二表面(1b)上的第二导电图案(19),
薄片(1)中的至少一个第二凹槽(2),其延伸穿过第一表面(1b)和绝缘材料层(1)直到第二表面(1b)上的第二导电图案(19),
具有接触表面的至少一个第二元件(6),所述接触表面具有接触区域或接触突起,该至少一个第二元件(6)置于第二凹槽(2)中,其接触表面面对第二表面(1b),该至少一个第二元件(6)贴附于第二导电图案(14),以及
所述第二导电图案(19)被电连接到设置于第二凹槽(2)中的第二元件(6)的至少一些接触区域或接触突起。
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2003
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2004
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- 2004-09-15 WO PCT/FI2004/000538 patent/WO2005027602A1/en active Application Filing
- 2004-09-15 GB GB0605377A patent/GB2422054B/en active Active
- 2004-09-15 JP JP2006526649A patent/JP4977464B2/ja active Active
- 2004-09-15 DE DE112004001727.0T patent/DE112004001727B4/de active Active
- 2004-09-15 US US10/572,340 patent/US7696005B2/en active Active
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2010
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2014
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2020
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JP2007506273A (ja) | 2007-03-15 |
CN1853451A (zh) | 2006-10-25 |
US7696005B2 (en) | 2010-04-13 |
US20070166886A1 (en) | 2007-07-19 |
US9232658B2 (en) | 2016-01-05 |
FI20031341A (fi) | 2005-03-19 |
DE112004001727B4 (de) | 2020-10-08 |
KR20060066115A (ko) | 2006-06-15 |
US10798823B2 (en) | 2020-10-06 |
US20150124411A1 (en) | 2015-05-07 |
FI20031341A0 (fi) | 2003-09-18 |
US20200187358A1 (en) | 2020-06-11 |
US20100188823A1 (en) | 2010-07-29 |
WO2005027602A1 (en) | 2005-03-24 |
US11716816B2 (en) | 2023-08-01 |
GB2422054B (en) | 2007-05-16 |
GB2422054A (en) | 2006-07-12 |
DE112004001727T5 (de) | 2006-10-19 |
GB0605377D0 (en) | 2006-04-26 |
US20210329788A1 (en) | 2021-10-21 |
JP4977464B2 (ja) | 2012-07-18 |
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