CN109103201A - 具有分段共享资源区域的三维异或串 - Google Patents

具有分段共享资源区域的三维异或串 Download PDF

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CN109103201A
CN109103201A CN201810657596.0A CN201810657596A CN109103201A CN 109103201 A CN109103201 A CN 109103201A CN 201810657596 A CN201810657596 A CN 201810657596A CN 109103201 A CN109103201 A CN 109103201A
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E.哈拉里
R.A.切尔内亚
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Sunrise Storage Co
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    • G—PHYSICS
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    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
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    • H03—ELECTRONIC CIRCUITRY
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    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract

一种NOR串包括共享位线的多个可个别寻址的薄膜存储晶体管，其中所述可个别寻址的薄膜晶体管进一步被分组为预定数目片段。在每一片段中，该片段的薄膜存储晶体管共享源极线片段，该源极线片段与NOR串内的其他片段中的其他源极线片段电隔离。可以沿着在半导体衬底的表面之上并且平行于半导体衬底的表面提供的半导体层的有源条带，形成NOR串，其中每个有源条带包括第一导电性的第一和第二半导体子层、以及第二导电性的第三半导体子层，其中共享位线和每个源极线片段分别形成在第一和第二半导体子层中。

Description

具有分段共享资源区域的三维异或串
相关申请的交叉引用
本申请涉及并要求2017年6月20日提交的标题为“3-Dimensional NOR Stringswith Segmented Shared Source Regions”的美国临时专利申请(“临时申请”)序列号62/522,665的优先权。该申请还涉及2016年8月26日提交的、并且现在公开为U.S.2017/0092371的、标题为“Capacitive-Coupled Non-Volatile Thin-film Transistor Stringsin Three-Dimensional Arrays”的共同未决的美国专利申请(“共同未决的非临时申请”)序列号15/248,420。所述临时申请和共同未决的非临时申请通过引用整体由此并入。通过该公开的段落号进行本文中对于共同未决的非临时申请的引用。
技术领域
本发明涉及非易失性NOR型存储器串。具体地，本发明涉及包括非易失性NOR型存储器串的阵列的3维半导体结构。
背景技术
共同未决的非临时申请公开了在半导体结构中组织为NOR串的存储晶体管的三维阵列。每个这样的NOR串包括共享共同或共享漏极区以及共同或共享源极区的大量可个别寻址的薄膜存储晶体管(“TFT”)。如共同未决的非临时申请的片段落[0159]中所讨论的，当NOR串中的TFT被寻址和读取时，由于NOR串中大量其他TFT(例如，数千个)导致的累积关断状态源极-漏极泄漏电流)可干扰寻址TFT的读取电流。为了避免这样的大泄漏电流，人们可以考虑具有较短的NOR串(即，具有较少TFT的NOR串)。然而，对于存储器串的阵列中的给定数量的TFT，每个NOR串中的较少数量的TFT导致阵列中所需的读出放大器和串解码器的总数量更多，从而增加了芯片成本。
发明内容
根据本发明的一个实施例，一种NOR串包括：共享位线的多个可个别寻址的薄膜存储晶体管，其中所述可个别寻址的薄膜晶体管进一步分组为预定数量的片段。在每一片段中，该片段的薄膜存储晶体管共享源极线片段，其与NOR串内的其他片段中的其他源极线片段电隔离。可以沿着在半导体衬底的表面之上并且平行于半导体衬底的表面提供的半导体层的有源条带形成NOR串，其中每个有源条带包括第一导电性的第一和第二半导体子层以及第二导电性的第三半导体子层，其中共享位线和每个源极线片段分别形成在第一和第二半导体子层中。
本发明的NOR串可以进一步包括与第一半导体子层相邻提供的导电子层，以在共享位线中提供低电阻率路径，其可以选择性地电连接到在半导体衬底中形成的电路。
本发明的NOR串可以是在一叠有源条带中、一个在另一个顶部上形成的、多个类似的NOR串之一。所述一叠活动条带依次(in turn)可以是组织为NOR串的阵列的多叠类似有源条带的一部分。
在本发明的NOR串中的每个片段内，可以提供一个或多个预充电晶体管，以连接共享位线和对应的源极线片段。
根据本发明的一个实施例，一种用于形成存储器结构的处理包括：(i)在半导体衬底中形成电路，所述半导体衬底具有平坦表面；(ii)形成多个有源层，连续的有源层通过隔离层彼此隔离，每个有源层包括第一导电类型的第一半导体子层和第二半导体子层、与第一导电类型相反的第二导电类型的第三半导体层；(iii)各向异性地(anisotropically)图案化并蚀刻所述有源层，以沿着基本上垂直于所述平坦表面的第一方向形成从所述有源层的顶部开始的第一沟槽(trenchs)系统，使得每个沟槽沿着基本平行于所述平坦表面的第二方向纵向延伸；(iv)用牺牲(sacrificial)材料填充第一组沟槽；(v)沿着第一方向各向异性地图案化和蚀刻牺牲材料，以形成沿着基本上平行于所述平坦表面且基本上正交于所述第二方向的第三方向纵向延伸的第二组沟槽，由此暴露所述多个有源层中的每一个的一部分；和(vi)各向同性地蚀刻有源层的暴露部分，以去除每个有源层的第一、第二和第三半导体子层的暴露部分。
在一个实施例中，本发明的处理在每个有源层中提供邻近第一半导体子层的导电层，所述导电层对所述各向同性蚀刻步骤具有抵抗力。
在所述各向同性蚀刻步骤之后，所述处理可以进一步包括：(i)选择性地从所述第一组沟槽去除牺牲材料以暴露有源层；(ii)在暴露的有源层上的沟槽中提供电荷捕获层；(iii)用导电材料填充第一沟槽；和(iv)图案化和各向异性地蚀刻所述导电材料，以提供导电材料的支柱(pillar)。
结合附图考虑以下详细描述，可更好地理解本发明。
附图说明
图1(包括图1A和图1B)示出了根据本发明一个实施例的其中在叠层中形成NOR串202-0、202-1、202-2和202-3的电路示意图，一个NOR串在另一个的顶部并且通过绝缘层(未示出)彼此分开。
图2示出了根据本发明一个实施例的在选择性蚀刻以创建源极线片段(导致每个NOR串中的两个单独的串片段A和B)之后的NOR串202-0和202-1的截面图。
图3图示了根据本发明一个实施例的能用来执行本文所述的选择性蚀刻的处理。
具体实施方式
本发明允许存储器阵列由较长的NOR串形成，然而该存储器阵列享有较低泄漏电流的益处，如同它由更短的NOR串形成一样。图1示出了根据本发明一个实施例的其中在叠层中形成NOR串202-0、202-1、202-2和202-3的电路示意图，一个NOR串在另一个的顶部并且通过绝缘层(未示出)彼此分开。如图1所示，每个NOR串被提供通常是N+多晶硅层的共享漏极子层或位线223，所述N+多晶硅层优选被低电阻率金属互连的细窄条带224(例如钨(W)、钴(Co)或其他金属材料或硅化物)捆绑。图1中的每个NOR串还被提供共享源极子层221(通常也是N+多晶硅)、沟道子层222(通常为p-多晶硅)、和导体字线(例如，字线151a和151b)。重要的是，共享位线子层224沿着每个NOR串的整个长度是连续的，而共享源极子层221中的电气连续性在由参考标号227指示的位置处中断，由此将共享源极子层221划分为多个源极线片段。其中共享源极子层中的电连接被中断的位置227可以按照规则的间隔分布。在一些实施例中，如在共同未决非临时申请中所讨论的，在读取、编程或擦除操作期间，共享源极子层221可以通过NOR串中的TFT从共用漏极子层223预充电到预定电压。然后，在读取、编程或擦除操作的剩余期间，电压由寄生电容保持为共享源极子层223中的虚拟电压源。
在图1中，NOR串202-0至202-3的位置227对齐，在每个NOR串中形成片段A和B。每个这样的串片段可以包括例如1,024个TFT，使得可以在8,192个TFT的NOR串中提供八个串片段。每个NOR串中的所有串片段由单一连续、导电共享位线224服务。如图1所示，每个这样的串片段可以合并预充电TFT(例如，预充电TFT 208-CHG-A和208-CHG-B)。这种预充电TFT可以是每个串片段中的专用TFT，或者作为选择可以由串片段中的任何TFT供应。在这些NOR串中，预充电TFT瞬间(momentarily)将位线上的电压传递到它们各自的源极线片段。
本发明的分段的NOR串是通过以下步骤实现的：将每个NOR串的源极子层切割成个别的源极线片段，同时跨越所有串片段、保持沿着NOR串的整个长度的漏极子层或位线224子层的电连续性。在这样的方案下，在读取操作期间，只有包括寻址TFT的源极线片段有助于整个NOR串的源极-漏极泄漏电流，而所有其他源极线片段被预充电到与位线的电压相同的电压，从而消除它们的泄漏电流贡献。虽然分段需要额外的空间来分开相邻的源极线片段，但该空间可能是相当小的面积损失。实现对源极子层进行分段的另一个优点，因为每个源极线片段的电容相应地小于全串源极电容的电容，这导致较低的功耗和较快的预充电。
选择性蚀刻处理可应用于NOR串结构，以在相邻源极线片段之间的位置227处形成间隙(separation)。图2示出了根据本发明一个实施例的在选择性蚀刻以创建源极线片段(导致两个单独的串片段A和B)之后的NOR串202-0和202-1的截面图。图2的结构是通过将选择性蚀刻施加到共同未决非临时申请的图2中所示结构的变型上而得到的。(与共同未决非临时申请中所示的结构不同，钨层224被提供在形成NOR串202-1和202-2的有源层的底部、而不是顶部)。
如图2所示，NOR串202-1和202-2中的每一个由堆叠的有源层形成，每个有源层包括N+子层221(共源极子层)、P-子层222(沟道子层)、N+子层223(公共漏极子层或位线)和导电层224(例如钨)。选择性蚀刻处理切割N+子层221、P-子层222和N+子层223，而不蚀刻到导电层224中。由于导电层224未被蚀刻，所以N+子层223的片段223-A和223-B(即，共享位线)保持电连接。
图2还示出了每个NOR串(例如，NOR串202-0和202-1)的导电层224通过相应的掩埋触点(例如，掩埋触点205-0和205-1)连接到在半导体衬底201中形成的电路。这样的电路可以包括例如读出放大器和电压源。此外，全局互连导体264(例如，全局互连导体208g-s)的系统可以用于将沿着NOR串的局部字线(未示出)连接到半导体衬底201中的电路。如图2中所示，全局互连导体208g-s中的每一个通过掩埋触点(例如，掩埋触点261-0至261-n中的任何一个)连接至半导体衬底201中的对应(即，触点262-0至262-n中的一个)。
图3示出了能执行上述选择性蚀刻的处理。图3是在通过图案化和各向异性蚀刻沿着Y方向纵向延伸且深度贯穿有源层的沟槽、来形成有源层的叠层之后的、NOR串阵列的顶视图。最初，逐子层地接连形成多个有源层，每一有源层通过绝缘层彼此隔离。在形成有源层之后，在有源层上形成绝缘层203。然后对得到的结构进行图案化和各向异性蚀刻。得到的有源层的剩余叠层是图3中被绝缘层203覆盖的部分。然后可以使用例如氧化硅的牺牲材料SAC2填充沟槽。沿着图3中由附图标记227指示的宽度的X方向纵向延伸的第二组沟槽被一直蚀刻到SAC2材料下方，由此暴露子层221、222、223和224的侧边缘。选择性蚀刻然后蚀刻掉暴露的半导体子层221、222和223，同时根本上留下原封不动的(in-tact)导电子层224。此后，如果期望的话，第二组沟槽可随后被绝缘体填充。然后可以选择性地去除牺牲材料SAC2。随后在通过去除SAC2材料得到的这些沟槽中提供存储材料(例如，电荷捕获材料)和局部字线导体。
提供上面的详细描述是为了说明本发明的具体实施例，而不意欲是限制性的。在本发明的范围内的许多变化和修改是可能的。通过所附权利要求来阐述本发明。

Claims (13)

1.一种NOR串，包括共享位线的多个可个别寻址的薄膜存储晶体管，其中所述可个别寻址的薄膜存储晶体管被划分为多个片段，每一片段包括该片段内的薄膜存储晶体管共享的对应源极线片段，并且其中所述源极线片段彼此电气隔离。
2.根据权利要求1所述的NOR串，其中沿着在半导体衬底的表面之上并且平行于半导体衬底的表面提供的半导体层的有源条带形成所述NOR串的存储晶体管，所述有源条带包括第一导电性的第一和第二半导体子层以及第二导电性的第三半导体子层，其中共享位线和每个源极线片段分别形成在第一和第二半导体子层中。
3.根据权利要求2所述的NOR串，还包括与第一半导体子层相邻提供的导电层，所述导电子层在所述共享位线中提供低电阻率路径。
4.根据权利要求3所述的NOR串，其中所述位线选择性地电连接到在所述半导体衬底中形成的电路。
5.根据权利要求2所述的NOR串，其中，所述NOR串是在一叠有源条带中、一个在另一个顶部上形成的多个类似NOR串之一。
6.根据权利要求5所述的NOR串，其中，所述一叠有源条带是通过沿第一方向纵向延伸的沟槽、而彼此分离的多叠类似有源条带中的一个。
7.根据权利要求6所述的NOR串，其中通过在沿着基本上正交于第一方向的第二方向延伸的沟槽中提供的绝缘材料，每个NOR串的相邻源极线片段彼此分离。
8.根据权利要求1所述的NOR串，其中，在每个片段内，提供一个或多个预充电晶体管，以连接所述共享位线和对应的一个源极线片段。
9.如权利要求8所述的NOR串，其中，在对所述NOR串的片段中的薄膜存储晶体管进行读取或编程操作期间，不在所述片段内的所述NOR串的源极线片段和所述共享位线保持在基本相同的电压。
10.一种用于形成存储器结构的处理，包括：
在半导体衬底中形成电路，所述半导体衬底具有平坦表面；
形成多个有源层，连续的有源层通过隔离层彼此隔离，每个有源层包括第一导电类型的第一半导体子层和第二半导体子层、与第一导电类型相反的第二导电类型的第三半导体层；
各向异性地图案化并蚀刻所述有源层，以沿着基本上垂直于所述平坦表面的第一方向从所述有源层的顶部形成第一沟槽系统，使得每个沟槽沿着基本平行于所述平坦表面的第二方向纵向延伸；
用牺牲材料填充第一组沟槽；
沿着第一方向各向异性地图案化和蚀刻牺牲材料，以形成沿着基本上平行于所述平坦表面且基本上正交于所述第二方向的第三方向纵向延伸的第二组沟槽，由此暴露所述多个有源层中的每一个的一部分；和
各向同性地蚀刻有源层的暴露部分，以去除每个有源层的第一、第二和第三半导体子层的暴露部分。
11.根据权利要求10所述的处理，其中所述有源层的每一个还包括与所述第一半导体子层相邻的导电层，所述导电层抵抗所述各向同性蚀刻步骤。
12.如权利要求10所述的处理，在所述各向同性蚀刻步骤之后，还包括：
选择性地从所述第一组沟槽去除牺牲材料以暴露有源层；
在暴露的有源层上的沟槽中提供电荷捕获层；
用导电材料填充第一沟槽；和
图案化和各向异性地蚀刻导电材料，以提供导电材料的支柱。
13.根据权利要求12所述的处理，其中(i)每个有源层的所述第一半导体子层和所述第二半导体子层为NOR串中的薄膜存储晶体管提供共享位线和共享源极线片段；(ii)第三半导体子层为薄膜存储晶体管提供沟道区；和(iii)导电材料的支柱为薄膜存储晶体管提供字线。
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