CN103545281B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN103545281B
CN103545281B CN201310288288.2A CN201310288288A CN103545281B CN 103545281 B CN103545281 B CN 103545281B CN 201310288288 A CN201310288288 A CN 201310288288A CN 103545281 B CN103545281 B CN 103545281B
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matching circuit
semiconductor substrate
grid
chip
transistor
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CN103545281A (zh
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国井彻郎
辻圣
辻圣一
小柳元良
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Rohm Co Ltd
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Mitsubishi Electric Corp
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Abstract

本发明得到不必增加封装件的尺寸，且不必使特性与可靠性劣化就能够提高输出的半导体装置。封装件（1）内设有输入匹配电路（4）与输出匹配电路（5）。在封装件（1）内，输入匹配电路（4）与输出匹配电路（5）之间设有多个晶体管芯片（6）。各晶体管芯片（6）具备：具有长边与比长边短的短边的四边形的半导体衬底（8）；和半导体衬底（8）上分别设置的栅极电极（9）、漏极电极（10）以及源极电极（11）。栅极电极（9）具备：沿半导体衬底（8）的长边方向排列的多个栅极指（9a）；和共同连接到多个栅极指（9a）并且用电线连接到输入匹配电路（4）的栅极焊盘（9b）。漏极电极（10）用电线连接于输出匹配电路（5）。多个晶体管芯片（6）的半导体衬底（8）的长边，从输入匹配电路（4）向着输出匹配电路（5）的输入输出方向倾斜。

Description

半导体装置
技术领域
本发明涉及不必增加封装件的尺寸，且不必使特性与可靠性劣化就能够提高输出的半导体装置。
背景技术
在高输出用的半导体装置中，需要放大被输入的RF信号，输出数W到数百W的功率。需要在这种半导体装置中运用的晶体管的栅极宽度为数mm到数百mm。这样大的栅极宽度的晶体管必须放在仅仅是数mm到数十mm尺寸的封装件中。因此，把1个到4个左右的将数十μm到数百mm的栅极宽度（栅极指长）的栅极指排列数十根到数百根左右的晶体管芯片配置于封装件内。
现有的半导体装置中把多个晶体管芯片的输入一侧与输出一侧的方向对齐并列成一列。此外，也有提案芯片互相前后配置的半导体装置（例如，参照专利文献1）。
此外，在把多个栅极指横向排列为一列的晶体管芯片中，由于从栅极焊盘到各栅极指的线路长度不同，会发生相位差。因此，提案把多个栅极指呈V字型配置，使从栅极焊盘到各栅极指的线路长度相同（例如，参照专利文献2）。由此，能够减少相位差，并且谋求高增益化。
专利文献1：日本特开2007－274181号公报；
专利文献2：日本特开昭61－104674号公报。
为了提高输出必须增加栅极宽度。但是，在把多个晶体管芯片排列成一列的半导体装置中，能够配置的芯片数与芯片的横向宽度受到封装件的横向宽度的限制。因此芯片数一旦增加或者芯片的横向宽度一旦增大，封装件的横向宽度就会增加从而增加成本。此外，在芯片互相前后配置的情况下，为了防止电线的接触只能重复芯片的端部，因此不能充分减小封装件的尺寸。
此外，为了在不增加封装件的尺寸的前提下增加栅极宽度，可以增加栅极指的长度（单位栅极宽度），或者缩小指的间隔而增加根数。但是，使栅极指变长就会降低增益。此外，一旦缩小指的间隔就会集中热量，使运行时的沟道温度升高。这样的结果会导致特性与可靠性劣化。
此外，在把多个栅极指横向排列为一列的情况下，运行时的发热区域集中于配置指的长方形的区域。与此相对，如果多个栅极指呈V字型配置可以扩大发热区域。但是在邻接的晶体管单元的边界中，彼此晶体管单元的端部的栅极指邻接。因此在单元边界的部分会集中热量。而且，由于从栅极焊盘到各栅极指的线路长度必须相同，因此不能够再减少邻接的栅极指重叠的部分。因此不能充分减少热量的集中，从而使温度上升并且特性与可靠性劣化。
发明内容
本发明为了解决上述课题而构思，其目的在于得到不必增加封装件的尺寸，且不必使特性与可靠性劣化就能够提高输出的半导体装置。
本发明涉及的半导体装置的特征在于，具备：封装件；所述封装件内设置的输入匹配电路与输出匹配电路；以及多个晶体管芯片，在所述封装件内，所述多个晶体管芯片设置在所述输入匹配电路与所述输出匹配电路之间，各晶体管芯片具备具有长边与比所述长边短的短边的四边形的半导体衬底、和所述半导体衬底上分别设置的栅极电极，漏极电极以及源极电极，所述栅极电极具备沿所述半导体衬底的所述长边的方向排列的多个栅极指、和共同连接到所述多个栅极指并且用电线连接于所述输入匹配电路的栅极焊盘，所述漏极电极用电线连接于所述输出匹配电路，所述多个晶体管芯片的所述半导体衬底的所述长边，从所述输入匹配电路向着所述输出匹配电路的输入输出方向倾斜。
依据本发明，不必增加封装件的尺寸，且不必使特性与可靠性劣化就能够提高输出。
附图说明
图1是示出本发明实施方式1涉及的半导体装置的平面图；
图2是示出沿着图1中的I－II的剖面图；
图3是示出放大图1中的晶体管芯片的平面图；
图4是示出晶体管芯片的平面图；
图5是示出比较例涉及的半导体装置的平面图；
图6是示出比较例涉及的晶体管芯片的平面图；
图7是示出本发明实施方式1涉及的晶体管芯片的变形例1的平面图；
图8是示出本发明实施方式1涉及的晶体管芯片的变形例2的平面图；
图9是示出本发明实施方式2涉及的半导体装置的平面图；
图10是示出放大图9中的晶体管芯片的平面图；
图11是示出本发明实施方式3涉及的半导体装置的平面图；
图12是示出放大图11的一部分的平面图；
图13是示出放大本发明实施方式4涉及的半导体装置的一部分的平面图。
具体实施方式
根据附图，讲述本发明的实施方式涉及的半导体装置。相同或者对应的构成要素标注相同的符号，有省略反复说明的情况。
实施方式1
图1是示出本发明实施方式1涉及的半导体装置的平面图。图2是示出沿着图1中的I－II的剖面图。平面视图中大致为四边形的封装件1的彼此相向的边分别设置有输入RF信号的RF输入端子2和输出RF信号的RF输出端子3。封装件1内设有输入匹配电路4以及输出匹配电路5，分别与RF输入端子2及RF输出端子3连接。在封装件1内输入匹配电路4与输出匹配电路5之间设有多个晶体管芯片6。封装件1的上部被盖7覆盖。
图3是示出放大图1中的晶体管芯片的平面图。图4是示出本发明实施方式1涉及的晶体管芯片的平面图。各晶体管芯片6具备：具有长边与比长边短的短边的四边形的半导体衬底8；和半导体衬底8上分别设置的栅极电极9、漏极电极10以及源极电极11。
栅极电极9具备：半导体衬底8的长边方向排列的多个栅极指9a；和与多个栅极指9a共同连接的栅极焊盘9b。漏极电极10具备：半导体衬底8的长边方向排列的多个漏极指10a；和与多个漏极指10a共同连接的漏极焊盘10b。源极电极11具备：半导体衬底8的长边方向排列的多个源极指11a；和与多个源极指11a共同连接的源极焊盘11b。栅极焊盘9b用金电线12连接到输入匹配电路4，漏极电极10的漏极焊盘10b用金电线13连接到输出匹配电路5。
与栅极电极9连接的芯片连接用栅极焊盘9c设置于短边的旁边。邻接的晶体管芯片6的芯片连接用栅极焊盘9c用金电线14互相连接。
本实施方式中多个晶体管芯片6的半导体衬底8的长边从输入匹配电路4向着输出匹配电路5的输入输出方向倾斜。在这里，输入匹配电路4以及输出匹配电路5分别具有芯片内的按每个晶体管单元已取得匹配的图案，那些图案用电线按每个单元连接，合成竞赛（tournament）型。因此，即使多个晶体管芯片6倾斜，在保持对称性的同时也可以在芯片内按每个封装件合成。此外，在保持对称性的同时也能芯片合成。
接下来，与比较例比较说明本实施方式的效果。图5是示出比较例涉及的半导体装置的平面图。图6是示出比较例涉及的晶体管芯片的平面图。在比较例中尺寸3.2mm×0.56mm的4个晶体管芯片6向着输入一侧与输出一侧的方向对齐排成一列。
另一方面，在本实施方式中4个晶体管芯片6配置为相对于输入输出方向45度倾斜。由此，可以不必增加封装件的尺寸，就能够使横向芯片尺寸扩大到（3.2－0.56/）×mm=3.97mm。这个结果，本实施方式不必改变栅极指的长度（单位栅极宽度）、指的间隔而增加指的根数，输出能够比比较例提高约24%。因此可以不必增加封装件的尺寸，且不必使特性与可靠性劣化就能够提高输出。
图7是示出本发明实施方式1涉及的晶体管芯片的变形例1的平面图。与实施方式1的图4的芯片相比，横向的芯片的尺寸与栅极指9a的根数相同，各栅极指9a的长度（单位栅极宽度）变短。由此与比较例的图6的芯片相比，栅极指9a的长度变短，并且增加根数能够使总栅极宽度相同。因此以与比较例相同的输出能够提高增益。
图8是示出本发明实施方式1涉及的晶体管芯片的变形例2的平面图。与实施方式1的图4的芯片相比，横向的芯片尺寸与各栅极指9a的长度（单位栅极宽度）相同，栅极指9a的根数变少。由此与比较例的图6的芯片相比，栅极指9a的单位栅极宽度以及根数相同，总栅极宽度相同，并且能够扩大各栅极指9a的间隔。因此，以与比较例相同的输出能够提高散热性。
此外，在本实施方式中，经由连接用栅极焊盘9b连接邻接的晶体管芯片6，多个晶体管芯片6的方向必须互相不同。但是没有必要连接芯片的情况下，多个晶体管芯片6也可以向着相同方向倾斜配置。
实施方式2
图9是示出本发明实施方式2涉及的半导体装置的平面图。图10是示出放大图9中的晶体管芯片的平面图。晶体管芯片6的形状并不是一般的长方形，而是平行四边形。而且多个晶体管芯片6的半导体衬底8的短边与输入输出方向平行。
在长方形的晶体管芯片6中，如果在芯片端部设置芯片连接用栅极焊盘9c，设置栅极指9a的区域就会减少。与此相对，在本实施方式中因为能够在芯片间的空隙区域中设置芯片连接用栅极焊盘9c，所以能够扩大设置栅极指9a的区域的面积。因此，不必增加封装件的尺寸就能够进一步提高输出。
晶体管芯片6的半导体衬底8是SiC，在其上设有GaN类HEMT。在这里，在与面方位不同的方向切割半导体衬底8的情况下，在芯片端部施加应力时沿面方位会发生断裂。因此，使用面方位60度的方向的六法晶的SiC衬底，长边解理面为＜－1100＞与＜1－100＞时，短边为相对于长边60度倾斜，沿解理面＜－1010＞与＜10－10＞，或者解理面＜0－110＞与＜01－10＞切割。这样一来能够抑制被施加应力时断裂的发生。
此外，MMIC的最后级的放大器特别要求高的输出。因此，如果在MMIC的最后级中适用实施方式1、2涉及的半导体装置就会很有效果。此外，半导体衬底8利用SiC形成的晶体管芯片6的耐电压性、允许电流密度高，所以能够小型化。使用这种小型化的芯片能够使装入这种芯片的半导体装置也小型化。此外，因为芯片的耐热性高，所以能够使散热器的散热片小型化，因为能够将水冷部气冷化，所以能够使半导体装置更加小型化。此外，因为芯片的功率损耗降低而高效率，所以能够使半导体装置高效率化。
实施方式3
图11是示出本发明实施方式3涉及的半导体装置的平面图。图12是示出放大图11的一部分的平面图。这种半导体装置是具有放大输入信号的前级晶体管部和进一步放大输出信号的最后级的晶体管部的MMIC。
在半导体衬底8上设置有多个晶体管单元15。在各晶体管单元15中斜线状配置多个栅极指9a。在邻接的晶体管单元15的边界中互相的晶体管单元15的端部的栅极指9a错开。因此在单元边界部分不会集中热量，能够防止温度上升带来的特性与可靠性的劣化。根据运用模拟的简易热阻计算结果，本实施方式与多个栅极指9a横向排为一列的装置相比，热阻值能够降低约为20%左右。
因为如此优越的散热性，所以不必改变每个栅极宽度的热阻，使栅极指的间隔变窄，增加指的根数就能够放大总栅极宽度。因此，不必增加封装件的尺寸，且不必使特性与可靠性劣化就能够提高输出。
此外，本实施例中在每一个单元中改变了栅极指9a的排列，但也可以在每多个单元中改变排列，也可以在一个单元内多次改变排列。
实施方式4
图13是示出放大本发明实施方式4涉及的半导体装置的一部分的平面图。与实施方式3同样地在半导体衬底8上设有多个晶体管单元15。多个栅极指9a的指方向稍微错开，将晶体管单元15的中央错开的朝向反方向折回而V字型配置。
从栅极焊盘9b到中央的栅极指9a的路线长度比从栅极焊盘9b到端部的栅极指9a的路线长度长。如此，多个栅极指9a配置为纵向长的V字型，与从栅极焊盘9b到各栅极指9a的路线长度相同的V字型配置相比，减少了邻接的栅极指9a的重叠部分。因此能够充分减少热量的集中。
因为如此优越的散热性，所以不必改变每个栅极宽度的热阻，使栅极指9a的间隔变窄，增加指的根数，能够扩大总栅极宽度。因此，不必增加封装件的尺寸，且不必使特性与可靠性劣化就能够提高输出。
此外，不必改变芯片尺寸与总栅极宽度，使指间隔变窄，能够使单位栅极宽度变小。由此，不必增加封装件的尺寸，且不必使特性与可靠性劣化就能够提高增益。
此外，在本实施方式中将错开栅极指9a的朝向在单元中央沿反方向折回，但也可以在每多个单元中折回，也可以在一个单元内多次折回。按照MMIC全部的布局也可以弹性地改变折回的周期，可以高自由度设计。
此外，在实施方式3、4中，也在漏极一侧设置源极焊盘11b能够减少源极电感，即使在漏极一侧不设置源极焊盘11b，仅在栅极一侧设置源极焊盘11b也可。此外，通过将实施方式3、4的构造与实施方式1、2的装置相结合，能进一步提高输出。
符号说明：
1封装件；4输入匹配电路；5输出匹配电路；6晶体管芯片；8半导体衬底；9栅极电极；9a栅极指；9b栅极焊盘；10漏极电极；11源极电极；15晶体管单元。

Claims (6)

1.一种半导体装置，其特征在于，具备：
封装件；
所述封装件内设置的输入匹配电路与输出匹配电路；以及
多个晶体管芯片，在所述封装件内，所述多个晶体管芯片设置在所述输入匹配电路与所述输出匹配电路之间，
各晶体管芯片具备具有长边与比所述长边短的短边的四边形的半导体衬底、和所述半导体衬底上分别设置的栅极电极，漏极电极以及源极电极，
所述栅极电极具备沿所述半导体衬底的所述长边的方向排列的多个栅极指、和共同连接到所述多个栅极指并且用电线连接于所述输入匹配电路的栅极焊盘，
所述漏极电极用电线连接于所述输出匹配电路，
所述多个晶体管芯片的所述半导体衬底的所述长边，从所述输入匹配电路向着所述输出匹配电路的输入输出方向倾斜。
2.如权利要求1所述的半导体装置，其特征在于，
各晶体管芯片还具有设置于所述短边的旁边并与所述栅极电极连接的芯片连接用栅极焊盘，邻接的晶体管芯片的所述芯片连接用栅极焊盘用电线互相连接，
所述多个晶体管芯片的所述半导体衬底的所述短边，与输入输出方向平行。
3.如权利要求2所述的半导体装置，其特征在于，
所述短边沿所述半导体衬底的解理面。
4.如权利要求3所述的半导体装置，其特征在于，
所述半导体衬底是SiC；
所述短边相对于所述长边60度倾斜。
5.如权利要求1～4的任一项所述的半导体装置，其特征在于，
所述半导体衬底上设有多个晶体管单元；
在各晶体管单元中斜线状设有所述多个栅极指；
在邻接的晶体管单元的边界中互相的晶体管单元的端部的栅极指错开。
6.如权利要求1～4的任一项所述的半导体装置，其特征在于，
所述多个栅极指配置成V字型；
从所述栅极焊盘到中央的栅极指的路线长度，比从所述栅极焊盘到端部的栅极指的路线长度长。
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JP2014017444A (ja) 2014-01-30
DE102013208142A1 (de) 2014-01-16
TW201403819A (zh) 2014-01-16
TWI484636B (zh) 2015-05-11
JP5983117B2 (ja) 2016-08-31
US20140014969A1 (en) 2014-01-16
CN103545281A (zh) 2014-01-29

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