JP2014017444A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2014017444A JP2014017444A JP2012155501A JP2012155501A JP2014017444A JP 2014017444 A JP2014017444 A JP 2014017444A JP 2012155501 A JP2012155501 A JP 2012155501A JP 2012155501 A JP2012155501 A JP 2012155501A JP 2014017444 A JP2014017444 A JP 2014017444A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000003776 cleavage reaction Methods 0.000 claims description 3
- 230000007017 scission Effects 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000002542 deteriorative effect Effects 0.000 abstract description 7
- 230000000052 comparative effect Effects 0.000 description 11
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】パッケージ1内に入力整合回路4及び出力整合回路5が設けられている。パッケージ1内において、入力整合回路4と出力整合回路5の間に複数のトランジスタチップ6が設けられている。各トランジスタチップ6は、長辺と長辺より短い短辺を持つ四角形の半導体基板8と、半導体基板8上にそれぞれ設けられたゲート電極9、ドレイン電極10、及びソース電極11とを有する。ゲート電極9は、半導体基板8の長辺の方向に並べられた複数のゲートフィンガー9aと、複数のゲートフィンガー9aに共通に接続され入力整合回路4にワイヤ接続されたゲートパッド9bとを有する。ドレイン電極10は出力整合回路5にワイヤ接続されている。複数のトランジスタチップ6の半導体基板8の長辺は、入力整合回路4から出力整合回路5に向かう入出力方向に対して斜めである。
【選択図】図1
Description
図1は、本発明の実施の形態1に係る半導体装置を示す平面図である。図2は、図1のI−IIに沿った断面図である。平面視で略四角形状のパッケージ1の互いに対向する辺に、それぞれRF信号を入力するRF入力端子2と、RF信号を出力するRF出力端子3とが設けられている。パッケージ1内に入力整合回路4及び出力整合回路5が設けられ、それぞれRF入力端子2及びRF出力端子3に接続されている。パッケージ1内において、入力整合回路4と出力整合回路5の間に複数のトランジスタチップ6が設けられている。パッケージ1の上部は蓋7で覆われている。
図9は、本発明の実施の形態2に係る半導体装置を示す平面図である。図10は、図9のトランジスタチップを拡大した平面図である。トランジスタチップ6の形状は通常の長方形ではなく、平行四辺形である。そして、複数のトランジスタチップ6の半導体基板8の短辺は、入出力方向に対して平行である。
図11は、本発明の実施の形態3に係る半導体装置を示す平面図である。図12は、図11の一部を拡大した平面図である。この半導体装置は、入力信号を増幅する前段トランジスタ部と、その出力信号を更に増幅する最終段トランジスタ部とを有するMMICである。
図13は、本発明の実施の形態4に係る半導体装置の一部を拡大した平面図である。実施の形態3と同様に半導体基板8上に複数のトランジスタセル15が設けられている。複数のゲートフィンガー9aは、フィンガー方向に少しずつずらし、トランジスタセル15の中央でずらす向きを反対方向に折り返してVの字型に配置されている。
4 入力整合回路
5 出力整合回路
6 トランジスタチップ
8 半導体基板
9 ゲート電極
9a ゲートフィンガー
9b ゲートパッド
10 ドレイン電極
11 ソース電極
15 トランジスタセル
Claims (8)
- パッケージと、
前記パッケージ内に設けられた入力整合回路及び出力整合回路と、
前記パッケージ内において、前記入力整合回路と前記出力整合回路の間に設けられた複数のトランジスタチップとを備え、
各トランジスタチップは、長辺と前記長辺より短い短辺を持つ四角形の半導体基板と、前記半導体基板上にそれぞれ設けられたゲート電極、ドレイン電極、及びソース電極とを有し、
前記ゲート電極は、前記半導体基板の前記長辺の方向に並べられた複数のゲートフィンガーと、前記複数のゲートフィンガーに共通に接続され前記入力整合回路にワイヤ接続されたゲートパッドとを有し、
前記ドレイン電極は前記出力整合回路にワイヤ接続され、
前記複数のトランジスタチップの前記半導体基板の前記長辺は、前記入力整合回路から前記出力整合回路に向かう入出力方向に対して斜めであることを特徴とする半導体装置。 - 各トランジスタチップは、前記短辺の近傍に設けられ前記ゲート電極に接続されたチップ連結用ゲートパッドを更に有し、
隣接するトランジスタチップの前記チップ連結用ゲートパッドは互いにワイヤ接続され、
前記複数のトランジスタチップの前記半導体基板の前記短辺は、前記入出力方向に対して平行であることを特徴とする請求項1に記載の半導体装置。 - 前記短辺は前記半導体基板の劈開面に沿っていることを特徴とする請求項2に記載の半導体装置。
- 前記半導体基板はSiCであり、
前記短辺は前記長辺に対して60度傾いていることを特徴とする請求項3に記載の半導体装置。 - 前記半導体基板上に複数のトランジスタセルが設けられ、
各トランジスタセルにおいて前記複数のゲートフィンガーが斜め直線状に配置され、
隣接するトランジスタセルの境界において互いのトランジスタセルの端のゲートフィンガーがずれていることを特徴とする請求項1〜4の何れか1項に記載の半導体装置。 - 前記複数のゲートフィンガーはVの字型に配置され、
前記ゲートパッドから中央のゲートフィンガーまでの線路長が、前記ゲートパッドから端のゲートフィンガーまでの線路長よりも長いことを特徴とする請求項1〜4の何れか1項に記載の半導体装置。 - 半導体基板と、
前記半導体基板上に設けられた複数のトランジスタセルとを備え、
各トランジスタセルは、斜め直線状に配置された複数のゲートフィンガーを有し、
隣接するトランジスタセルの境界において互いのトランジスタセルの端のゲートフィンガーがずれていることを特徴とする半導体装置。 - 半導体基板と、
前記半導体基板上に設けられた複数のトランジスタセルとを備え、
各トランジスタセルは、Vの字型に配置された複数のゲートフィンガーと、前記複数のゲートフィンガーに電気的に接続されたゲートパッドとを有し、
前記ゲートパッドから中央のゲートフィンガーまでの線路長が、前記ゲートパッドから端のゲートフィンガーまでの線路長よりも長いことを特徴とする半導体装置。
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