TW201403819A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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TW201403819A
TW201403819A TW102108782A TW102108782A TW201403819A TW 201403819 A TW201403819 A TW 201403819A TW 102108782 A TW102108782 A TW 102108782A TW 102108782 A TW102108782 A TW 102108782A TW 201403819 A TW201403819 A TW 201403819A
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gate
transistor
matching circuit
semiconductor substrate
semiconductor device
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TW102108782A
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TWI484636B (zh
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Tetsuo Kunii
Seiichi Tsuji
Motoyoshi Koyanagi
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Mitsubishi Electric Corp
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Abstract

〔課題〕本發明係可獲得能在不會增加封裝尺寸、不致使特性與可靠度劣化之情況下，可提升輸出的半導體裝置。〔解決手段〕在封裝1內設置輸入匹配電路4與輸出匹配電路5。在封裝1內，於輸入匹配電路4與輸出匹配電路5之間設置複數電晶體晶片6。各電晶體晶片6係包括：具有長邊與較短於長邊之短邊的四角形半導體基板8、以及在半導體基板8上分別設置的閘極電極9、汲極電極10、及源極電極11。閘極電極9係包括：朝半導體基板8之長邊方向排列的複數閘極指9a、以及共通連接於複數閘極指9a且焊線連接於輸入匹配電路4的閘極墊片9b。汲極電極10係焊線連接於輸出匹配電路5。複數電晶體晶片6的半導體基板8之長邊，係相對於從輸入匹配電路4朝輸出匹配電路5的輸出入方向呈傾斜。

Description

半導體裝置
本發明係關於能在不會增加封裝尺寸、且不致使特性與可靠度劣化的情況下，提升輸出的半導體裝置。
高輸出用半導體裝置，所輸入的RF信號必需放大後再輸出數W至數百W的功率。該半導體裝置所使用電晶體的閘極寬度必需係數mm至數百mm。必需將僅此大小程度閘極寬度的電晶體放入僅有數mm至數十mm尺寸的封裝內。所以，在封裝內配置1個至4個左右，由數十μm至數百mm閘極寬度(閘極指長)的閘極指(gate finger)，呈數十條至百條程度排列的電晶體晶片。
習知半導體裝置中，複數電晶體晶片係整合輸入側與輸出的方向並呈一排排列。又，亦有晶片呈相互前後配置的半導體裝置(例如參照專利文獻1)。
再者，複數閘極指呈橫一排排列的電晶體晶片，因為閘極墊片(gate pad)距各閘極指的線路長不同，因而會產生相位差。所以，有提案將複數閘極指呈V字配置，俾使閘極墊片距各閘極指的線路長相同(例如參照專利文獻2)。藉此，可達相位差降低、及高增益化。
[先行技術文獻] [專利文獻]
[專利文獻1]日本專利特開2007-274181號公報
[專利文獻2]日本專利特開昭61-104674號公報
為提升輸出便必需增加閘極寬度。但是，由複數電晶體晶片呈一排排列的半導體裝置，就能配置的晶片數與晶片的橫寬會受到封裝的橫寬限制。所以，若增加晶片數或增大晶片的橫寬，封裝的橫寬便會增加導致成本提高。又，當晶片呈相互前後配置時，為防止焊線的接觸，便僅有晶片的端部能重複而已，因而無法充分減小封裝尺寸。
再者，為能在不會增加封裝尺寸的情況下增加閘極寬度，亦可加長閘極指的長度(單位閘極寬度)、或縮小指間隔並增加條數。但是，若加長閘極指便會導致增益降低。又，若縮小指間隔，便會導致熱集中造成動作時的通道溫度上升。結果，導致特性與可靠度劣化。
再者，複數閘極指呈橫一排排列時，動作時的發熱區域會集中於指配置的長方形區域中。相對於此，若將複數閘極指呈V形配置便會導致發熱區域擴大。但是，因為在鄰接電晶體單元的邊界處相互電晶體單元的端部之閘極指相鄰接，因而在單元邊界部分處會出現熱集中。然而，因為必需將閘極墊片距各閘極指間之線路長設為相同，因而相鄰接閘極指的重疊部分便無法達此程度以上的更減少。所以，無法充分降 低熱集中，會導致溫度上升，造成特性與可靠度劣化。
本發明係為解決如上述課題而完成，其目的在於獲得能在不會增加封裝尺寸、不致使致特性與可靠度劣化的情況下，提升輸出的半導體裝置。
本發明的半導體裝置係包括：封裝、在上述封裝內設置的輸入匹配電路及輸出匹配電路、以及在上述封裝內設置於上述輸入匹配電路與上述輸出匹配電路間的複數電晶體晶片；其特徵在於：各電晶體晶片係包括：具有長邊與較短於上述長邊之短邊的四角形半導體基板、以及分別設置於上述半導體基板上的閘極電極、汲極電極、及源極電極；上述閘極電極係包括：排列於上述半導體基板的上述長邊方向上之複數閘極指、以及共通連接於上述複數閘極指且焊線連接於上述輸入匹配電路的閘極墊片；上述汲極電極係焊線連接於上述輸出匹配電路；上述複數電晶體晶片的上述半導體基板之上述長邊係相對於從上述輸入匹配電路朝上述輸出匹配電路的輸出入方向呈傾斜。
利用本發明可提供能在不會增加封裝尺寸、不致使特性與可靠度劣化的情況下，提升輸出。
1‧‧‧封裝
2‧‧‧RF輸入端子
3‧‧‧RF輸出端子
4‧‧‧輸入匹配電路
5‧‧‧輸出匹配電路
6‧‧‧電晶體晶片
7‧‧‧蓋
8‧‧‧半導體基板
9‧‧‧閘極電極
9a‧‧‧閘極指
9b‧‧‧閘極墊片
9c‧‧‧晶片連結用閘極墊片
10‧‧‧汲極電極
10a‧‧‧汲極指
10b‧‧‧汲極墊片
11‧‧‧源極電極
11a‧‧‧源極指
11b‧‧‧源極墊片
12‧‧‧金焊線
13‧‧‧金焊線
15‧‧‧電晶體單元
圖1係本發明實施形態1的半導體裝置平面圖。
圖2係沿圖1之I-II的剖視圖。
圖3係圖1的電晶體晶片之放大平面圖。
圖4係電晶體晶片的平面圖。
圖5係比較例的半導體裝置平面圖。
圖6係比較例的電晶體晶片平面圖。
圖7係本發明實施形態1的電晶體晶片變化例1之平面圖。
圖8係本發明實施形態1的電晶體晶片變化例2之平面圖。
圖9係本發明實施形態2的半導體裝置平面圖。
圖10係圖9的電晶體晶片之放大平面圖。
圖11係本發明實施形態3的半導體裝置平面圖。
圖12係圖11的部分放大平面圖。
圖13係本發明實施形態4的半導體裝置之部分放大平面圖。
針對本發明實施形態的半導體裝置，參照圖式進行說明。相同或對應的構成要件便賦予相同元件符號，並有省略重複說明的情況。
實施形態1.
圖1所示係本發明實施形態1的半導體裝置平面圖。圖2所示係沿圖1的I-II之剖視圖。在俯視呈略四角形狀的封裝1之相對向的邊上，分別設置：輸入RF信號的RF輸入端子2、及輸出RF信號的RF輸出端子3。在封裝1內設有輸入匹配電路4及輸出匹配電路5，分別連接於RF輸入端子2與RF輸出端子3。在封裝1內，於輸入匹配電路4與輸出匹配電路5之間設置複數電晶體晶片6。封裝1的上部覆蓋著蓋7。
圖3所示係圖1的電晶體晶片之放大平面圖。圖4所示係本發明實施形態1的電晶體晶片平面圖。各電晶體晶片6係包括：具長邊與較短於長邊之短邊且呈四角形的半導體基板8、以及分別設置於半導體基板8上的閘極電極9、汲極電極10、及源極電極11。
閘極電極9係包括：朝半導體基板8的長邊方向排列之複數閘極指9a、以及共通連接於複數閘極指9a的閘極墊片9b。汲極電極10係包括：朝半導體基板8的長邊方向排列之複數汲極指10a、以及共通連接於複數汲極指10a的汲極墊片10b。源極電極11係包括：朝半導體基板8的長邊方向排列之複數源極指11a、以及共通連接於複數源極指11a的源極墊片11b。閘極墊片9b係利用金焊線12連接於輸入匹配電路4，而汲極電極10的汲極墊片10b係利用金焊線13連接於輸出匹配電路5。
閘極電極9所連接的晶片連結用閘極墊片9c係設置於短邊附近。相鄰接電晶體晶片6的晶片連結用閘極墊片9c相互間係利用金焊線14連接。
本實施形態中，複數電晶體晶片6的半導體基板8之長邊，係相對於從輸入匹配電路4朝輸出匹配電路5的輸出入方向呈傾斜。此處，輸入匹配電路4及輸出匹配電路5係依晶片內的每個電晶體單元設有取得匹配的圖案，該等圖案係依每個單元施行焊線連接，而合成為競賽式(tournament type)。所以，即便複數電晶體晶片6呈傾斜，仍可在保持對稱性狀態下，進行晶片內的每個單元之合成。又，亦可進行保持對稱性 狀態的晶片合成。
接著，針對本實施形態的效果與比較例進行比較說明。圖5所示係比較例的半導體裝置平面圖。圖6所示係比較例的電晶體晶片平面圖。比較例中，尺寸3.2mm×0.56mm的4個電晶體晶片6係整合輸入側與輸出側的方向呈一列排開。
另一方面，本實施形態中，4個電晶體晶片6相對於輸出入方向呈45度傾斜配置。藉此，便可在不致增加封裝尺寸情況下，將橫向晶片尺寸擴大(3.2-0.56/√2)×√2mm=3.97mm。結果，本實施形態係可在不會改變閘極指長度(單位閘極寬度)與指間隔的情況下，增加指支數，俾使輸出較比較例提升約24%。所以，能在不會增加封裝尺寸、不致使特性與可靠度劣化的情況下，提升輸出。
圖7所示係本發明實施形態1的電晶體晶片變化例1之平面圖。相較於實施形態1的圖4之晶片，橫方向的晶片尺寸與閘極指9a支數係相同，但各閘極指9a的長度(單位閘極寬度)較短。藉此，相較於比較例的圖6之晶片，能在縮短閘極指9a長度的情況下，增加支數而使總閘極寬度相同。所以，依與比較例相同的輸出便能提升增益。
圖8所示係本發明實施形態1的電晶體晶片變化例2之平面圖。相較於實施形態1的圖4之晶片，橫向晶片尺寸與各閘極指9a的長度(單位閘極寬度)相同，但閘極指9a的支數較少。藉此，相較於比較例的圖6之晶片，在將閘極指9a的單位閘極寬度與支本數設為相同，而使總閘極寬度相同之情況下，能擴大各閘極指9a的間隔。所以，依比較例的相同輸 出便能提升散熱性。
另外，本實施形態中，因為相鄰接電晶體晶片6係經由連結用閘極墊片9b相連結，因而複數電晶體晶片6的朝向必需互異。但是，當晶片沒有必要連結的情況，複數電晶體晶片6亦可朝相同方向傾斜配置。
實施形態2.
圖9所示係本發明實施形態2的半導體裝置平面圖。圖10所示係圖9的電晶體晶片之放大平面圖。電晶體晶片6的形狀並非通常的長方形，而是平行四邊形。所以，複數電晶體晶片6的半導體基板8之短邊係相對於輸出入方向呈平行。
長方形電晶體晶片6係若在晶片端部設置晶片連結用閘極墊片9c，便會導致設置閘極指9a之區域的面積減少。相對於此，本實施形態，因為可在晶片間的間隙區域設置晶片連結用閘極墊片9c，因而可放大設置閘極指9a之區域的面積。所以，能在不致增加封裝尺寸的情況下，更加提升輸出。
電晶體晶片6的半導體基板8係SiC，在其上面設有GaN系HEMT。此處，朝面方位的不同方向切斷半導體基板8時，當對晶片端部施加壓力時會沿面方位發生龜裂。所以，當使用面方位為60度方向的六方晶SiC基板，且長邊的劈裂面為<-1100>與<1-100>時，短邊相對於長邊呈60度傾斜沿劈裂面<-1010>與<10-10>、或劈裂面<0-110>與<01-10>進行切斷。藉此，可抑制施加壓力時的龜裂發生。
另外，對MMIC的最終段放大器特別要求高輸出。所以，若MMIC的最終段係使用實施形態1、2的半導體裝置， 便特別有效。又，半導體基板8係由SiC所形成的電晶體晶片6，因為耐電壓性與容許電流密度較高，因而可小型化。藉由使用該經小型化的晶片，即便組裝該晶片的半導體裝置亦仍小型化。又，因為晶片的耐熱性較高，因而可將散熱體的散熱鰭片小型化，因為水冷部能空冷化，因而半導體裝置可更加小型化。又，因為晶片的功率損失低、屬於高效率，因而半導體裝置能高效率化。
實施形態3.
圖11所示係本發明實施形態3的半導體裝置平面圖。圖12所示係圖11的部分放大平面圖。該半導體裝置係包括：放大輸入信號的前段電晶體部、與更加放大該輸出信號的最終段電晶體部之MMIC。
在半導體基板8上設置複數電晶體單元15。各電晶體單元15中，複數閘極指9a呈傾斜直線狀配置。在相鄰接電晶體單元15的邊界，電晶體單元15之端的閘極指9a相互錯開。所以，在單元邊界部分處不會有熱集中，俾可防止因溫度上升造成的特性與可靠度劣化。根據使用模擬的簡易熱阻計算結果，本實施形態相較於由複數閘極指9a呈橫一排排列的裝置之下，熱阻值可降低約20%程度。
依此因為散熱性優異，因而能在不致改變閘極每單位寬度的熱阻之情況下，縮小閘極指間隔，可增加指支數，俾能擴大總閘極寬度。所以，能在不致增加封裝尺寸、且不會使特性與可靠度劣化之情況下，提升輸出。
另外，本實施例雖依每1單元改變閘極指9a的排 列，但亦可依每複數單元變更排列，亦可在1個單元內改變複數次排列。
實施形態4.
圖13所示係本發明實施形態4的半導體裝置之部分放大平面圖。與實施形態3同樣的，在半導體基板8上設置複數電晶體單元15。複數閘極指9a係朝指方向稍微逐次錯開，在電晶體單元15的中央處，將錯開的方向朝相反方向返折而呈V字形配置。
閘極墊片9b距中央處閘極指9a間的線路長，係較長於閘極墊片9b距端的閘極指9a間之線路長。依此藉由複數閘極指9a呈縱長V字形配置，相較於閘極墊片9b距各閘極指9a的線路長為相同之V字形配置，能減輕相鄰接閘極指9a的重疊部分。所以，可充分降低熱集中。
依此因為散熱性優異，因而能在不致改變閘極每單位寬度的熱阻的情況下，縮小閘極指9a的間隔，可增加指支數，俾能擴大總閘極寬度。所以，能在不致增加封裝尺寸、且不會使特性與可靠度劣化之情況下，提升輸出。
再者，亦能在不致改變晶片尺寸與總閘極寬度的情況下，縮小指間隔，而縮小單位閘極寬度。藉此，可在不會增加封裝尺寸、不致使特性與可靠度劣化的情況下，提升增益。
另外，本實施形態中，閘極指9a錯開的方向在單元中央處朝相反方向返折，但亦可依每複數單元返折，亦可在1個單元內進行複數次返折。配合MMIC全體的佈局，能彈性地改變返折週期，可進行高自由度的設計。
再者，實施形態3、4中，在汲極側設置源極墊片11b而降低源極電感，但亦可在汲極側並未設置源極墊片11b，而是僅在閘極側設置源極墊片11b。又，藉由將實施形態3、4的構造組合於實施形態1、2的裝置中，便可更加提升輸出。
1‧‧‧封裝
2‧‧‧RF輸入端子
3‧‧‧RF輸出端子
4‧‧‧輸入匹配電路
5‧‧‧輸出匹配電路
6‧‧‧電晶體晶片

Claims (8)

  1. 一種半導體裝置，包括：封裝；輸入匹配電路及輸出匹配電路，其乃設置於上述封裝內；以及複數電晶體晶片，其乃在上述封裝內，設置於上述輸入匹配電路與上述輸出匹配電路之間；其特徵在於：各電晶體晶片係包括：半導體基板，其乃具有長邊、與較短於上述長邊之短邊的四角形；以及閘極電極、汲極電極及源極電極，其乃分別設置於上述半導體基板上；上述閘極電極係包括：複數閘極指，其乃朝上述半導體基板的上述長邊方向排列；以及閘極墊片，其乃共通連接於上述複數閘極指，且焊線連接於上述輸入匹配電路；上述汲極電極係焊線連接於上述輸出匹配電路；上述複數電晶體晶片的上述半導體基板之上述長邊，係相對於從上述輸入匹配電路朝上述輸出匹配電路的輸出入方向呈傾斜。
  2. 如申請專利範圍第1項之半導體裝置，其中，各電晶體晶片係更進一步包括設置於上述短邊附近且連接於上述閘極 電極的晶片連結用閘極墊片；相鄰接電晶體晶片的上述晶片連結用閘極墊片係相互焊線連接；上述複數電晶體晶片的上述半導體基板之上述短邊，係相對於上述輸出入方向呈平行。
  3. 如申請專利範圍第2項之半導體裝置，其中，上述短邊係沿上述半導體基板的劈裂面。
  4. 如申請專利範圍第3項之半導體裝置，其中，上述半導體基板係SiC；上述短邊係相對於上述長邊呈60度傾斜。
  5. 如申請專利範圍第1至4項中任一項之半導體裝置，其中，在上述半導體基板上設有複數電晶體單元；各電晶體單元中，上述複數閘極指係呈傾斜直線狀配置；在相鄰接電晶體單元的邊界處，相互電晶體單元之端的閘極指呈錯開。
  6. 如申請專利範圍第1至4項中任一項之半導體裝置，其中，上述複數閘極指係呈V字形配置；上述閘極墊片距中央處之閘極指的線路長，係較長於上述閘極墊片距端之閘極指間的線路長。
  7. 一種半導體裝置，包括：半導體基板；以及複數電晶體單元，其乃設置於上述半導體基板上；其特徵在於：各電晶體單元係具有呈傾斜直線狀配置的複數閘極指； 在相鄰接電晶體單元的邊界處，相互電晶體單元之端的閘極指呈錯開。
  8. 一種半導體裝置，包括：半導體基板；以及複數電晶體單元，其乃設置於上述半導體基板上；其特徵在於：各電晶體單元係包括：呈V字形配置的複數閘極指、以及電氣式連接於上述複數閘極指的閘極墊片；上述閘極墊片距中央處之閘極指的線路長，係較長於上述閘極墊片距端之閘極指間的線路長。
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