CN101075581A - 集成的场效应晶体管和肖特基器件及其制造方法 - Google Patents

集成的场效应晶体管和肖特基器件及其制造方法 Download PDF

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CN101075581A
CN101075581A CNA2007101108738A CN200710110873A CN101075581A CN 101075581 A CN101075581 A CN 101075581A CN A2007101108738 A CNA2007101108738 A CN A2007101108738A CN 200710110873 A CN200710110873 A CN 200710110873A CN 101075581 A CN101075581 A CN 101075581A
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何红海
里图·苏迪希
达维德·基奥拉
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Infineon Technologies Americas Corp
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Abstract

一种半导体器件，包括在共用管芯中形成的肖特基器件和诸如金属氧化物半导体场效应晶体管的沟槽型半导体开关器件。

Description

集成的场效应晶体管和肖特基器件及其制造方法
本申请是于2004年8月4日向中国专利局提交的题为“集成的场效应晶体管和肖特基器件”的第200410070283.3号申请的分案申请。
技术领域
本发明涉及一种功率半导体器件，尤其涉及一种包括形成在共用管芯中的肖特基器件和MOSFET(金属氧化物场效应晶体管)的功率半导体器件。
发明背景
功率应用中所关心的主要因素是功率损耗。功率应用中的功率损耗大部分是由于功率电路中的功率开关器件(如功率MOSFET)引起的。例如，与功率MOSFET的体二极管(body diode)相关的功率损耗是形成功率电路综合功率损耗的一个因素。
现代功率应用需要高频率和高电流，这要求减少功率损耗。为防止MOSFET的体二极管产生功率损耗，公知是使用与该体二极管并联的肖特基器件，该肖特基器件以比体二极管更低的电压开启，从而防止MOSFET的体二极管导通。因此，共封装(Co-packaged)MOSFET和肖特基器件已被开发出来以在功率应用中使用。然而，这种封装相对较大，并且表现出不受欢迎的瞬变(transient)行为。
发明内容
为克服现有技术的器件的缺点，根据本发明的器件包括形成在共用管芯中的肖特基器件和功率MOSFET。结果，根据本发明的器件更加紧凑，并且功率损耗更小。
根据本发明的半导体器件包括形成在共用管芯中的沟槽型(trenchtype)MOSFET和肖特基器件。该沟槽型MOSFET包括多个沟槽，每个沟槽都支撑着栅极结构(gate structure)。肖特基器件包括肖特基势垒，肖特基势垒布置在管芯的部分顶面上，并与之肖特基接触。根据本发明的一个方面，肖特基器件包括多个肖特基区，每个肖特基区都布置在该MOSFET器件的一组沟槽之间。在根据本发明的器件中，共用触点(common contact)与MOSFET的源极区和肖特基器件的肖特基势垒接触。
根据本发明的第一实施方案，每个肖特基区包括一肖特基势垒，该肖特基势垒布置在形成于管芯中的至少一个台面(mesa)上，并与之肖特基接触。该台面的两侧与沟槽相邻，每一侧都包括处于其侧壁上的氧化物层，并含有导电材料。在根据本发明第一实施方案的器件中，肖特基势垒在台面上延展，并与各个沟槽中的导电材料相接触。
根据本发明的第二实施方案，肖特基器件的各个肖特基区中的肖特基势垒不与邻近至少一个台面的沟槽中的导电材料接触，而仅仅与台面的一部分接触。
根据本发明的第三实施方案，肖特基器件中的各个肖特基区包括形成在管芯顶面的一部分之上的肖特基势垒。在根据本发明的第三实施方案的器件中，没有使用肖特基沟槽。
通过下面参照附图对本发明的描述，本发明的其它特征和优点将变得显而易见。
附图说明
图1是根据本发明所述的半导体器件的俯视图，其中示意性地示出了本发明所述半导体器件中的肖特基区的结构；
图2是根据本发明第一实施方案所述的器件的局部剖视图；
图3-7示出了为获得本发明第一实施方案所述的器件而采取的处理步骤；
图8是根据本发明第二实施方案所述的器件的局部剖视图；
图9-10示出了为获得本发明第二实施方案所述的器件而采取的处理步骤；
图11是根据本发明第三实施方案所述的器件的局部剖视图；
图12-15示出了为获得本发明第三实施方案所述的器件而采取的处理步骤。
具体实施方式
参照图1，根据本发明的半导体器件包括形成在共用管芯中的肖特基器件和场效应器件，从而形成集成的FET(场效应晶体管)和肖特基器件。在根据本发明的半导体器件中，场效应器件是沟槽型MOSFET。如本领域中公知的那样，沟槽型MOSFET包括多个栅极结构。每个栅极结构都为形成在管芯体中的沟槽，并在其侧壁上包括栅氧化层，并容纳有用作栅电极的导电栅材料。典型的MOSFET可以包括大量并列的栅极结构。
根据本发明的肖特基器件包括许多肖特基区12。根据本发明的一个方面，如图1示意性地示出的那样，MOSFET的栅极结构分组排列，从而每个肖特基区12与一组栅极结构14相邻。栅极结构组14以公知的方式通过栅转子(runner)(未示出)与栅触点6相接触，从而它们谐调工作以驱动MOSFET。
应该注意，为说明本发明，肖特基区12和栅极结构组14的相对数目和尺寸被夸大了。本领域技术人员应意识到，肖特基区12和栅极结构组14的数目和尺寸是设计选择问题，在典型的应用中，其范围可以是几十万或者更多。
参照图2，根据本发明第一实施方案的半导体器件10包括至少一个肖特基区12和场效应器件，该场效应器件包括在共用管芯8中形成的多组栅极结构14。管芯8可包括一种导电类型的高掺杂衬底16和形成在该衬底16的主表面上的一种导电类型的轻掺杂外延层18。衬底16可掺杂红磷，但本发明不排除使用其它的高掺杂衬底。
在根据本发明的第一实施方案的半导体器件10中的场效应器件包括多个栅极结构，该栅极结构与公知沟槽型器件的栅极结构类似。根据本发明的一个方面，如图2所示，每组栅极结构组14与肖特基区12相邻布置。
各个沟槽20形成在外延层18中，每个沟槽20包括在其侧壁上的厚度适当的栅极氧化物22，可选地在其底部的厚氧化层24，以及用作沟槽20中的栅极的导电材料26，如多晶硅。
半导体器件10中的场效应器件还包括基区28和源极区30。通过用与外延层18的导电性(conductivity)相反的掺杂物对外延层进行反向掺杂，在外延层18中形成基区28。
源极区30为与外延层18导电类型相同的高掺杂区。每个源极区30从管芯8的顶面向基区28内部延伸预定的深度，并被布置成与沟槽20的侧壁相邻。
每个沟槽20从管芯的顶面延伸到基区28下方一定深度，基区28中与栅极氧化物22相邻的区域可以通过对与之相邻的导电材料26施加适当的电压进行转化，从而在邻近栅极结构的基区28中形成沟道区。沟道区使源极区30与基区28下方的外延层18的区域(以下称漂移区)电连接，从而使它们之间能够导通。
在根据本发明第一实施方案的半导体器件10中，在每对沟槽20之间形成有凹陷(depression)32。在每个凹陷32的底部还形成有与基区28导电类型相同的高掺杂区34，并且源极区30位于每个凹陷32的相对的侧壁上。根据本发明的一个方面，在每个凹陷32的侧壁和底面上形成有钛(Ti)层或TiSi2层以减少薄膜电阻。
在本发明的第一实施方案中，每个肖特基区12包括肖特基势垒40。肖特基势垒层40优选地由TiSi2组成，但使用其他合适的势垒材料也不会脱离本发明的精神。肖特基势垒40形成在台面36上，台面36的两侧带有两个沟槽38。每个沟槽38的侧壁填充有栅极氧化物22，并且每个沟槽38的底部可选地包括厚氧化层24。在本发明的第一实施方案中，肖特基势垒40形成在台面36上、台面36的部分侧壁以及每个沟槽38中的导电材料26的顶部上，并与台面肖特基接触。将肖特基势垒40延伸到台面36的侧壁有利于增加肖特基有效面积(active area)。应该注意到，在根据本发明第一实施方案的半导体器件中，肖特基区12不限于一个台面36。
根据本发明的一个方面，半导体器件10包括接触层42，接触层42在管芯的顶面上延伸，并与肖特基势垒40和源极区30(通过布置在凹陷32的侧壁上的TiSi2层)电接触。因而，在根据本发明的半导体器件中，接触层42既用作场效应器件的源极触点(source contact)又用作肖特基器件的肖特基触点。应该注意到，接触层42通过绝缘插头(insulation plug)44与沟槽20中的导电材料26绝缘。绝缘插头44优选地由低温氧化物(如TEOS，四乙基原硅酸盐)组成。根据本发明的优选实施方案，接触层42由Al，AlSi或AlSiCu组成。
半导体器件10还包括终端结构(termination structure)48，其环绕(见图1)有效区(包括肖特基器件和场效应器件的区域)。终端结构48包括布置在深凹陷50的底和侧壁上的场氧化物层52以及布置在场氧化物层52上的多晶硅层51。深凹陷50形成在半导体器件10的有效区的周围，并延伸到基区28下方一定深度，优选地延伸到沟槽20和38的下方一定深度。终端结构48进一步包括布置在多晶硅层54上的可以是TEOS或类似物的低温氧化物层56以及布置在低温氧化物层56上的终端触点58，并通过低温氧化物层56中的出入孔57与多晶硅层54电连接。器件10不限于终端结构48，还可以包括传统的终端结构，例如常规的场电极(rield plate)。
另外，半导体器件10包括既用作场效应器件的漏极触点(drain contact)又用作肖特基器件的第二触点的底触点46。底触点46可以包括任何合适的导电结构，如常规的三金属结构。
现在描述器件10的制造过程。
首先参照图3，从管芯8开始，在管芯8的主表面的顶上生长薄的(例如230)垫氧化物层60。下一步，在垫氧化物层60上淀积相对较厚(例如1200)的Si3N4层62。随后，在Si3N4层62上淀积光刻胶层64，并在管芯8中形成光刻的深凹陷50。
接下来参照图4，去除光刻胶层64，并在深凹陷50的底部和侧壁上生长场氧化物层52。随后，通过光刻淀积和处理光刻胶层68以在管芯8的顶面的选定部分上提供窗口70。下一步，与管芯8导电类型相反的掺杂原子通过窗口70、Si3N4层62和垫氧化物60被植入管芯8的顶面，并在扩散驱动(diffusion drive)中被驱动到预定的深度，从而形成横向分开的基区28。在扩散驱动之前，去除光刻胶层68。
下面参照图5，沟槽20，38通过(例如)光刻或蚀刻被形成在管芯8中的基区28下的一定深度上。随后，由较后的光刻过程形成的任何光刻胶材料被去除，并以按照如下步骤在每个沟槽的底上形成厚氧化物层24，在侧壁上形成栅极氧化物层22。
首先，在沟槽20、38的底部和侧壁上生长并去除牺牲氧化物层，随后在沟槽20、38的底部和侧壁上生长垫氧化物层，接着在垫氧化物层上淀积Si3N4层。随后利用干蚀刻去除每个沟槽20、38的底部的Si3N4，并使每个沟槽20、38的底部进一步氧化，以在每个沟槽20、38的底部上形成厚氧化物24。随后，Si3N4的剩余部分被从沟槽20、38的侧壁上去除，并在沟槽的侧壁上生长栅极氧化物层22。
随后，淀积多晶硅层以对沟槽20、38进行填充。然后蚀刻多晶硅层以使沟槽20、38的至少一部分被多晶硅填充，并在场氧化物层52上保留多晶硅层54。每个沟槽20、38中剩余的多晶硅构成了前述的导电材料。如图5中的虚线所示，随后可以对每个导电材料26的顶面进行氧化。
下面参照图6，接下来用湿蚀刻去除剩余的Si3N462，并淀积光刻胶层72。然后蚀刻光刻胶层72，从而使管芯8顶面上的区域74暴露出来。如后面将看到的那样，区域74将是用于场效应器件的有效区的位置。与外延层18导电性相同(与基区28的导电性相反)的源极掺杂物随后被植入区域74以在基区28中形成反掺杂区76。应该注意，在植入源极掺杂物期间，光刻胶层72的一部分留在台面36和与之相邻的沟槽38上。随后，去除光刻胶层72(虚线表示出了去除)，并在结构的整个表面上淀积TEOS 56。
下面参照图7，通过采用光刻法在管芯8中形成延伸至反掺杂区76之下一定深度的凹陷32，保留沟槽20、38顶部的绝缘插头44(由TEOS 56形成)。优选地，绝缘插头44被蚀刻成具有锥形侧壁。随后，去除剩余的任何光刻胶，并在扩散驱动步骤中驱动源极掺杂物以形成源极区30。随后，与基区28导电类型相同的掺杂物被植入到每个凹陷32的底部，并被驱动以形成高导电区34。
再次参照图2，通过光刻去除台面36和与之相邻的沟槽38上的绝缘插头44。随后去除光刻步骤留下的任何光刻胶，任何淀积钛层，并利用快速热退火(RTA)形成硅化钛(titanium silicide)势垒。随后从绝缘插头44和TEOS层56的顶部去除未反应的钛，淀积铝(AL)层并对其烧结以形成接触层42。为获得器件10，可利用任一常规公知技术形成后触点46和栅极触点6(见图1)。
参照图8，除了器件78的肖特基区12包括肖特基势垒80外，根据本发明第二实施方案的器件78与器件10在所有方面都类似。肖特基势垒80与器件10的肖特基势垒40不同，它只与台面36的顶面接触，并且未延伸到沟槽38和沟槽38内的多晶硅的侧壁。
根据第二实施方案的器件78的制造方法比根据第一实施方案的器件10的制造方法具有更少的掩模步骤，该制造方法根据上述结合附图3-5的方法并结合下面的附加步骤实现。
下面参照图9，与上述用于制造器件10的方法(第一实施方案)不同，在导电材料26形成(也就是在沟槽20中淀积多晶硅)之后不去除Si3N4层62。反而在不去除Si3N4层62的情况下淀积并压实(densify)TEOS层56(由虚线示出)。下一步，通过采用光刻技术去除TEOS 56(去除部分由虚线示出)，直到Si3N4 62被暴露只剩下绝缘插头44为止。应该注意到，与器件10的处理方法(第一实施方案)类似，终端区中的TEOS层56被保留。
下面参照图10，利用湿蚀刻去除剩余的Si3N4，并淀积第二TEOS层82(由虚线示出)。随后，通过对第二TEOS层82进行各向异性地蚀刻，在绝缘插头44的侧壁上形成绝缘间隔(spacer)84。后一蚀刻步骤被持续进行，直到至少管芯8的顶面被暴露为止。
接下来，利用源极掩模33，以一定的角度植入源极掺杂物。随后，使用任何适当的蚀刻方法在管芯8的顶面上形成凹陷32。
再次参照图8，通过现存的源极掩模33，在每个凹陷32的底部植入导电类型与基区28相同的掺杂物原子。随后，掺杂物原子与源极掺杂物一起被驱动，从而分别形成高导电区34和源极区30。接下来，去除源极掩模33，并且在一个清洁步骤之后，Ti层被淀积，并且通过硅化处理和适当蚀刻以在台面36的顶部形成肖特基势垒80，并且在凹陷32的表面上形成TiSi2。随后以与上述参照器件10描述的内容相同的方式形成触点42和底部触点46。
参照图11，根据本发明第三实施方案的器件86包括器件10(第一实施方案)和器件78(第二实施方案)中的全部特征，但器件86的肖特基区域12不是形成在与两个横向分开的沟槽相邻的台面上方或之上。器件86的肖特基区12包括形成在外延层18的未被反掺杂的区域的顶面上的肖特基势垒层40。应该注意到，器件86的肖特基区12附近的基区28被加深并且相对于基区28的其他部分更高地掺杂(区92)，从而减少电场应力并提高击穿电压。还应注意到，反掺杂区90是彼此横向分开的，并且每个反掺杂区的横向边缘包括区域92，区域92更深地深入外延层18并相对于反掺杂区90的其余部分更高地掺杂。
根据下面的方法制造根据本发明第三实施方案的器件86。
首先参照图12，在管芯8的顶面上形成氧化物层。下一步，通过光刻和蚀刻，去除氧化物层的一部分，在氧化物层上开设窗口89，以形成氧化物层88(实线)和氧化物层92a(虚线)，并在窗口89区域内暴露外延层18的部分顶面。通过窗口89进行植入，以在外延层18内形成反掺杂区92。随后，在氧化物层88上形成光刻胶层，并去除氧化物层92a以暴露外延层18的部分顶面。利用氧化物层88(未通过光刻和蚀刻去除)作为掩模，在外延层18中形成反掺杂区90。随后，利用氧化物层88作为掩模，在反掺杂区90中植入源极掺杂物。应该注意到，源极掺杂物植入的深度小于反掺杂区90的深度。还应注意到，如图12所示，反掺杂区90与反掺杂区92是混合的。区92比区90更深地进入外延层18，并通过一个驱动步骤横向延伸到氧化物层88下方的区域。
参照图13，优选地，反掺杂区90和包含源极掺杂物的区域在一扩散驱动中被驱动，以形成基区28和源极区30。随后通过光刻形成沟槽20以获得如图13所示的结构。
参照图14，氧化物层94被生长在图13所示结构的上方，包括每个沟槽20的侧壁和底部。应该注意到，也可以修改处理方法以获得具有类似于器件10(第一实施方案)和器件78(第二实施方案)的厚氧化物底部的沟槽20。在形成氧化物层94之后，淀积多晶硅层，随后进行充分的蚀刻(与任何在下面的氧化物一起进行)，以使各个沟槽20部分地填充以用作栅极的多晶硅(导电材料26)。
接下来下面参照图15，随后去除剩余的氧化物88，然后在如图14所示的结构上淀积TEOS层96(如虚线所示)。接着，在TEOS层96中开设一个开口98(由竖直虚线示出)，以暴露外延层18顶面的特定部分，该部分被蚀刻以形成凹陷32。随后，与基区28导电类型相同的掺杂物被植入每个凹陷32的底部，并在一个扩散驱动中被驱动以形成高导电区34。所后通过(例如)光刻去除TEOS 96的选定部分(去除部分如虚线所示)，从而形成绝缘插头44。
再次参照图11，钛(Ti)层利用如喷溅等方法被淀积在图15所示的结构上，并随后经过退火以形成TiSi2，其用作在横向分开的基区28之间的外延层区之上的肖特基势垒40的势垒材料。应该注意到，TiSi2也可以延伸在每个凹陷32的底部和侧壁上。下一步，从绝缘插头44的顶部除去多余的TiSi2，并喷上触点层42。随后在管芯8的底部上淀积底部触点46，从而形成根据本发明第三实施方案的器件86。
尽管本发明是结合特定的实施方案进行描述的，对本领域的技术人员而言，许多其它的变化、改进和应用是显而易见的。因而声明，本发明的保护范围只受权利要求的限制，而不受本文的特定公开的限制。

Claims (9)

1.一种用于制造半导体器件的方法，包括：
提供半导体管芯；
在所述管芯中形成肖特基器件；
在所述管芯中形成沟槽型半导体开关器件，所述沟槽型半导体开关器件包括基区，其中邻近所述肖特基器件的基区相对于所述基区的其他部分被加深并且更高地掺杂，并且所述半导体开关器件包括至少一个功率节点；以及
形成与所述肖特基器件和所述至少一个功率节点相接触的共用第一触点。
2.根据权利要求1所述的方法，其特征在于，所述沟槽型半导体开关器件是沟槽型金属氧化物半导体场效应晶体管。
3.根据权利要求1所述的方法，其特征在于，所述肖特基器件包括由TiSi2组成的肖特基势垒。
4.根据权利要求3所述的方法，其特征在于，所述肖特基势垒被布置在所述管芯的顶面的一部分上，并与其肖特基接触。
5.根据权利要求4所述的方法，其特征在于，所述肖特基势垒被布置在形成于所述管芯内的台面的一部分上，并与其肖特基接触。
6.一种半导体器件，包括：
管芯，其中形成有肖特基器件和金属氧化物半导体门控开关器件，所述肖特基器件包括形成在所述管芯的表面上的多个肖特基区，所述金属氧化物半导体门控开关器件包括多个栅极结构，每个栅极结构包括延伸穿过基区的沟槽，所述沟槽在侧壁上形成有绝缘层，并且包含有导电电极；
其中，所述栅极结构被分组形成，并通过肖特基区相互分开，并且位于所述肖特基器件附近的基区相对于所述基区的其他部分被加深并且更高地掺杂。
7.根据权利要求6所述的半导体器件，其特征在于，所述金属氧化物半导体门控开关器件为金属氧化物半导体场效应晶体管。
8.根据权利要求6所述的半导体器件，其特征在于，各个肖特基区包括含有TiSi2的肖特基势垒。
9.根据权利要求8所述的半导体器件，其特征在于，各个肖特基势垒被布置在所述管芯内形成的台面的主表面上。
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