TWI302028B - Integrated fet and schottky device - Google Patents
Integrated fet and schottky device Download PDFInfo
- Publication number
- TWI302028B TWI302028B TW093123093A TW93123093A TWI302028B TW I302028 B TWI302028 B TW I302028B TW 093123093 A TW093123093 A TW 093123093A TW 93123093 A TW93123093 A TW 93123093A TW I302028 B TWI302028 B TW I302028B
- Authority
- TW
- Taiwan
- Prior art keywords
- schottky
- contact
- region
- trench
- wafer
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 claims description 38
- 230000004888 barrier function Effects 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 16
- 239000004020 conductor Substances 0.000 claims description 14
- 230000005669 field effect Effects 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 229910008479 TiSi2 Inorganic materials 0.000 claims description 3
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims 2
- 150000004706 metal oxides Chemical class 0.000 claims 2
- 241000283080 Proboscidea <mammal> Species 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 238000001459 lithography Methods 0.000 description 11
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 241000282320 Panthera leo Species 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 210000004556 brain Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- 150000003573 thiols Chemical group 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
1302028 玖、發明說明: 【發明所屬之技術領域】 體(M0SFET) 本發明是有關於-種功率半導體裝置,更尤其是有關功率半導體裝 置,其包括形級共同w巾之肖特紐置與金魏化物半物場效應電 【先前技術】 在功率應用巾主制_素為神損失。在功率應财之功率損失主 要疋由於·在神電路巾辨城裝置修:神卿et之功率損失。例 如·與功率M0SFET之體二極體有關之功率損失,是造成功率電路整體功率 損失之因素。 現代功率應狀高解與高電流要求須要降低功率損失。為了避免由 於M0SFET讀二極體之辨損失,6知侧,频二減細之宵特基 裝置,其在較體一極體為低之電壓導通,而防止由MOsfet之體二極體導電。 因此發展出使用於功率應用中之共同封裝之M0SFET與肖特基裝置。然而, 此種封裝相當大,且顯示非所欲之暫態行為。 【發明内容】 為了克服習知技術裝置之缺點,此根據本發明之裝置包括··形成於共同 晶片中之肖特基裝置與功率M0SFET。因此,此根據本發明之裝置是更小型 緊密且顯示較少功率損失。 1302028 均形成於共同晶片中之溝渠式 此根據本發明之半導體裝置包括: /、各支持問極結構。 M0SFET與肖特基裝置。此溝渠式M0SFET包括多個溝渠 此宵特基裝置包括肖特基阻障’其設置在晶片之職面之部份上且與其作 肖特基接觸。根據本發明之-觀點,此肖特基裝置包括多個肖特基區域, 其各設置在MGSFEm置之溝渠組之間。在根據本發明,喊畴 觸與M0SFET之源極區域以及宵特基裝置之肖特基阻障接觸。 根據本發明之第-實施例,各肖特基區域包括:肖特基轉,其設置 在形成於⑼中至少-平台上且與其做肖特基接觸。此平台在其各側靠近 溝渠’其各在其側壁上包括-層氧化物,且包括導電材料。在根據本發明 第-實施例之裝置中,此肖特基阻障在平台上延伸,以及與在各溝渠中之 導電材料接觸。 根據本發明之第二實補,此肖特基裝置之各肖特基區域中之肖特基 阻p早並不與溝渠中之#電材料接觸,其靠近至少一平台,且只與平台之 一部份接觸。 根據本發明之第三實施例,此肖特基裝置之各肖特基區域包括:形成 於晶片頂表面上之一部份上之肖特基阻障。在根據本發明第三實施例之裝 置中,並未使用肖特基溝渠。 本發明之其鱗點與優點將由町本發狀賴並參考顺圖式而為 明顯。 【實施方式】 1302028 睛參考第1圖,此根據本發明之半導體裝置包括:形成於共同晶片中之 肖特基裝置與場效應裝置,因此形成積體式埸效應電晶體(FET)與肖特基裝 置。此根據本發明之半導體裝置中之場效應裝置是溝渠式M〇SFET。如同於 此技術中所知,麟細SFET包括乡個_結構。各_結構是形成於晶 片體中之溝渠,且包括在其側壁上之_氧化物層,以及包括使用作為閘 極電極之導電閘極材料。典型之腦FET包括側靠側所形成之大量閘極結構。 此根據本發明之肖特基裝置包括多個宵特基區域12,根據本發明之一 觀點,將結構配置成組,贿於靠近閘極結構組敗各肖特 基區域12是如同由第1_概要顯示者。關極結構組14以已知之方式由閘 極連線(未圖示)連接至閘極接觸6,以致於其一起共同操作以啟細謝。 應注意為綱本發明將肖特基區域12與閘極結構組14之尺寸與數目放 大。熟習此技術人士瞭解:肖特基區域12與閘極結構組14之尺寸與數目是 -種設計選擇,且在典型顧巾,其顧可以為數十萬或更多。 現在明參考第2® ’此根據本發明第—實施例之半導體裝㈣包括:至 少-肖特基區域12與場效裝置,其包括形成於共同晶片8中之閘極結構組 14。晶片8可以包括:-種導電型式之高度摻雜基板16,以及在基板μ主要 表面上所形成-種導電型式之輕度摻齡晶層18。基板16可以紅碟換雜, 雖然可以使用其他而度摻雜基板而不會偏離本發明。 此根據本發明第-實施例之半導體裝置1〇中之場效應裝置包括:多個 閘極結構,其與已知鰱式裝£之_結翻似。娜本發明之—觀點, 各閘極結構組14設置靠近-肖特基區域同由第細所說明者。 1302028 各溝渠20形成於磊晶層18中,且包括:在其側壁上適當厚度之閘極氧 化物22、在其底部選擇性之厚之氧化物層24、以及導電材料26例如多晶矽, 其作用為溝渠20中之閘極電極。 此在半導體裝置10中之場效應裝置亦包括基極區域28與源極區域30。 基極區域28藉由將導電性與磊晶層丨8相反之摻雜物作逆摻雜(c〇unter doping),而形成於磊晶層ι8中。 源極區域30是與磊晶層18相同導電型式之高度摻雜區。各源極區域3〇 從晶片8之頂部表面在基極區域28中延伸至預設深度,且設置靠近溝渠2〇之 側壁。 各溝渠20從晶片之頂表面延伸至基極區域28下之深度。此在基極區域 28中靠近閘極氧化物22之區域,可以藉由將適當電壓施加至靠近它之導電 材料26反轉,而在靠近閘極結構之基極區域28中形成通道區。此通道區電 性連接源極區_至基極區域28(以下稱為漂移層日日層敗區域, 因此,允許兩者間之導電。 在此根據本發明第-實施例之半導體裝置1〇中,在各對溝渠2〇之間形 成凹口32。而且,在底部形成高度摻雜區34,其導電型式與基極區域撕目 同,且源極區域30是位於各凹口32之對面側璧。根據本發明之一觀點,將 一層Ti或Ti&形成於各凹口32側壁與底部表面上,以降低片電阻。 在本發明第-實施例中,各肖特基區域12包括宵特基阻障仙。宵特基 阻障層嫩佳由他構成,雜可以使用其他適#阻障材料,科會偏離本 發明之精神。肖特基阻障4〇形成於平台36上,其具有兩個溝魏設置於其 1302028 各側上。各溝渠38之側壁與閘極氧化物22成一直線,以及各溝渠38之底部 · 選擇性地包括厚的氧化物層24。在本發明第一實施例中,宵特基阻障4〇形 成於以下物件上且與其成肖特基接觸:平台、平台36之侧壁之一部份、以 及在各溝渠38中導電材料26之頂部。將肖特基阻障層4〇延伸至平台36之側 , 壁是有利的,因為其增加肖特基主動區。應注意是在根據本發明第一實施 _ 例之半導體裝置中之肖特基區12,而並不受限於平台36。 根據本發明之一觀點,半導體裝置1〇包括:接觸層42,其在晶片之頂 表面上延伸,且與肖特基阻障4〇以及源極區域3〇(經由設置在凹口犯側壁上 鲁 之Τι&層)電性接觸。因此,在根據本發明之半導體裝置中,接觸層犯作為: 用於場效應裝置之源極接觸,與用於肖特基裝置之肖特基接觸。應注意接 觸層42藉由絕緣插塞44與溝渠20中之導電材料26絕緣,而此插塞較佳由低 溫氧化物例如TEOS構成。根據本發明之較佳實施例,此接觸層42是由A1、
AlSi、或AlSiCu所構成。 半導體裝置10亦包括終端結構48,其圍繞(參考第丨圖)主動區(此區域 包括:肖特基裝置與場效應裝置)。終端結構48包括··設置在深凹口 5〇底部 修 與侧壁上之%氧化物層52、以及設置在場氧化物層π上之多晶石夕層54。深 凹口50是形成於半導體裝置1〇中主動區周圍,且延伸至基極區域沈下之深 1 度,以及較佳在溝渠20與38之深度之下。終端結構48更包括:設置於多晶 矽層54上之低溫氧化物層56,其可以為TEOS等;以及設置於低溫氧化物層 56上之終端接觸58,且經由低溫氧化物層56中之接達孔57而電性連接多晶 矽層54。裝置10並不受限於終端結構48,但可以包括傳統終端結構,例如 11 1302028 傳統之場片。 此外,半V體裝置10包括底部接觸46,其作用為:用於場效裝置之没 極接觸,以及用於肖特基裝置之第二接觸。底部接觸46可以包括任何適當 導電結構,例如傳統之三金屬結構。 現在說明用於製造裝置1〇之過程。 首先請參考第3圖,從晶片8開始,在晶片8之主要表面頂上成長一薄層 (例如:230埃)之墊氧化物6〇。然後,在此墊氧化物層6〇上沉積相當厚(例如: 1200埃)之Si3N4層62。然後,在此Si_62上沉積絲層64,以及經由微影 術在晶片8中界定深凹口50。 其次,请參考第4圖,將光阻層64去除,且在深凹口5〇之侧壁與底部上 成長-場氧化物層52。其次,沉積_光阻層68,錄由微影術處理,在晶 片8之頂表面之所選擇之部份上提供窗口7〇。其次,將導電型式與晶片8之 ‘電型式反之摻雜原子經由:窗口 7〇、sil層62、以及墊氧化物6〇,植 入於晶片8之絲面巾,且在概驅射·_至所想要之深度,以形成橫 向間隔之基極區域28。在此擴散驅動之前將光阻層68去除。 其次,請參考第5圖,藉由例如微影術與侧,在晶片8中將溝渠2〇、 38形成至基極區麵以下之深度。其次,將微影處理之任何剩餘光阻材料 去除’以及如同町將底部上厚的氧化物層24,與各溝渠罐上之閑極氧 化物層22去除。 首先’在溝渠20、38之側壁與底部成長犧牲氧化物層然後去除。其次, 在溝渠2G、38之側鶴底部上餘—層魏化物。接著在此魏化物層上 12 1302028 沉積一層ShN4。然後,將各溝渠20、38底部之Shli藉由乾式蝕刻去除,以 及將溝渠20、38底部進一步氧化,而在溝渠20、38之底部形成厚的氧化物 24。其次,將ShN4之殘餘部份從溝渠20、38之側壁去除,以及在溝渠之側 壁上成長閘極氧化物層22。 參 然後,沉積多晶矽層而造成將溝渠20、38填滿。之後,將此多晶石夕層 . 蝕刻以留下各溝渠20、38至少部份以多晶矽填入,且在場氧化物層52上留 下多晶矽層54。此在各溝渠20、38中所存留之多晶矽構成早先說明之導電 材料26。然後,如同第5圖中虛線所示,將各導電材料26之頂部表面氧化。 暴 其次,請參考第6圖,然後,藉由濕式蝕刻將剩餘之Si3N4 62去除,以 及沉積光阻層72。隨後將光阻層72蝕刻,以致於曝露晶片8之頂表面上之區 域74。如同稍後可看出,區域μ為用於場效應裝置主動區域之位置。然後, 在區域74中植入與磊晶層18相同導電型式(與基極層汾之導電型式相反)之 源極摻雜物,而在基極區域28中形成逆摻雜區76。應注意,在源極摻雜物 植入期間,光阻層72之一部份存留在平台36上且靠近溝渠38。然後,將光 阻層72移除(藉由虛線以顯示移除),且將TE〇s 56沉積在此結構之整個表面 _ 上。 其次,請參考第7圖,藉由實施微影術在晶片8中形成凹口32至逆攙雜 區76以下之深度,而留下絕緣插塞44(由TE〇s帥形成)在溝渠2〇、犯之頂上。 #父佳將絕雜塞44铜成具有逐漸變狀砸。其次,將任侧餘光阻去 除’且在擴散_步财驅觸極獅物以碱雜區卿。然後,將與 基極區域28財_導電型紅獅物植入各凹 口 32之底部且驅入,以形 13 1302028 成高導電區34。 請再參考第2®,將在平纟36上且靠近溝渠38之絲減繼由微影術 去除。然後,將由微影步驟所剩餘之任何光阻去除,且沉積一層鈦,以及 藉由快速回火(腿)形成!域錄轉。雜,將未反應之賊絕緣插塞44 與TE0S層56之頂部去除,以及沉積一顧且燒結以形成接觸層犯。為了獲 得裝置10 ’則根據任何傳統已知技術形成後接觸46與閘極接觸6(第丨圖)。 請參考第8圖,此根據本發明第二實施例之裝置78在各方面類似於裝置 1〇,所不同的是··裝置78之肖特基區域12包括肖特基阻障8〇,其與裝置1〇 之肖特基阻障40不同,只與平台36之頂表面接觸,且並未延伸至溝渠洲之 側壁與溝渠38内之多晶矽。 此用於製造根據帛二實施例之裝置78之過程、較用於製造根據第一實 施例之裝410之雜,具有較少鮮步驟,並且根據上述參考第如圖之 製程且與以下額外步驟組合而實施。 其次,請參考第9圖,不同於以上說明用於製造裝置1〇(第一實施例)之 製程,在形成導電材料26(即,在溝渠2〇中沉積多晶石夕)後,並未將62 去除。而是,未將Sil 62去除,而沉積一層TE〇s 56(由虛線所示)且使其 濃密。然後,藉由實施微影術將TE0S 56去除(去除部份由虛線所示),一直 至將祕62曝露而留下絕緣插塞44為止。應注意,類似於裝之處理(第 一實施例),將一層TEOS 56留在終端區域中。 其次,請參考第10圖,將所剩餘之藉由濕式钱刻去除,以及沉積 第二層畐82(由虛線所示)。然後,藉由將第二層TE〇s 82作非均向性餘 1302028 刻,而在絕緣插塞44之侧壯形成絕緣間隔件84。繼續此後者餘刻步驟一 直至至少將晶片8之頂表面曝露為止。 然後,使用源極遮罩33以-角度植入源極摻雜物。然後使用任何適當 蝕刻方法,在晶片8之頂表面上形成凹口32。 肀 口月再度參考第8圖,將與基極區域28相畴電型式之摻雜原子經由現彳 , 之源極遮罩33植入至各凹口32底部,以及然後與源極摻雜物一起驅動,以 各別形成局導電區34與源極區域3〇。其次,去除源極遮罩33,且在清理步 驟後/儿積-層鈇,使其經由石夕化與適當侧,而在平台36之頂上形成肖特 φ 基阻障80,以及在凹口32之表面上形成现2。然後,與上述關於裝置_ 同之方式形成接觸42與底部接觸46。 凊參考第11圖,此根據本發明第三實施例之裝置86包括在裝置1〇(第一 實施例)與裝置78(第二實施例)中所說明之所有特性,所不同的是:裝置86 之肖特基區域12並未形成於靠近兩健_隔溝渠之平台上。而是,在裝 置86中之肖特基區域12包括··肖特基阻障層40,其形成於未經逆摻雜之蟲 晶層18中之區域之頂表面上。應注意,此靠近裝置86之肖特基區域12之基 φ 極區域28被深化,且相對於基極區域28之其餘部份被更高度摻雜(區域 92),以便降低電場應力以及增加崩潰電壓。亦應注意,此等逆換雜區剛皮 ♦ 此橫向間隔,且各在其橫向邊緣包括區域92,其延伸得更深入磊晶層18中, · 且相對於逆摻雜區90之其餘部份被更高度摻雜。 此根據本發明第三實施例之裝置86是根據以下過程製造。 首先,請參考第12圖,在晶片8之頂表面上形成一層氧化物。其次經由 15 1302028 微〜術與蝕刻’將氧化物層之一些部份去除,而在氧化物層中開啟窗口89, 以形成氧化物層88(實線)與氧化物層92a(虛線) ’以及將窗口89區域中蠢晶 層18之頂表面之部份曝露。經由窗口89植入,在磊晶層18中形成逆摻雜區 92。然後,在氧化物層88上形成光阻層,以及將氧化物層92a去除,以曝露 磊晶層18之頂表面之部份。使用氧化物層肋(未由微影術與餘刻去除者)作 為遮罩,在磊晶層18中形成逆摻雜區90。然後,使用氧化物層88作為遮罩, 將源極攙雜物植入於逆摻雜區9〇中。應注意,此來源摻雜物被植入較逆摻 雜區90為小之深度。亦應注意此逆摻雜區90與逆掺雜區92合併,如同在第 12圖中所不者。區域92較區域9〇延伸進入磊晶層18更深,且經由驅動步驟 橫向延伸至氧化物層88以下之區域。 請參考第13圖,宜將逆摻雜區9〇與包含源極摻雜物之區域在擴散驅動 中驅動,以形成基極區域28以及源極區域3〇。然後,經由微影術形成溝渠 20以獲得在第13圖中所示之結構。 請參考第14圖,在第13圖所示結構之頂成長氧化物層94,其包括各溝 渠20之側壁與底部。應注意可以將此過程修正以獲得溝渠,其具有類似 於裝置l〇d實棚)絲龍(第二實補)之厚的氧化物底部。在形成 氧化物層94後,沉積一層多晶矽,然後(與任何位於其下之氧化物)實施足 夠蝕刻,而在各溝渠20留下部份填滿之多晶矽(導電材料26),其將作為閘 極電極。 其次,請參考第15圖,將氧化物層88之其餘部份去除,以及然後在第 14圖所示之結構上沉積一層TEOS 96(由虛線所示)。其次,在te〇s 96層中 16 1302028 開啟開口98(由垂直虛線所示),以曝露磊晶層18頂表面之某些部份,此等 部份被敍刻以產生凹口32。然後,將與基極區域28相同導電型式之摻雜物 植入於各凹口32之底部,且在擴散驅入中驅入以形成高導電區34。隨後, 經由例如微影術藉由將TE0S 96經選擇之部份去除(此等去除部份由虛線所 示),而形成絕緣插塞44。 請在參考第11圖,藉由例如濺鍍在由第15圖所示之結構上沉積一層 Τι,且然後回火以形成TiSi2,其在橫向間隔之基極區域沈之間之蟲晶層 之該區域上作為用於肖特基阻障4〇之阻障材料。應注意:TiSi2可以在各凹 馨 口 32之侧璧與底部上延伸。其次,將多餘的Η%從絕緣插塞44之頂部去除, 且濺鍍上接觸層42。然後,將底部接觸46沉積在晶片8之底部上,以形成根 據本發明第三實施例之裝置86。 雖然’以上根據特殊實施例說明本發明,然而,對於熟習此技術人士 . 而為明顯,可以對其作許多其他之變化與修正。因此,本發明較佳並不受 在此所揭示特定細節之限制,而只受限於所附之申請專利範圍。 17 1302028 【圖式簡單說明】 ’其概要說明根據本發明半導 第1圖為根據本發明半導體裳置之項视平面圖 體裝置中肖特基區域之配置; 第2圖為根據本發明第一實施例之裝置之—部份之橫截面圖; 第3至7騎崎實獻_娜,顿得滅本發㈣ 細為根據本發明第二實施例之裳置之一部份之橫截面圖; 第9至_酬所實施之步驟,犧得輯本發㈣二實關之裝置; 第11圖為根據本發明第三實施例之裝置之—部份之橫截面圖;以及 第12至15®·所實狀轉,卩獲得娜本發㈣三實糊之裝置。 【元件符號說明】 6 閘極接觸 8 晶片 10 半導體裝置 12 肖特基區 14 閘極結構組 16 基板 18 蠢晶層 20 溝渠 22 閘極氧化物(層) 24 氧化物層 18 導電材料 基極區域 源極區域 凹口 源極遮罩 高度摻雜區(高導電區) 平台 溝渠 肖特基阻障層 接觸層 絕緣插塞 底部接觸 終端結構 凹口 場氧化物層 多晶石夕層 TEOS(層) 接達孔 終端接觸 墊氧化物 Si3N4 層 19 光阻層 光阻層 窗口 光阻層 區域 逆摻雜區 裝置 肖特基阻障 TEOS 層 絕緣間隔件 裝置 氧化物層 窗口 區域/逆摻雜區 區域/逆摻雜區 氧化物層 氧化物層 TEOS 層 開口 20
Claims (1)
1302028 拾、申請專利範圍: 1. 一種半導體裝置,包括: 旧 晶片,,具有形成於其中之半導體切換裝置與肖特基3, 斜¥體切換裝置包括··多個溝渠各包含一對相面對之側壁與一底部 壁、且各賴象難峨_㈣巾綱域,多伽 口、其形成於鱗_賴細彡树㈣麵之麵 、\間之表耐,第—導電型式之通道區、形狀該;t且設置靠 =亥溝渠之側壁’閘極絕緣層,設置在靠近各通道區之溝渠之各側 璧上’導電閘極材料、包含於該溝渠中、且藉由該閉極絕緣層與該 通道區絕緣1H峨_、謝爾麵側壁之 該通道區㈣峨減、林細靡各通道 區域; 该肖特基裝置包括,設置在該晶片 且與其作肖特基接觸; 之頂表面之一部份上之肖特基阻障, =接觸’與該肖縣轉以第二導電型式之該轉域接觸;以及 端°構D亥終^結構是由以下所構成形成於該晶片中至該通道區以 :朱度之凹卩、形成於該凹口主要表面上之第―絕緣層、形成於該 絕緣層上之導電層、形成於錄導電層上之第二絕緣層、以及形成於 :第_|&緣層上之終端接觸’其中鱗端接觸經由該第二絕緣層與 該導電層電性接觸。 21 羅正替換頁' __ ^ 2·如申請專利範圍第1項之半導體裝置,更包括 第二接觸,與該第-接觸相面對之該晶片之主要表面接觸。 3·如申請專利範圍第1項之半導體裝置,其中 該半導體切換裝置為金屬氧化物半導體場效應電晶體(膽阳。 1·如申清專利範圍弟1項之半導體裝置,呈中 該肖特基阻障包括TiSi2。 •如申請專利範圍第1項之半導體裝置,其中 該肖特基轉是設置麵成於該^巾平台之主要表面上。 •如申請專利範圍第1項之半導體裝置,其中 孩肖特基裝置更包括平台,具有形成於其各面上之溝渠,各溝渠具有形 成於其側壁與底部上之絕緣層,且包含導電材料。 如申請專娜财6項之半導體裝置,財 該肖特基阻障在該溝渠之該側壁上延伸。 如申請專利範圍第1項之半導體裝置,更包括 、.電區其u在⑦第二導電形式之各對該區域間之該通道區域之
彥(更LiE/替換頁i 導電型式相同,且接觸該第一接觸 9·如申請專利範圍第8項之半導體裝置,其中 該高導電區是位於該晶片中凹口之底部。 10·如申凊專利範圍第丨項之半導體裝置,其中 各该溝渠包括在其底部—厚的氧化物層。 η. 於製造半導體裝置之方法,其包括以下步驟: 提供半導體晶片; 在該晶片中形成肖特基裝置; 在该晶片中形成溝渠式半導_換裝置,該溝渠式半導體切換裝置包 括基極區域,此基極區域相對於靠近該肖特基裳置之該基極區域 之其餘部份更高度掺雜且深人’且該半導體切歸置包括至少一 個功率節點; 在該半導體切換農置之相鄰對溝渠之間之表面中形成凹口,其中此等 源極區域形成於該凹口側壁之頂上;以及 、 形成共同第一接觸,其與肖特基裝置以及該至少-功率節點接觸。 12·如申請專利範圍第11項之方法,其中 。亥溝七式半導㈣換裝置是溝渠錢。 23 1302028 β Λ心心,/ 13·如申請專利範圍第11項之方法,其中 該肖特基裝置包括由TiSh構成之肖特基阻障。 14·如申請專利範圍第13項之方法,其中 ^亥宵特基轉設置在該晶片之頂表面之_部份上,賴其作肖特基接 觸0 15·如申請專利範圍第14項之方法,其中 該肖特基轉設置在該;巾所軸平台之—部份上,且與其作肖特 基接觸。 16. 如申請專利範圍第15項之方法,更包括 在。亥平台之各面上之溝渠,各溝渠具有形成於其趣上氧化物且包括 導電材料,其中該肖縣轉與該導電材料作諸基接觸。 17. —種半導體裝置,包括 晶片’其具有形成於其中之肖特基裝置與金屬氧化物半導體(觸問控 切換裝置; 該肖特基裝置包括形成於該晶片表面上之多個肖特基區域; 該M0S閘控哺裝置包括多侧結構,各結構包括溝渠具有形成於其側 24 壁上絕緣層,以及包含導電電極;以及 凹口,其形成於相鄰對溝渠、與形成於該凹口側壁之頂之至少一源極 區域間之表面中,其中該閘結構形成組,且藉由肖特基區域彼此間隔, 以及其中該基極區域相對於靠近該肖特基裝置之該基極區域之其餘部 份為更高度掺雜且深入。 18.如申請專利範圍第1了項之半導體裝置,其中 該M0S閘控切換裝置是MOSFET。 19·如申請專利範圍第17項之半導體裝置,其中 各肖特基區域包括由TiSh構成之肖特基阻障。 2〇·如申請專利範圍第19項之半導體裝置,其中 各肖特基阻障是設置在形成於該晶片中平台之主要表面上。
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-
2003
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-
2004
- 2004-07-27 DE DE102004036330.7A patent/DE102004036330B4/de not_active Expired - Fee Related
- 2004-08-02 TW TW093123093A patent/TWI302028B/zh active
- 2004-08-03 JP JP2004227165A patent/JP4843204B2/ja not_active Expired - Fee Related
- 2004-08-04 CN CN2007101108738A patent/CN101075581B/zh not_active Expired - Fee Related
- 2004-08-04 CN CNB2004100702833A patent/CN100409456C/zh not_active Expired - Fee Related
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2005
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Cited By (11)
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TWI471943B (zh) * | 2007-01-08 | 2015-02-01 | Vishay Siliconix | 平面化金屬化高密度功率金屬氧化物半導體場效電晶體 |
US9437729B2 (en) | 2007-01-08 | 2016-09-06 | Vishay-Siliconix | High-density power MOSFET with planarized metalization |
US9947770B2 (en) | 2007-04-03 | 2018-04-17 | Vishay-Siliconix | Self-aligned trench MOSFET and method of manufacture |
US9431530B2 (en) | 2009-10-20 | 2016-08-30 | Vishay-Siliconix | Super-high density trench MOSFET |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
US10283587B2 (en) | 2014-06-23 | 2019-05-07 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
US10234486B2 (en) | 2014-08-19 | 2019-03-19 | Vishay/Siliconix | Vertical sense devices in vertical trench MOSFET |
US10340377B2 (en) | 2014-08-19 | 2019-07-02 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
US10444262B2 (en) | 2014-08-19 | 2019-10-15 | Vishay-Siliconix | Vertical sense devices in vertical trench MOSFET |
US10527654B2 (en) | 2014-08-19 | 2020-01-07 | Vishay SIliconix, LLC | Vertical sense devices in vertical trench MOSFET |
Also Published As
Publication number | Publication date |
---|---|
JP4843204B2 (ja) | 2011-12-21 |
JP2005057291A (ja) | 2005-03-03 |
CN1581510A (zh) | 2005-02-16 |
CN100409456C (zh) | 2008-08-06 |
US6987305B2 (en) | 2006-01-17 |
TW200507237A (en) | 2005-02-16 |
DE102004036330B4 (de) | 2018-04-05 |
US7510953B2 (en) | 2009-03-31 |
DE102004036330A1 (de) | 2005-03-17 |
CN101075581A (zh) | 2007-11-21 |
US20050029585A1 (en) | 2005-02-10 |
CN101075581B (zh) | 2010-06-09 |
US20060035422A1 (en) | 2006-02-16 |
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