CN1675776A - 制造垂直栅极半导体器件的方法 - Google Patents

制造垂直栅极半导体器件的方法 Download PDF

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CN1675776A
CN1675776A CNA038193590A CN03819359A CN1675776A CN 1675776 A CN1675776 A CN 1675776A CN A038193590 A CNA038193590 A CN A038193590A CN 03819359 A CN03819359 A CN 03819359A CN 1675776 A CN1675776 A CN 1675776A
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戈登·M·格里芙娜
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Semiconductor Components Industries LLC
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Abstract

一种制造半导体器件(10)的方法，包括在半导体衬底(14，16)的水平表面上形成的多层结构(17，18，19，20)的第一垂直表面(41)上淀积第一导电层(50)。第一导电层(50)控制在垂直于第一表面的第二表面(40)上的半导体器件的沟道(70)。该方法进一步包括在多层上形成在第一导电层(50)和垂直表面之间的第一电介质膜(32)，蚀刻它以在多层结构中形成的控制电极(68)和第一导电层(50)之间形成间隙(53)并将导电材料(50)淀积在该间隙中以将第一导电层电连接到控制电极。

Description

制造垂直栅极半导体器件的方法
技术领域
本发明一般涉及半导体器件，更具体地说，涉及垂直栅极晶体管。
背景技术
人们一直需要具有更高级的性能和更低制造成本的半导体器件。例如，开关调节器的制造商需要更高效率的功率MOSFET晶体管用于切换形成调节的输出电压的电感器电流。通过利用具有更短沟道的晶体管提供更高的频率响应以减小调节器的开关损失来实现更高的效率。
然而，最早的高频功率晶体管要求能够分辨细小特征尺寸的高级光刻设备以提供减小开关损失所需要的更短长度的沟道。其它的高频率晶体管形成有垂直的栅极结构，在这种结构中沟道长度由淀积的栅极电极的厚度确定而不是光刻工具的特征尺寸确定。这种方法使得不再需要昂贵的光刻设备并且减小了构造器件的成本。然而，已有的垂直栅极器件要求大量的掩模步骤和复杂序列的处理步骤，这导致了较低的芯片产量和较高的制造成本。
发明内容
因此，需要一种具有用于有效高频操作的更短沟道的半导体器件，这种半导体器件以简单序列的处理步骤和较低的成本制造工具制造。
附图说明
附图1所示为在第一制造阶段之后半导体器件的横截面视图；
附图2所示为在第二制造阶段之后半导体器件的横截面视图；
附图3所示为在第三制造阶段之后半导体器件的横截面视图；
附图4所示为在第四制造阶段之后半导体器件的横截面视图；
附图5所示为在第五制造阶段之后半导体器件的顶视图；
附图6所示为在第六制造阶段之后半导体器件的横截面视图；
附图7所示为在第七制造阶段之后半导体器件的横截面视图；
附图8所示为在第一制造阶段之后变型半导体器件的横截面视图；
附图9所示为在第二制造阶段之后变型半导体器件的横截面视图；
附图10所示为在第三制造阶段之后变型半导体器件的横截面视图；和
附图11所示为在第四制造阶段之后变型半导体器件的横截面视图。
具体实施方式
在附图中，具有相同的参考标号的元件具有类似的功能。
附图1所示为在第一处理阶段之后形成有半导体衬底12的半导体器件10的横截面视图。在一个实施例中，半导体器件10形成有多个有源和无源部件以用作集成电路。
底层14被形成为具有大约250微米的厚度。在一个实施例中，底层14被高浓度掺杂以使其具有p-型导电性和大约0.01欧姆-厘米的电阻率以用作半导体器件10的接地平面。底层14的上部部分可以包括其厚度在大约6和7微米之间和其电阻率在大约2和3欧姆-厘米之间的p-型外延区。在一个实施例中，底层14包括单晶硅。
外延层16在底层14上生长到在大约0.5和0.7微米之间的厚度。在一个实施例中，外延层16包括被掺杂成使其具有n-型导电性并具有大约1.0*1016和大约1.5*1016原子/厘米3之间的掺杂浓度的单晶硅。
电介质层17形成在外延层16上且其厚度为大约700埃。在一个实施例中，电介质层17以热生长的二氧化硅形成。
衬底12被掩蔽并进行一系列的蚀刻步骤以形成以电介质材料2比如二氧化硅填充的浅隔离区。进一步的掩蔽步骤和一系列的蚀刻用于光学地形成与电介质材料4对齐并以半导体材料5填充的深沟槽的阵列，如图所示。在制造周期的后期可以清除半导体材料5以形成空气间隙，这产生了适合于形成高频无源部件和/或焊盘(未示)的低电介质常数区。可替换地，半导体材料5可以连同在深沟槽之间的半导体材料一起被氧化以形成低电介质常数二氧化硅的连续区。在一个实施例中，电介质材料4包括二氧化硅，半导体材料5包括多晶硅。
光刻掩模用于对衬底12构图以对将n-型掺杂剂注入衬底12形成轻微掺杂的漏极(LDD)区21的注入步骤进行掩蔽。在另一光刻掩模之后进行另一注入步骤以将p-型掺杂剂注入到衬底12以形成高浓度的掺杂的本体增强区22，如图所示。
垫层电介质层18形成在电介质层17且其厚度为大约1500埃。在一个实施例中，电介质层18包括淀积的氮化硅。
垫层电介质层19形成在电介质层18且其厚度为大约8000埃。在一个实施例中，电介质层19包括淀积的二氧化硅。
深沟槽被蚀刻并以掺杂的半导体材料填充以形成衬底触点23。在一个实施例中，衬底触点23由高浓度掺杂的p-型多晶硅形成以提供到本体增强区22和底层14的低电阻电连接。然后热氧化在衬底触点23中的半导体材料以形成电介质帽24。
半导体层20形成在电介质层19上且其厚度为大约8000埃。在一个实施例中，半导体层20包括高浓度掺杂的多晶硅。
附图2所示为在第二处理阶段之后半导体器件10的横截面视图。
光掩模(未示)应用在半导体层20上以有选择性地蚀刻半导体层20和电介质层19以在衬底12中形成凹进区33，并且该凹进区33的宽度由垂直表面30确定。然后应用湿氮化物蚀刻以清除电介质层18在凹进区33内的部分。注意，垂直表面30与衬底12的表面40基本垂直地形成以确定如图所示的凸起的支座结构31。在一个实施例中，凹进区33具有在大约2.8和大约3.6微米之间的宽度。在变型实施例中，光掩模和蚀刻步骤也可以用于在LDD区21上形成开口以形成自对准的漏极触点。这种结构将减小由半导体器件10占用的芯片区，由此减小它的制造成本。
电介质材料共形地淀积在衬底12到大约800埃的厚度，然后各向异性地蚀刻以沿垂直表面30形成电介质分隔层32。在一个实施例中，以氮化硅形成电介质分隔层32。
应用二氧化硅湿蚀刻以清除电介质层17位于凹进区33内的部分。延长蚀刻以使从位于分隔层32之下的电介质层17下切割或清除材料以形成凹进的垂直表面34。以这种方式凹进的电介质层17确保了在本体区37中形成的沟道(未示)延伸进外延层16，从而允许沟道电流流动，以及通过增加其沟道长度增加半导体器件10的操作电压和输出阻抗。在一个实施例中，表面34从电介质分隔层32的垂直表面41凹进大约0.1微米的距离。
然后对衬底12进行p型注入。掺杂剂被电介质分隔层32阻挡以形成一个其边界39由垂直表面41界定的本体区37。本体区37具有适合于形成作为如下文描述的半导体器件10的导电沟道操作的反型层的掺杂浓度。
热氧化物在凹进区33内的表面40上生长到150埃的厚度以形成栅电介质35。这个热氧化步骤也在半导体层20的暴露的表面上形成了薄氧化物层36。
附图3所示为在第三制造阶段之后半导体器件10的横截面视图。半导体材料层共形地淀积到大约3000埃的厚度。应用端点各向异性蚀刻，以清除半导体材料的预定的厚度，从而沿作为垂直栅极50设计的垂直表面41形成半导体分隔层。在某些应用中，通过使用附加的光掩模步骤以清除一个垂直栅极(优选离衬底触点23更近的一个)可以改善器件性能。垂直栅极50用于对在本体区37内限定源极区45的注入或扩散步骤进行掩蔽，如图所示。
垂直栅极50的淀积膜厚度有效地建立了在源极区45和外延层16之间沿表面40形成的沟道的长度。由于膜厚度很好地控制并且比用于对半导体器件10构图的光刻工具的最小特征尺寸小得多，因此使用相对低廉的设备可以构造高性能器件。
注意，通过省去使电介质层19凹进的蚀刻步骤并对电介质层18蚀刻以在本体区37上直接形成垂直栅极50，可以形成具有用作基电极的垂直栅极50的双极型晶体管。通过掺杂垂直栅极50以使其具有与本体区37相同的导电型，在垂直栅极50和本体区37之间的欧姆连接被形成作为双极型晶体管的基极。随后的处理如下文所述，其中源极和漏极分别用作双极型器件的发射极和集电极。
电介质材料然后被淀积到大约6000埃的厚度，各向异性地蚀刻以形成在垂直栅极50附近的电介质分隔层52。在一个实施例中，电介质分隔层52以淀积的二氧化硅形成。在本实施例中，各向异性的蚀刻步骤也从在凹进区33内的表面40的暴露的部分中和从半导体层20的暴露表面中清除二氧化硅。
然后应用时控的湿蚀刻以清除电介质分隔层32的材料的一部分，以在垂直栅极50和半导体层20之间形成间隙53。
附图4所示为在第四制造阶段之后的半导体器件10的横截面视图。应用标准光抗蚀剂层并进行构图，以对从半导体层20和电介质层19、18和17中连续地清除材料的一系列蚀刻步骤进行掩蔽以形成开口55，该开口55暴露用作漏极触点57的表面40的区域。
半导体层56淀积为具有大约6000埃的厚度，以填充开口55并涂敷半导体层20和凹进区33的表面，如图所示。半导体层56电接触在漏极触点57上的LDD区21。在一个实施例中，半导体层56包括多晶硅。可替换地，半导体层56可以以正好足够填充间隙53的厚度形成，在这之后热氧化步骤完全氧化了半导体层56的剩余部分。在进一步的变型中，半导体层56全部被省去。作为替换，淀积导电材料层比如钛或铂以填充间隙53，从而在半导体层20的表面形成低电阻硅化物层以用于局部互连。然后使用蚀刻步骤以从没有形成硅化物的非半导体表面清除导电材料。
施加光抗蚀剂层大约6000埃的厚度，但不进行构图。凹进区33相对较窄，以使光抗蚀剂层在凹进区33上比其它的表面更厚。因此，用于清除超过淀积的光抗蚀剂材料的6000埃的端点光抗蚀剂蚀刻将插塞58留在凹进区33内的半导体层56上。
附图5所示为在第五阶段之后半导体器件10的横截面视图。时控的各向同性的半导体蚀刻清除在凹进区33之外的半导体层56的部分，清除插塞58以剩下用于形成到源极区45的电触点的源电极62。执行垫层注入以对半导体层20和源电极62进行掺杂。在一个实施例中，垫层注入引入高浓度n-型掺杂剂以在半导体层20和源电极62内形成低电阻膜。注入步骤之后进行热氧化步骤，该热氧化步骤在暴露的半导体材料上形成二氧化硅膜59。在一个实施例中，热氧化步骤形成具有大约3000埃的厚度的二氧化硅膜59。
附图6所示为在第六制造阶段之后半导体器件10的横截面视图。光掩模对半导体器件10的电极进行构图，随后进行二氧化硅和多晶硅蚀刻，以从在区域63中的二氧化硅膜59和半导体层20中清除材料，从而将漏电极66与栅电极68隔离。蚀刻步骤也清除在区域64内的材料以将相关的栅电极68A与在衬底12上形成的其它部件(未示)隔离。在一个实施例中，栅电极68和相关的栅电极68A在附图6的视平面之外电连接以减小半导体器件10的接通电阻。在变型实施例中，相关的栅电极68A被清除。
附图7所示为在第七制造阶段之后的半导体器件10的横截面视图。
中间层电介质膜69形成在衬底12上。在一个实施例中，电介质膜69包括电极到大约6000埃的厚度的二氧化硅。电介质膜69然后被构图并进行各向同性和各向异性蚀刻以形成到达源电极62、漏电极66和栅电极68的接触开口。
标准金属化层被淀积，然后被构图并蚀刻以形成连接到源电极62的源极端子72、通过栅电极68连接到垂直栅极50的栅极端子74和连接到漏电极66的漏极端子76，以形成可以连接到内部和/或外部部件的功能器件。
半导体器件10的操作如下。假设源极端子72在零伏特的电压Vs下操作，栅极端子74接收大于半导体器件10的导通阈值的控制电压VG＝2.5伏特，以及漏极端子76在漏极电压VD＝5.0伏特下操作。VG和Vs的值使本体区37在垂直栅极50下反型以形成沟道70，从而将源极区45电连接到外延层16。器件电流Is从源极端子72流动，并通过源电极62、源极区45、沟道70、外延层16、LDD区21和漏电极66到达漏极端子76。因此，Is垂直地流经衬底12以形成较低的接通电阻。在一个实施例中，Is＝1.0安。
注意，沟道70的长度由用于形成垂直栅极50的膜的厚度确定。垂直栅极指由淀积在一个表面上的栅极材料形成的、用于控制在另一垂直表面上形成的沟道的控制电极。在半导体器件10的情况下，沟道70形成在表面40上，表面40被看作水平表面。控制电极膜沿与表面40垂直地走向的垂直表面41淀积。结果，沟道长度通过垂直栅极50膜的厚度确定。因此，应用到垂直栅极50的控制信号使本体区37在表面40上反向以形成具有大约等于垂直栅极50的厚度的长度的沟道70。
附图8所示为变型第一制造阶段的半导体器件10的横截面示图。在本实施例中，结构的元件类似于前文所述的元件。导体材料淀积在电介质层19上以形成导体层20A。在一个实施例中，导体层20A以淀积到大约1800埃的厚度的导体材料(比如多晶硅)形成。可替换地，导体材料可以是低阻抗硅化物材料比如钨、钛或它们的硅化物。导体层20A被构图并蚀刻以形成漏电极66和栅电极68。
中间层电介质膜69被淀积到大约6000埃的厚度并被蚀刻以形成凹进区33和支座31。在一个实施例中，以淀积的二氧化硅形成电介质膜69。
对电介质层18进行湿氮化物蚀刻以从凹进区33中清除材料。这个蚀刻步骤可以产生底切电介质层18以使该层在垂直表面30下方凹进。
支座31的垂直表面30用于掩蔽到凹进区33的p-型注入以形成本体区37。
附图9所示为变型第二制造阶段的半导体器件10的横截面视图。
淀积电介质材料并各向异性地蚀刻以形成电介质分隔层32，如图所示。
电介质层17被湿蚀刻以清除在凹进区33内的材料，从而形成凹进的垂直表面34。使用热氧化步骤形成栅极电介质层35。
然后将半导体材料淀积到大约3000埃的厚度。应用垫层n-型注入以对暴露的半导体表面进行掺杂并使用各向异性蚀刻以形成垂直栅极50。在一个实施例中，垂直栅极50被蚀刻以使它们的高度在分隔层32的顶部表面之下大约0.3-0.4微米。
使用氮化物蚀刻以清除一部分电介质分隔层32，从而在垂直栅极50和栅电极68之间形成间隙53。
附图10所示为变型第三制造阶段的半导体器件10的横截面视图。
薄多晶硅层被淀积到大约500埃的厚度并热氧化，以便形成填充间隙53并将垂直栅极50电连接到栅电极68的多晶硅插塞。
然后对衬底12进行垫层n-型注入，这种n-型注入形成其边界由垂直栅极50确定的或与垂直栅极50自对准的源极区45。
将电介质材料施加到大约6000埃的厚度并进行各向异性蚀刻以形成电介质分隔层52。
附图11所示为变型第四制造阶段的半导体器件10的横截面视图。光掩模(未示)对半导体器件10进行构图并且一系列蚀刻步骤形成了以导电材料比如多晶硅填充的开口55，以形成用于在漏极触点57处电连接LDD区21的漏极80。相同的步骤以导电材料填充凹进的区域以形成电连接到源极区45的源极82。
注意，所描述的处理获得了一种容易使用标准的半导体材料制造的高度平面的器件。平面性有利于增加金属互连的一个或多个薄层以形成连接到标准平面金属氧化物半导体或双极性晶体管或其它类型的电部件的电连接，由此形成集成电路。下文不再讨论随后的金属化和中间层电介质处理的细节，因为它类似于前文的描述。
总之，通过本方法提供的短沟道器件具有比以用于制造它的光刻工具可实现的特征尺寸更短的沟道。这种方法形成了低成本、高性能器件，它适合于与其它的电路集成以生产集成电路。将导电层淀积在第一表面上以控制在垂直于第一表面的第二表面上的沟道。蚀刻电介质膜以在半导体器件的第一表面和控制端子之间形成间隙，并将导电材料淀积在该间隙中以将导电层电连接到控制端子。

Claims (9)

1.一种制造半导体器件的方法，包括如下的步骤：
将第一导电层淀积在第一表面上以控制在垂直于所述第一表面的第二表面上的半导体器件的沟道；
蚀刻第一电介质膜以在所述半导体器件的第一表面和所述半导体器件的控制电极之间形成间隙；并
将导电材料淀积在该间隙中以将所述第一导电层电连接到所述控制电极。
2.权利要求1的方法，进一步包括在半导体衬底的所述第二表面上形成本体区以提供所述沟道的步骤。
3.权利要求2的方法，进一步包括在所述半导体衬底上淀积第二导电层以形成所述控制电极的步骤。
4.权利要求3的方法，进一步包括如下的步骤：
在所述第一表面附近的所述第二表面上淀积第二电介质膜；和
在所述第一表面附近的所述第二电介质膜上淀积第三电介质膜。
5.权利要求4的方法，其中淀积所述第二导电层的步骤包括将多晶硅淀积在所述第三电介质膜上以形成所述控制电极。
6.权利要求5的方法，进一步包括如下的步骤：
蚀刻所述第二电介质膜以形成与所述第一表面平行的第一垂直表面；
蚀刻所述第三电介质膜以形成与所述第一垂直表面基本共面的第二垂直表面；和
蚀刻所述第二导电层以形成与所述第一和第二垂直表面基本共面的第三垂直表面。
7.权利要求6的方法，进一步包括在所述第一、第二和第三表面上淀积所述第一电介质膜的步骤。
8.一种制造半导体器件的方法，包括如下的步骤：
蚀刻第一导电材料以便沿垂直表面形成垂直栅极，从而沿半导体衬底的水平表面控制沟道；
蚀刻电介质分隔层以便在半导体器件的垂直栅极和控制电极之间形成间隙；和
将第二导电材料淀积在该间隙中以将所述垂直栅极电连接到所述控制电极。
9.一种制造半导体器件的方法，包括如下的步骤：
蚀刻电介质材料以在第一半导体层的垂直表面的附近形成电介质分隔层；
蚀刻第二半导体层以在所述电介质分隔层的附近形成半导体器件的栅极；
蚀刻电介质分隔层以在所述第一半导体层和栅极之间形成间隙；和
将导电材料淀积在该间隙中以将第一半导体层电连接到该栅极。
CNB038193590A 2002-08-16 2003-07-28 制造垂直栅极半导体器件的方法 Expired - Fee Related CN100435283C (zh)

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WO2004017414A1 (en) 2004-02-26
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