WO2014050793A1 - 半導体装置又は結晶、および、半導体装置又は結晶の製造方法 - Google Patents
半導体装置又は結晶、および、半導体装置又は結晶の製造方法 Download PDFInfo
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- WO2014050793A1 WO2014050793A1 PCT/JP2013/075659 JP2013075659W WO2014050793A1 WO 2014050793 A1 WO2014050793 A1 WO 2014050793A1 JP 2013075659 W JP2013075659 W JP 2013075659W WO 2014050793 A1 WO2014050793 A1 WO 2014050793A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 184
- 239000013078 crystal Substances 0.000 title claims abstract description 130
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 144
- 239000000463 material Substances 0.000 claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 22
- 229910052593 corundum Inorganic materials 0.000 claims description 61
- 239000010431 corundum Substances 0.000 claims description 61
- 238000000034 method Methods 0.000 claims description 30
- 239000000203 mixture Substances 0.000 claims description 21
- 230000007704 transition Effects 0.000 claims description 21
- 239000003595 mist Substances 0.000 claims description 20
- 230000002265 prevention Effects 0.000 claims description 18
- 229910052594 sapphire Inorganic materials 0.000 claims description 17
- 239000010980 sapphire Substances 0.000 claims description 17
- 239000002994 raw material Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- UQSXHKLRYXJYBZ-UHFFFAOYSA-N Iron oxide Chemical compound [Fe]=O UQSXHKLRYXJYBZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 7
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 6
- 239000002904 solvent Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 229910003437 indium oxide Inorganic materials 0.000 claims description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 claims 3
- XHCLAFWTIXFWPH-UHFFFAOYSA-N [O-2].[O-2].[O-2].[O-2].[O-2].[V+5].[V+5] Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[V+5].[V+5] XHCLAFWTIXFWPH-UHFFFAOYSA-N 0.000 claims 3
- 229910000423 chromium oxide Inorganic materials 0.000 claims 3
- 229910000428 cobalt oxide Inorganic materials 0.000 claims 3
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(ii) oxide Chemical compound [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 claims 3
- 229910001935 vanadium oxide Inorganic materials 0.000 claims 3
- 239000010408 film Substances 0.000 description 195
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 17
- 229910052757 nitrogen Inorganic materials 0.000 description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 6
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 5
- 238000003917 TEM image Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZVYYAYJIGYODSD-LNTINUHCSA-K (z)-4-bis[[(z)-4-oxopent-2-en-2-yl]oxy]gallanyloxypent-3-en-2-one Chemical compound [Ga+3].C\C([O-])=C\C(C)=O.C\C([O-])=C\C(C)=O.C\C([O-])=C\C(C)=O ZVYYAYJIGYODSD-LNTINUHCSA-K 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- KAGOZRSGIYZEKW-UHFFFAOYSA-N cobalt(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Co+3].[Co+3] KAGOZRSGIYZEKW-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- QDOXWKRWXJOMAK-UHFFFAOYSA-N dichromium trioxide Chemical compound O=[Cr]O[Cr]=O QDOXWKRWXJOMAK-UHFFFAOYSA-N 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- KFAFTZQGYMGWLU-UHFFFAOYSA-N oxo(oxovanadiooxy)vanadium Chemical compound O=[V]O[V]=O KFAFTZQGYMGWLU-UHFFFAOYSA-N 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 229910021642 ultra pure water Inorganic materials 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/16—Oxides
- C30B29/22—Complex oxides
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
- C30B29/16—Oxides
- C30B29/20—Aluminium oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02609—Crystal orientation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02623—Liquid deposition
- H01L21/02628—Liquid deposition using solutions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
Definitions
- the present invention relates to a semiconductor device or a crystal suitably used for power applications.
- SiC silicon carbide
- GaN gallium nitride
- the present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device in which a good insulating film is formed.
- the present invention is a semiconductor device or a crystal formed using a base substrate having a corundum crystal structure, a semiconductor layer, and an insulating film.
- a base substrate having a corundum type crystal structure many oxide films are included and not only can function as an insulating film, but also the base substrate, the semiconductor layer and the insulating film all have a corundum type crystal structure. Therefore, a high-quality semiconductor layer and insulating film can be realized on the base substrate.
- the base substrate, the semiconductor layer, and the insulating film having a corundum type crystal structure are crystal-grown using means such as CVD.
- Examples of materials having a corundum crystal structure include sapphire (Al 2 O 3 ), gallium oxide (Ga 2 O 3 ), indium oxide (In 2 O 3 ), chromium oxide (Cr 2 O 3 ), and iron oxide (Fe 2 O 3 ), titanium oxide (Ti 2 O 3 ), vanadium oxide (V 2 O 3 ), cobalt oxide (Co 2 O 3 ), and a mixed crystal obtained by combining these plural materials.
- the base substrate and the semiconductor layer are formed by homoepitaxial growth with the same semiconductor composition, no crystal defects due to lattice constant mismatch occur, or the lattice constant of the semiconductor layer is ⁇ 15 of the lattice constant of the base substrate.
- the lattice constant of the semiconductor layer is ⁇ 15 of the lattice constant of the base substrate.
- crystal defects due to lattice constant mismatch are unlikely to occur.
- Some materials having a corundum crystal structure have a relatively large band gap value, and when the impurity species and the impurity concentration are controlled and used as a semiconductor layer and an insulating layer, good characteristics can be realized. If the lattice constant difference is within 5%, crystal defects due to lattice constant mismatch are less likely to occur.
- each X value needs to satisfy the condition that the difference in lattice constant is 15% or less, but X1, Y1, X2, Y2, X3, and Y3 are specifically, for example, 0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2 and may be within a range between any two of the numerical values exemplified here. Specifically, X + Y is, for example, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, 2.5. It may be within the range between any two of the numerical values exemplified here.
- the base substrate and the semiconductor layer, the semiconductor layer and the insulating film, or the base substrate, the semiconductor layer, and the insulating film can all be formed using different materials having different corundum crystal structures and different compositions.
- X1, Y1, Z1, X2, Y2, and Z2 are, for example, 0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, respectively. 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2 It may be within a range between any two of the numerical values exemplified here.
- X1 + Y1 + Z1, X2 + Y2, and X2 + Y2 + Z2 are specifically, for example, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2, respectively. .4, 2.5, which may be in the range between any two of the numerical values exemplified here, or a material different from only one of the three layers of the base substrate, the semiconductor layer, and the insulating film, You may form with a different composition.
- the base substrate 6 may be any substrate having a corundum crystal structure.
- the semiconductor layer 5 easily functions as a semiconductor when In or Ga is contained, it is preferable that 0.1 ⁇ X1 or 0.1 ⁇ Z1. Further, in order to impart conductivity to the semiconductor layer 5, a donor or acceptor level may be formed by oxygen deficiency, oxygen excess, metal deficiency, or metal excess instead of doping with impurities. . In this case, X1 + Y1 + Z1 ⁇ 2. In addition, the semiconductor layer 5 is preferably 0.1 ⁇ X1 and 0.1 ⁇ Z1 because an effect of increasing the carrier concentration and controlling the mobility when both In and Ga are contained can be expected. . X1, Y1, and Z1 are each preferably 0.1 or more.
- the insulating film 4 contains Al and Ga in a predetermined amount or more, in addition to the expectation of a high breakdown electric field, it is high with a semiconductor layer made of ⁇ -type In X1 Al Y1 Ga Z1 O 3. Has affinity. Therefore, in the above general formula, it is preferable that 0.1 ⁇ X2 and 0.1 ⁇ Y2. Further, when Y2 indicating the Al content of the insulating film is larger than Y1 indicating the Al content of the semiconductor layer, the gate formed on the insulating film side because the insulating film is larger in band gap than the semiconductor layer. It is preferable that Y2> Y1 because an advantage is obtained in that carriers are not moved and accumulated on the insulating film side even when a voltage is applied to the electrode, and an accumulation of carriers at the semiconductor-insulating film interface is helped.
- a crystalline stress relaxation layer having a corundum crystal structure can be formed as an intermediate layer.
- the crystalline stress relaxation layer is effective in reducing the stress generated at the interface between different materials and maintaining good crystal quality in the interface and each layer. Further, when there is an unexpected current path in the base substrate, an effect of reducing current leakage derived from the base substrate may be expected.
- the buffer layer may be formed of a low crystal quality film grown at a low temperature between the base substrate and the semiconductor layer, but the crystalline stress relaxation layer has crystallinity that is not significantly different from that of the semiconductor layer or the base substrate. It is characterized by that. This is because common buffer layers have different crystal structures
- ⁇ -type Al X1 Ga Y1 O 3 (0 ⁇ X1) in which ⁇ -type sapphire Al 2 O 3 is used for the base substrate 10 and the amount of Al is gradually reduced as the crystalline stress relaxation layer 9.
- the total number of different materials in the crystalline stress relaxation layer may be one or more.
- X1, Y1, X2, Y2, Z2, X3, and Y3 are, for example, 0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0, respectively. 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2 It may be within the range between any two of the numerical values exemplified here.
- X1 + Y1, X2 + Y2 + Z2, and X3 + Y3 are specifically, for example, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2 .4, 2.5, and may be within a range between any two of the numerical values exemplified here.
- a cap layer having a corundum crystal structure can be formed between the semiconductor layer and the insulating film. Unlike the buffer layer formed between the base substrate and the semiconductor layer, the cap layer is formed between the semiconductor layer and the insulating film.
- the insulating film is expected to be thin in order to efficiently transmit an electric field generated by a voltage applied to a metal formed on the insulating film. Therefore, the stress generated in the insulating film is small due to the mismatch of the lattice constant existing at the interface between the semiconductor film and the insulating film, and there is no need to relax the stress.
- the cap layer has the effect of improving the reliability of the corundum crystal film.
- a current path generated between the semiconductor layer and the insulating film can be reduced.
- the small holes existing in the corundum crystal film can be reduced, the entry of external impurities such as hydrogen atoms is prevented.
- ⁇ -type sapphire Al 2 O 3 is used for the base substrate 15, and ⁇ -type Al X1 Ga Y1 O 3 (0 ⁇ X1) in which the amount of Al is gradually reduced as the crystalline stress relaxation layer 14.
- the total number of different materials for the crystalline stress relaxation layer and the cap layer may be one or more.
- X1, Y1, X2, Y2, Z2, X3, Y3, X4, and Y4 are specifically, for example, 0, 0.1, 0.2, 0.3, 0.4, 0.5, 0 .6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1 .9, 2 and may be within a range between any two of the numerical values exemplified here.
- X1 + Y1, X2 + Y2 + Z2, X3 + Y3, and X4 + Y4 are specifically, for example, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3. 2.4, 2.5, and may be within a range between any two of the numerical values exemplified here.
- the base substrate and the semiconductor layer, or the semiconductor layer and the insulating film are formed of different materials having a corundum crystal structure, the semiconductor layer and the insulating film, the base substrate and the semiconductor layer, and the crystalline stress relaxation layer, the semiconductor layer, and the cap It is also possible to form a structural phase transition prevention layer having a corundum crystal structure between the layer and the insulating film.
- a corundum type is formed by forming a structural phase transition prevention layer. It is possible to prevent a change from a crystal structure to a different crystal structure.
- the formation temperature of the crystalline stress relaxation layer, the semiconductor layer, the cap layer, and the insulating film is lowered in order to prevent the phase transition of the crystal structure, the crystallinity is lowered. Therefore, it is difficult to suppress the change of the crystal structure by lowering the film formation temperature, and the formation of the structural phase transition prevention layer is effective.
- the Al content (X2 value) of the structural phase transition prevention layer 17 is larger than the Al content (Y1 value) in the semiconductor layer and smaller than the Al content (X3 value) in the insulating film.
- the total number of different materials in the structural phase transition prevention layer may be one or more.
- X1, Y1, Z1, X2, Y2, Z2, X3, and Y3 are, for example, 0, 0.1, 0.2, 0.3, 0.4, 0.5, and 0.6, respectively. 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 2 and may be within a range between any two of the numerical values exemplified here.
- X1 + Y1 + Z1, X2 + Y2, and X3 + Y3 are each specifically, for example, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2 .4, 2.5, and may be within a range between any two of the numerical values exemplified here.
- the semiconductor device manufacturing method or the crystal manufacturing method is not particularly limited.
- the semiconductor device and the crystal manufacturing method are produced by misting a raw material solution in which a solute that is a raw material of the semiconductor layer and the insulating film is dissolved in a solvent. Supplying a raw material mist to the film forming chamber.
- the method includes a step of reacting the raw material mist in the film formation chamber to form the semiconductor layer and the insulating film on the base substrate.
- at least one of the semiconductor layer and the insulating film is formed of a mixed crystal film, and the mixed crystal film is formed using a raw material solution in which two or more kinds of solutes are dissolved in a solvent.
- At least one of the semiconductor layer and the insulating film is a mixed crystal film, and the mixed crystal film simultaneously introduces a raw material mist generated by separately misting two or more kinds of raw material solutions into the film forming chamber. It is formed by doing.
- a support substrate is attached to the surface that is not the base substrate, and then the base substrate is subjected to hydrogen ion implantation, heat treatment, etc. By peeling through the steps, it is possible to form a semiconductor manufacturing apparatus using a support substrate in which the semiconductor layer and the insulating film are corundum crystals but are not corundum crystals.
- the support substrate is any one of a SiC substrate, a Si substrate, a metal substrate, a ceramic substrate, and a glass substrate.
- the support substrate is attached to a surface that is not the base substrate via a bonding layer.
- the bonding layer is formed of a silicon oxide film.
- a substrate that is not a corundum crystal can be used as a support substrate, it is possible to use a substrate with better heat dissipation and reduce the substrate cost. It is also possible to change the order of film formation, such as forming an insulating film on a base substrate and forming a semiconductor layer thereon. Thereby, the procedure of device processes such as ion implantation, etching, and photolithography can be simplified.
- a film forming apparatus 19 shown in FIG. 6 is a mist CVD apparatus and has the following configuration. That is, the film forming apparatus 19 includes a film formation sample 20 such as a base substrate, a sample stage 21, a nitrogen source 22, a flow rate adjusting valve 23 for adjusting the flow rate of nitrogen sent from the nitrogen source 22, and a solution 24a.
- the chamber 27 and a heater 28 installed at the periphery or lower part of the film forming chamber 27 are provided.
- the temperature of the film forming chamber 27 is raised to a predetermined temperature (for example, 300 to 550 ° C.) by the heater 28. Thereafter, a film formation sample 20 such as a base substrate is placed on the sample stage 21 in the film formation chamber 27.
- a predetermined temperature for example, 300 to 550 ° C.
- the atmosphere in the film formation chamber is sufficiently replaced with nitrogen gas sent from the nitrogen source 22 in advance, and then the vibration of the ultrasonic transducer 26 is started.
- the ultrasonic vibrator 26 vibrates at a predetermined frequency (for example, 2.4 MHz)
- the vibration propagates to the solution 24a through the water 25a, and mist is generated from the solution 24a.
- the generated mist is pushed out by the nitrogen sent from the nitrogen source 22 and introduced into the film forming chamber 27 after the temperature rise.
- the mist introduced into the film forming chamber 27 reaches the surface of the film formation target sample 20 on which the corundum crystal film is to be formed while being decomposed at a high temperature. Then, a CVD reaction occurs on the surface of the deposition target sample 20, and a corundum crystal film is formed. As a result, at least a part of the surface on which the mist has reached is covered with the corundum crystal film.
- the solution 24a is composed of gallium acetylacetonate as a solute and ultrapure water as a solvent, a gallium oxide film is formed.
- the film forming apparatus 19 can form corundum crystal films shown in the following table. [Corundum crystal material and composition]
- Table 1 shows examples of crystal film seeds constituting a base substrate having a corundum crystal structure, a semiconductor layer, and an insulating film, and solutes and solvents used for film formation.
- the corundum crystal film forming the base substrate, the semiconductor layer, and the insulating film may be a single composition film or a mixed crystal film.
- mist may be generated from the solution 13a in which two or more kinds of solutes are mixed, or two or more kinds of mist generated separately may be introduced into the film forming chamber 16 at the same time.
- the base substrate with the corundum crystal film is taken out from the film forming chamber 16.
- the film forming process of the semiconductor device according to the present invention is completed, and the process proceeds to a device process such as ion implantation, etching, or photolithography.
- ⁇ -type sapphire Al 2 O 3 is used as a base substrate by a mist CVD method using a film forming apparatus 10C, and ⁇ -type gallium oxide Ga 2 O 3 film (FIG. 7) and ⁇ -type are used as semiconductor layers.
- the base substrate, the semiconductor layer, and the insulating film may be formed using various materials and compositions. These materials and mixed crystals thereof may be used.
- the base substrate, the semiconductor layer, and the insulating film may all be the same film, or may be formed using a semiconductor material or semiconductor composition having a lattice constant difference within 15% of the lattice constant of the base layer of each film. May be.
- a layer formed of a different material / composition may be formed between the base substrate, the semiconductor layer, and the insulating film having a corundum crystal structure.
- a crystalline stress relaxation layer having a corundum crystal structure may be formed between the base substrate and the semiconductor layer, or a cap layer having a corundum crystal structure or a structural phase transition between the semiconductor layer and the insulating film.
- a prevention layer may be formed.
- a plurality of these crystalline stress relaxation layers, cap layers, and structural phase transition prevention layers may be formed in combination.
- each of the corundum crystal films forming the base substrate, the semiconductor layer, and the insulating film can have a multilayer structure in which a plurality of single composition films or mixed crystal films are stacked. With a multilayer structure, crystallinity can be improved, current can be increased, and reliability can be improved.
- the crystalline stress relaxation layer is formed of one or more layers having a corundum crystal structure.
- a film may be used.
- the crystalline stress relaxation layer is an ⁇ -type sapphire substrate and a semiconductor layer
- the cap layer is a variety of dislocations such as blade dislocations, screw dislocations, and basal plane dislocations derived from the difference in lattice constant between the semiconductor layer and the insulating film. The effect can be expected to reduce.
- the structural phase transition prevention layer may be formed in the following cases.
- An ⁇ -type Ga 2 O 3 film is formed as a semiconductor layer on an ⁇ -type sapphire base substrate, and an ⁇ -type Al X Ga Y O 3 (0 ⁇ X ⁇ 2, 0 ⁇ Y) having excellent crystallinity as an insulating film is formed thereon.
- ⁇ 2, X + Y 1.5 to 2.5
- an ⁇ -type Al X Ga Y O 3 (0) having a smaller Al composition ratio than the insulating film as a cap layer between the semiconductor and the insulating film.
- ⁇ X ⁇ 2, 0 ⁇ Y ⁇ 2, X + Y 1.5 to 2.5
- a film having a higher crystallinity can be formed by setting the film forming temperature to 530 ° C. or higher.
- a film formation temperature of 530 ° C. or higher if an insulating film is formed without a cap layer, a part of the semiconductor layer and the insulating film may have undergone a structural phase transition to ⁇ -type. is there.
- the film is formed at a temperature of 530 ° C or higher.
- the base substrate, the semiconductor layer, and the insulating film may be formed in the order of the base substrate, the semiconductor layer, and the insulating film from the bottom, or may be formed in the order of the base substrate, the insulating film, and the semiconductor layer. Therefore, the semiconductor device or crystal of this embodiment includes a semiconductor layer and an insulating film on a base substrate in this order or in the reverse order, and the base substrate, the semiconductor layer, and the insulating film are All have a corundum crystal structure.
- the base substrate may be peeled off and fixed to another support substrate.
- the following procedure may be used.
- a silicon oxide film is formed over the semiconductor layer.
- a support substrate in which a silicon oxide film is formed on a SiC substrate or a Si substrate is prepared and bonded to a silicon oxide film on a semiconductor layer, and then the base substrate is peeled off.
- This silicon oxide film functions as a bonding layer.
- ion implantation such as hydrogen ions
- a heating / cooling step plasma treatment
- any metal oxide film having a corundum crystal structure included in Table 1 may be used as the base substrate, and semiconductor substrates such as Si, SiC, GaAs, and GaN, ceramic films, metal substrates, and glass substrates may be used as the support substrate. Etc. may be used.
- a layer formed of a different material / composition may be formed between the base substrate, the semiconductor layer, and the insulating film having a corundum crystal structure.
- a crystalline stress relaxation layer having a corundum crystal structure may be formed between the base substrate and the semiconductor layer, or a cap layer having a corundum crystal structure or a structural phase transition between the semiconductor layer and the insulating film.
- a prevention layer may be formed.
- a plurality of these crystalline stress relaxation layers, cap layers, and structural phase transition prevention layers may be formed in combination.
- the surface may be polished by a method such as CMP, which allows the crystalline stress relaxation layer, the cap layer, and the structural phase transition prevention layer to be polished. Some or all may be removed.
- the present invention is not limited to the above-described embodiment, and various modifications can be considered.
- a linear source method in which the nozzle is sprayed and the nozzle is moved in a direction perpendicular to the linear outlet, or a method in which a plurality of methods are mixed or derived may be used.
- a carrier gas a gas such as argon, oxygen, ozone, or air can be flowed instead of nitrogen, and the film formation chamber may be pressurized or depressurized instead of atmospheric pressure.
- mold crystal film was formed by mist CVD method, you may form by another method.
- Other methods that can form a corundum crystal film include metal organic chemical vapor deposition and molecular beam epitaxy.
- an appropriate element for example, tin, silicon, etc.
- a corundum crystal film is used for a base substrate having a corundum crystal structure, a semiconductor film, an insulating film, a crystalline stress relaxation layer, a cap layer, and a structural phase transition prevention layer.
- Magnesium may be doped.
- a semiconductor film having a corundum crystal structure, an insulating film, a crystalline stress relaxation layer, a cap layer, and a structural phase transition prevention layer are provided with a certain repeating structure with respect to the film composition and element doping concentration. It may be introduced. As a result, it is possible to promote stress relaxation, adjust the carrier concentration, and adjust the carrier mobility.
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Abstract
Description
特にSiCを材料とする高耐圧半導体デバイスにおいては、シリコンと同様、基板表面にMOS構造を形成するSiCMOSFETの開発が進められてきた。
しかし、SiC半導体装置やGaN半導体装置では、多くの解決すべき課題が残されている。なかでも重大な課題は、ノーマリーオフ型の素子構造が困難である問題である。
特にSiCMOSFETのMOS構造においては、良質な絶縁膜の形成が困難であることに起因することが明らかになってきた。これは、結晶性の良い半導体層を形成することに注視するあまり、結晶性が良く良好なデバイス特性が期待されるSiC等の半導体が選択され、そのうえで、熱酸化等の手法による実現可能な絶縁膜の選択、成膜プロセスの検討が行われてきてきたことに因る。
たとえば、図2に示すように、下地基板6にα型サファイアAl2O3、半導体層5に不純物ドープされたα型InX1AlY1GaZ1O3(0≦X1≦2、0≦Y1≦2、0≦Z1≦2、X1+Y1+Z1=1.5~2.5)、絶縁膜4にα型AlX2GaY2O3(0≦X2≦2、0≦Y2≦2、X2+Y2=1.5~2.5)を形成することができる。また、絶縁膜4は、α型Inz2AlX2GaY2O3(0≦X2≦2、0≦Y2≦2、0≦Z2≦2、X2+Y2+Z2=1.5~2.5)であってもよい。
X1、Y1、Z1、X2、Y2、Z2は、それぞれ、具体的には例えば、0、0.1、0.2、0.3、0.4、0.5、0.6、0.7、0.8、0.9、1、1.1、1.2、1.3、1.4、1.5、1.6、1.7、1.8、1.9、2であり、ここで例示した数値の何れか2つの間の範囲内であってもよい。X1+Y1+Z1、X2+Y2、X2+Y2+Z2は、それぞれ、具体的には例えば、1.5、1.6、1.7、1.8、1.9、2、2.1、2.2、2.3、2.4、2.5であり、ここで例示した数値の何れか2つの間の範囲内であってもよいし、下地基板と半導体層、絶縁膜の3層のうち、1層のみ異なる材料、異なる組成で形成してもよい。また、下地基板6は、コランダム型の結晶構造を有する任意の基板を使用してもよい。
ここで結晶性応力緩和層の異種材料総数は1以上であれば良い。X1、Y1、X2、Y2、Z2、X3、Y3は、それぞれ、具体的には例えば、0、0.1、0.2、0.3、0.4、0.5、0.6、0.7、0.8、0.9、1、1.1、1.2、1.3、1.4、1.5、1.6、1.7、1.8、1.9、2であり、ここで例示した数値の何れか2つの間の範囲内であってもよい。X1+Y1、X2+Y2+Z2、X3+Y3は、それぞれ、具体的には例えば、1.5、1.6、1.7、1.8、1.9、2、2.1、2.2、2.3、2.4、2.5であり、ここで例示した数値の何れか2つの間の範囲内であってもよい。
半導体装置の製造方法およびコランダム型結晶を成膜する際に使用する成膜装置10Aについて説明する。
[コランダム型結晶材料および組成]
[取り出し]
[膜構造]
2 半導体層
3 下地基板
4 絶縁膜
5 半導体層
6 下地基板
7 絶縁膜
8 半導体層
9 結晶性応力緩和層
10 下地基板
11 絶縁膜
12 キャップ層
13 半導体層
14 結晶性応力緩和層
15 下地基板
16 絶縁膜
17 構造相転移防止層
18 半導体層
19 成膜装置
20 被成膜試料
21 試料台
22 窒素源
23 流量調節弁
24 ミスト発生源
24a 溶液
25 ミスト発生源
25a 水
26 超音波振動子
27 成膜室
28 ヒータ
Claims (28)
- 下地基板上に、半導体層と、絶縁膜とをこの順序で又はこの逆の順序で備え、
前記下地基板、前記半導体層、及び前記絶縁膜は、何れもコランダム型結晶構造を有する半導体装置、又は結晶。 - 前記下地基板、前記半導体層、前記絶縁膜のすべてが、サファイア、酸化ガリウム、酸化インジウム、酸化クロム、酸化鉄、酸化チタン、酸化バナジウム、酸化コバルトのいずれか、あるいは、サファイア、酸化ガリウム、酸化インジウム、酸化クロム、酸化鉄、酸化チタン、酸化バナジウム、酸化コバルトの複数の混晶で形成される、請求項1記載の半導体装置、又は結晶。
- 前記下地基板、前記半導体層、前記絶縁膜のすべてが同一、あるいは格子定数差15%以内の半導体材料および組成を用いて形成される請求項1又は請求項2に記載の半導体装置、又は結晶。
- 前記下地基板、前記半導体層、前記絶縁膜のすべてがα型酸化アルミニウム・ガリウムAlXGaYO3(0≦X≦2、0≦Y≦2、X+Y=1.5~2.5)から形成される請求項3に記載の半導体装置、又は結晶。
- 前記下地基板、前記半導体層、前記絶縁膜の少なくとも一層が、異なる組成を有する請求項1~請求項4の何れか1つに記載の半導体装置、又は結晶。
- 前記下地基板及び前記絶縁膜がサファイア、酸化ガリウム、酸化インジウム、酸化クロム、酸化鉄、酸化チタン、酸化バナジウム、酸化コバルトのいずれか、あるいは、これらの複数の混晶で形成され、前記半導体層がα型InX1AlY1GaZ1O3(0≦X1≦2、0≦Y1≦2、0≦Z1≦2、X1+Y1+Z1=1.5~2.5)から形成される請求項1~請求項5に記載の半導体装置、又は結晶。
- 0.1≦X1又は0.1≦Z1である請求項6に記載の半導体装置、又は結晶。
- 0.1≦X1且つ0.1≦Z1である請求項6又は請求項7に記載の半導体装置、又は結晶。
- 前記下地基板がα型サファイアから形成され、前記絶縁膜がα型AlY2GaZ2O3(0≦Y2≦2、0≦Z2≦2、Y2+Z2=1.5~2.5)から形成される請求項6~請求項8に記載の半導体装置、又は結晶。
- 0.1≦X2且つ0.1≦Y2である請求項9に記載の半導体装置、又は結晶。
- 前記下地基板と前記半導体層との間に、コランダム型結晶構造を有する結晶性応力緩和層を有する請求項1~請求項10の何れか1つに記載の半導体装置、又は結晶。
- 前記下地基板がα型サファイアから形成され、
前記結晶性応力緩和層は、1層以上から形成され、前記下地基板から前記半導体層に向かってAl量を徐々に低減させたα型AlX1GaY1O3(0≦X1≦2、0≦Y1≦2、X1+Y1=1.5~2.5)から形成され、
前記半導体層は、α型InX2AlY2GaZ2O3(0≦X2≦2、0≦Y2≦2、0≦Z2≦2、X2+Y2+Z2=1.5~2.5)から形成され、
前記絶縁膜は、α型AlX3GaY3O3(0≦X3≦2、0≦Y3≦2、X3+Y3=1.5~2.5)から形成される請求項11に記載の半導体装置、又は結晶。 - 前記半導体層と前記絶縁膜との間に、前記半導体層と前記絶縁膜に含まれる元素の少なくとも一部の元素を含むキャップ層を有する請求項1~請求項12の何れか1つに記載の半導体装置、又は結晶。
- 前記下地基板がα型サファイアから形成され、
前記半導体層は、不純物ドープされたα型InX2AlY2GaZ2O3(0≦X2≦2、0≦Y2≦2、0≦Z2≦2、X2+Y2+Z2=1.5~2.5)から形成され、
前記キャップ層は、前記半導体層から前記絶縁膜に向かってAl量を徐々に大きくしたα型AlX3GaY3O3(0≦X3≦2、0≦Y3≦2、X3+Y3=1.5~2.5)から形成され、
前記絶縁膜は、α型AlX4GaY4O3(0≦X4≦2、0≦Y4≦2、X4+Y4=1.5~2.5)から形成される請求項13に記載の半導体装置、又は結晶。 - 前記下地基板と前記半導体層との間に、コランダム型結晶構造を有する結晶性応力緩和層を有し、
前記結晶性応力緩和層は、1層以上から形成され、前記下地基板から前記半導体層に向かってAl量を徐々に低減させたα型AlX1GaY1O3(0≦X1≦2、0≦Y1≦2、X1+Y1=1.5~2.5)から形成される請求項14に記載の半導体装置、又は結晶。 - 前記半導体層と前記絶縁膜との間に、前記半導体層と前記絶縁膜に含まれる元素の少なくとも一部の元素を含む構造相転移防止層を有する請求項1~請求項15の何れか1つに記載の半導体装置、又は結晶。
- 前記半導体層は、不純物ドープされたα型InX1AlY1GaZ1O3(0≦X1≦2、0≦Y1≦2、0≦Z1≦2、X1+Y1+Z1=1.5~2.5)から形成され、
前記構造相転移防止層は、前記半導体層から前記絶縁膜に向かってAl量を徐々に大きくしたα型AlX2GaY2O3(0≦X2≦2、0≦Y2≦2、X2+Y2=1.5~2.5)から形成され、
前記絶縁膜は、α型AlX3GaY3O3(0≦X3≦2、0≦Y3≦2、X3+Y3=1.5~2.5)から形成される請求項16に記載の半導体装置、又は結晶。 - 請求項1~請求項17の何れか1つに記載の半導体装置の製造方法、又は結晶の製造方法であって、
前記半導体層及び前記絶縁膜の原料となる溶質が溶媒中に溶解されてなる原料溶液をミスト化して生成される原料ミストを成膜室に供給する工程を備える、半導体装置の製造方法、又は結晶の製造方法。 - 前記原料ミストを前記成膜室中で反応させて前記下地基板上に前記半導体層及び前記絶縁膜を形成する工程を備える、請求項18に記載の方法。
- 前記半導体層と前記絶縁膜の少なくとも一方が混晶膜からなり、
前記混晶膜は、2種類以上の溶質が溶媒中に溶解されてなる原料溶液を用いて形成される、請求項18又は請求項19に記載の方法。 - 前記半導体層と前記絶縁膜の少なくとも一方が混晶膜からなり、
前記混晶膜は、2種類以上の原料溶液を別々にミスト化して生成される原料ミストを同時に成膜室に導入することによって形成される、請求項18又は請求項19に記載の方法。 - 下地基板上に、半導体層と、絶縁膜とをこの順序で又はこの逆の順序で備え、
前記下地基板は、コランダム型結晶構造を有するか又は有さず、
前記半導体層及び前記絶縁膜は、何れもコランダム型結晶構造を有し、
前記支持基板と前記半導体層の間に、前記支持基板とコランダム型結晶との接合層を有する半導体装置、又は結晶。 - 前記支持基板が、SiC基板、Si基板、金属基板、セラミック基板、ガラス基板のいずれかで形成される請求項22に記載の半導体装置、又は結晶。
- 前記接合層が、酸化シリコン膜で形成される請求項22又は請求項23に記載の半導体装置、又は結晶。
- 下地基板上に、半導体層と、絶縁膜とをこの順序で又はこの逆の順序で形成する結晶形成工程と、
前記下地基板ではない側の面に支持基板を貼り付ける貼り付け工程と、
前記下地基板を剥離する剥離工程を備え、
前記下地基板、前記半導体層、及び前記絶縁膜は、何れもコランダム型結晶構造を有する、半導体装置の製造方法、又は結晶の製造方法。 - 前記支持基板が、SiC基板、Si基板、金属基板、セラミック基板、ガラス基板のいずれかである請求項25に記載の方法。
- 前記支持基板は、接合層を介して、前記下地基板でない側の面に貼り付ける、請求項25又は請求項26に記載の方法。
- 前記接合層が、酸化シリコン膜で形成される、請求項27に記載の方法。
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TW201421542A (zh) | 2014-06-01 |
EP2752869B1 (en) | 2016-11-09 |
US20150194479A1 (en) | 2015-07-09 |
KR101579460B1 (ko) | 2015-12-22 |
JP2014072463A (ja) | 2014-04-21 |
KR20140085414A (ko) | 2014-07-07 |
EP2752869A1 (en) | 2014-07-09 |
EP2752869A4 (en) | 2015-01-07 |
TWI518748B (zh) | 2016-01-21 |
CN110071037A (zh) | 2019-07-30 |
CN110071037B (zh) | 2024-05-14 |
CN104205296A (zh) | 2014-12-10 |
JP5343224B1 (ja) | 2013-11-13 |
US9711590B2 (en) | 2017-07-18 |
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