WO2011111500A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2011111500A1 WO2011111500A1 PCT/JP2011/053549 JP2011053549W WO2011111500A1 WO 2011111500 A1 WO2011111500 A1 WO 2011111500A1 JP 2011053549 W JP2011053549 W JP 2011053549W WO 2011111500 A1 WO2011111500 A1 WO 2011111500A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Definitions
- the present invention relates to a semiconductor device.
- IGBTs insulated gate bipolar transistors
- a trench gate type IGBT in which a gate electrode is formed in a trench provided on the surface of a silicon wafer can increase the density (total channel length) of an inversion layer (channel) of electrons, thereby reducing the on-voltage. it can.
- the trench gate type IGBT has a theoretical limit on the trade-off characteristics between so-called turn-off loss and on-voltage by combining a well-known field stop structure in which a n-type drift layer thickness is reduced by forming a field stop layer for stopping a depletion layer. Is approaching. For this reason, it is difficult to further improve the characteristics of the trench gate type IGBT.
- FIG. 31 is a cross-sectional view showing a main part of a conventional semiconductor device.
- FIG. 31 shows a structure described in Patent Document 1 below.
- the gate trench 7 and the dummy trench 8 are arranged on the front surface of the element so as to be parallel to each other.
- the planar layout of the gate trench 7 and the dummy trench 8 is striped. That is, the gate trench 7 and the dummy trench 8 are formed in stripes in a direction perpendicular to the paper surface of FIG.
- the p-type layer including the p-type base layer 4 is uniformly formed on the surface layer on the front surface side of the element.
- This p-type layer in the mesa region 18 is insulated from the p-type base layer 4 by the gate trench 7. That is, the p-type layer in the mesa region 18 is a floating p layer 30 having a floating potential (floating).
- the floating p layer 30 is also insulated from the emitter electrode 12 by the interlayer insulating film 9.
- the gate trench 7 is filled with gate polysilicon 11a as a control electrode made of polycrystalline (poly) silicon.
- the dummy trench 8 is filled with conductive dummy polysilicon 11 b through a gate oxide film 10.
- the dummy polysilicon 11b is connected to the emitter electrode 12.
- the n-type drift layer is formed by covering a large portion of the surface on the front surface side of the element with the floating p layer 30 and reducing the area of the p-type base layer 4 on the element front surface.
- the holes injected into 1 are accumulated below the p-type base layer 4.
- This effect is called an injection enhancement (IE) effect.
- IE injection enhancement
- FIG. 32 is a cross-sectional view showing a main part of a conventional semiconductor device.
- FIG. 32 is a perspective view of the IGBT structure described in Patent Document 2 below.
- a gate trench 7 is formed on the front surface of a silicon wafer made of the n-type drift layer 1.
- a p-type base layer 4 having an impurity concentration higher than that of the n-type drift layer 1 is selectively formed between adjacent gate trenches 7.
- n-type emitter layer 5 and a p-type contact layer are selectively formed on the front surface layer of the p-type base layer 4.
- the p-type base layer 4 and the n-type drift layer 1 are sequentially provided so as to appear in the mesa region 18, and the p-type base layers 4 are dispersedly arranged.
- the n-type drift layer 1 and the p-type base layer 4 are alternately arranged across the gate trench 7 in the direction orthogonal to the longitudinal direction of the gate trench 7.
- the p-type base layer 4 is arranged in a pattern-like planar layout.
- the p-type base layer 4 is uniformly distributed, so that the electric field distribution in the silicon wafer is also uniform. As a result, it is possible to prevent a reduction in device breakdown voltage.
- the gate trench 7 is filled with a gate polysilicon 11a as a control electrode made of polysilicon with the gate oxide film 10 interposed therebetween. On the portion where the front surface of the gate polysilicon 11a and the n-type drift layer 1 is exposed, an interlayer insulating film (not shown) is formed so as to cover them.
- an emitter electrode (not shown) is formed so as to be in contact with the n-type emitter layer 5 and the p-type base layer 4 in common.
- a contact opening 14 for contacting the emitter electrode is provided on the n-type emitter layer 5 and the p-type base layer 4.
- An n-type field stop layer 2 and a p-type collector layer 3 are formed on the surface opposite to the front surface (back surface) of the n-type drift layer 1.
- a collector electrode (not shown) is provided on the front surface (back surface of the wafer) of the p-type collector layer 3.
- One of the features of the conventional IGBT shown in FIG. 32 is that a device for avoiding the problem of the floating structure described later is devised. That is, the mesa region 18 and the p-type base layer 4 are adjacent to each other so that the mesa region 18 sandwiched between the gate trenches 7 does not have a floating structure, so that the potential of the mesa region 18 can follow the p-type base layer 4. It is that. As a result, gate controllability is ensured so that the rapid increase in current increase rate when the IGBT is turned on due to the floating structure can be easily suppressed by the gate resistance.
- the gate-emitter capacitance is reduced.
- the electric field concentration at the bottom of the trench gate can be relaxed and a high breakdown voltage can be obtained. That is, by narrowing the width of the mesa region 18 sandwiched between the gate trenches 7, the n-type drift layer 1 portion of the mesa region 18 sandwiched between the gate trenches 7 can be easily applied with an applied voltage of about several volts. To be depleted. Thereby, not only can the electric field distribution near the front surface of the element in the off state be equalized, but also the gate-collector capacitance (mirror capacitance) can be reduced.
- the above-mentioned influence due to the increase in the mirror capacitance particularly appears when the IGBT is turned off when it transitions from the on state to the off state.
- the mirror capacitance at this time is the capacitance of the gate oxide film itself.
- the turn-off is started, depletion starts near the pn junction, but the area of the depletion layer end immediately after the depletion layer starts to spread is large and the depletion layer width is extremely small. Further, residual carriers prevent the depletion layer from spreading.
- the mirror capacitance becomes the largest at the turn-off time when the IGBT transitions from the on state to the off state.
- the turn-off time is increased and the rise of the collector-emitter voltage is also delayed, so that the switching loss is increased.
- the mirror capacitance increases at turn-on when the IGBT transitions from the off state to the on state.
- the mirror capacitance In the blocking state before turn-on, the mirror capacitance is sufficiently small because a sufficiently high voltage is applied between the collector and the emitter, and carriers do not exist under the gate oxide film.
- the width of the depletion layer is reduced and carriers are injected.
- the collector-emitter voltage is sufficiently small, the area of the depletion layer edge is increased and the depletion layer width is also reduced, so that the mirror capacitance is increased.
- the fall of the collector-emitter voltage startsing of the decrease
- the switching loss the fall of the collector-emitter voltage (starting of the decrease) is slightly delayed, which also increases the switching loss.
- the IGBT combining the floating p layer 30 and the dummy trench 8 shown in FIG. 31 has the following problems in the turn-on process of the IGBT.
- the potential of the mesa region 18 is floating, the potential of the gate electrode 15 suddenly increases or fluctuates during the turn-on process, and turn-on di / dt (current increase rate at turn-on) increases rapidly.
- the IGBT is turned on, the depletion layer that has spread inside the n-type drift layer 1 in the off state is reduced, and is distributed only on the front surface of the element.
- the holes injected into the n-type drift layer 1 from the p-type collector layer 3 on the back surface of the element flow toward the p-type base layer 4, but the floating p layer 30 occupying most of the front surface of the element. Also flows in. At this time, the concentration of holes in the remaining depletion layer increases. As a result, the electric field strength increases and the potential of the floating p layer 30 rises.
- Such an increase in the potential of the floating p layer 30 also increases the potential of the gate polysilicon 11 a filled in the gate trench 7 adjacent to the floating p layer 30. For this reason, a displacement current is generated in the gate drive circuit through the gate polysilicon 11a. As a result, the potential of the gate electrode 15 increases rapidly, and the collector current increases accordingly. As a result, turn-on di / dt increases rapidly.
- the rise in the potential of the floating p layer 30 is a phenomenon that occurs in a minute time of several tens of ns or less, and depends on the behavior of the depletion layer and holes inside the IGBT. Also, the displacement current flowing through the gate polysilicon 11a to the gate drive circuit is large. Therefore, even if the gate resistance installed between the gate drive circuit and the gate electrode 15 is increased, the turn-on di / dt cannot be reduced, and strong electromagnetic noise is generated in the actual operation of the inverter or the like. No impact.
- Such a phenomenon is more prominent when the dummy polysilicon 11b filled in the dummy trench 8 is connected to the emitter electrode 12. That is, in the turn-on process, the holes injected into the n-type drift layer 1 from the p-type collector layer 3 are more closely connected to the dummy trenches 8 and the gates in the mesa region 18 than in the vicinity of the floating p-layer 30 that is substantially fixed to the emitter potential. It concentrates on the part formed between the trenches 7. As a result, the potential of the portion of the mesa region 18 formed between the dummy trench 8 and the gate trench 7 is increased more and steeply, and the turn-on di / dt control by the gate resistance is extremely difficult. It will be a thing.
- the potential of the mesa region 18 between the dummy trench 8 and the gate trench 7 must be fixed. For this purpose, it is necessary to connect the mesa region 18 between the dummy trench 8 and the gate trench 7 to the emitter electrode 12. But this has another major reaction. That is, when the mesa region 18 between the dummy trench 8 and the gate trench 7 is connected to the emitter electrode 12, holes injected from the p-type collector layer 3 into the n-type drift layer 1 are from the connection portion with the emitter electrode 12. Since it is pulled out by the emitter, the IE effect is significantly reduced. As a result, the controllability of the turn-on di / dt due to the gate resistance is restored, but at the expense of increasing the on-voltage.
- the dummy trench 8 is provided to reduce the mirror capacitance, and (2) the mesa region 18 between the gate trench 7 and the dummy trench 8 is formed.
- FIG. 32 there is a semiconductor element having the above-described IGBT structure shown in FIG. 32 as a semiconductor element capable of achieving both the problem that the turn-on di / dt rapidly increases in a short time and the IE effect.
- the IGBT shown in FIG. 32 enhances the IE effect and lowers the on-voltage as described above, and at the same time significantly improves the controllability of turn-on di / dt by adjusting the gate resistance and the like.
- the conventional IGBT shown in FIG. 32 still has a problem that the mirror capacitance (gate-collector capacitance) is not sufficiently reduced, and the switching characteristics are deteriorated as described above.
- An object of the present invention is to provide a semiconductor device having a small mirror capacitance in order to solve the above-described problems caused by the conventional technology. Another object is to provide a semiconductor device with low on-voltage. Another object of the present invention is to provide a semiconductor device with low switching loss.
- a semiconductor device includes a first semiconductor layer of a first conductivity type and a first semiconductor layer provided on the first semiconductor layer.
- a plurality of first conductivity type third semiconductor layers selectively formed in the longitudinal direction between the first grooves, and a second conductivity selectively formed on the surface of the third semiconductor layer.
- an insulated gate semiconductor device having a fourth semiconductor layer of a type, an emitter electrode in contact with the third semiconductor layer and the fourth semiconductor layer, and a collector electrode in contact with the first semiconductor layer Provided between the first grooves in parallel with the first grooves, and two of the third grooves Wherein the second groove sandwiched between the semiconductor layer is formed one or more.
- a feature of the structure of the semiconductor device according to the present invention is that a p-type base layer (third layer) selectively formed in a mesa region sandwiched between two adjacent stripe-shaped gate trenches (first grooves). One or more dummy trenches (second grooves) are provided between the semiconductor layers. According to the present invention, the mirror capacity is reduced due to the above structural features.
- a first conductor is embedded in the second groove through an insulating film, and the first conductor is connected to the gate electrode.
- the separation means that it is electrically insulated.
- the depletion layer spreads from the sidewall of the dummy trench as well as the gate trench. Therefore, the depletion layer extending from each of the gate trench and the dummy trench contacts at a smaller applied voltage, and as a result, the mirror capacitance is reduced.
- the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first conductor is connected to the emitter electrode.
- the depletion layer is pinched off with a sufficiently small applied voltage, and the first conductor is always at the same potential as the emitter electrode, the mirror capacitance is further reduced.
- the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first conductor is connected to the emitter electrode at an end in a longitudinal direction of the second groove.
- the semiconductor device according to the present invention is characterized in that, in the above-described invention, two or more of the second grooves formed between the adjacent first grooves are formed.
- the distance between the first groove and the second groove or the distance between adjacent second grooves is reduced, and the mesa region is depleted with a smaller applied voltage. .
- the mirror capacity is further reduced.
- the first conductors formed in one or more of the second grooves formed are electrically connected to each other at the same potential. It is characterized by being connected.
- the present invention by setting the potential of the first conductor formed in the plurality of second grooves to the same potential, it is possible to stably follow fluctuations in the potential, and the mirror capacitance. Can be stabilized.
- the second grooves adjacent to each other are connected to each other at an end portion in the longitudinal direction of the second groove, and the inside of the second groove
- the first conductors formed on each other are connected to each other at the end portions.
- the first conductors formed inside the adjacent second grooves are connected to the upper surfaces of the adjacent second grooves.
- a second conductor in contact with the first conductor is formed, and the second conductor is connected to the emitter electrode at a part of the second conductor.
- the emitter electrode, the collector electrode, the gate electrode, and the first conductor are separated so that the first conductor has a floating potential. It is characterized by.
- the first conductor may be a floating potential.
- the mask layout and the manufacturing process can be facilitated while having the same effect as the above-described invention for the second groove and the first conductor formed therein.
- the first groove and the second groove are on the side wall in the longitudinal direction of the first groove or the side wall in the longitudinal direction of the second groove. Are adjacent to each other.
- the distance between the first groove and the second groove is the second semiconductor layer and the third semiconductor layer in a thermal equilibrium state. It is smaller than the built-in depletion layer width extending from the pn junction to the second semiconductor layer.
- the depletion layer extending from the first groove is applied to the applied voltage between the collector and the emitter. Is low, pinch-off occurs, and the area of the equipotential surface decreases.
- the distance between the second groove and the first groove or the distance between the adjacent second grooves is reduced.
- the width of the effective mesa region is narrowed, so that the IE effect is improved.
- switching speed or switching loss can be reduced by reducing the mirror capacity.
- the semiconductor device of the present invention it is possible to obtain a semiconductor device having a small mirror capacity.
- the semiconductor device having a low on-voltage can be obtained.
- the semiconductor device having a small switching loss can be obtained.
- FIG. 1 is a perspective view illustrating a main part of the semiconductor device according to the first embodiment.
- FIG. 2 is a cross-sectional view taken along a cutting line A-A ′ in FIG.
- FIG. 3 is a characteristic diagram showing electrical characteristics between the capacitance and the collector-emitter voltage according to the first embodiment.
- FIG. 4 is a perspective view illustrating a main part of the semiconductor device according to the second embodiment.
- FIG. 5 is a cross-sectional view taken along section line B-B ′ of FIG. 6 is a plan view showing the semiconductor device of FIG.
- FIG. 7 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the third embodiment.
- FIG. 8 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the fourth example.
- FIG. 1 is a perspective view illustrating a main part of the semiconductor device according to the first embodiment.
- FIG. 2 is a cross-sectional view taken along a cutting line A-A ′ in FIG.
- FIG. 3 is
- FIG. 9 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the fifth example.
- FIG. 10 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the sixth example.
- FIG. 11 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the seventh embodiment.
- FIG. 12 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to Example 8.
- FIG. 13 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Working Example 9.
- FIG. 14 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Working Example 10.
- FIG. 15 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Example 11.
- FIG. 16 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Working Example 12.
- FIG. 17 is a cross-sectional view illustrating a main part of the semiconductor device according to the third embodiment.
- FIG. 18 is a plan view illustrating the main part of the semiconductor device according to the fourth embodiment.
- FIG. 19 is a cross-sectional view illustrating a main part of the semiconductor device according to the fifth embodiment.
- FIG. 20 is a plan view showing a main part of the IGBT of FIG.
- FIG. 21 is a perspective view of a relevant part of the semiconductor device according to the sixth embodiment.
- FIG. 22 is a cross-sectional view illustrating a main part of the semiconductor device according to the seventh embodiment.
- FIG. 23 is a perspective view of a relevant part of the semiconductor device according to the eighth embodiment.
- 24 is a cross-sectional view taken along the section line C-C ′ of FIG.
- FIG. 25 is a cross-sectional view illustrating a main part of the semiconductor device according to the ninth embodiment.
- FIG. 26 is a perspective view of the main part of the semiconductor device according to the tenth embodiment.
- FIG. 27 is a cross-sectional view taken along the section line D-D ′ of FIG.
- FIG. 28 is a plan view of the main part of the semiconductor device according to the eleventh embodiment.
- FIG. 29 is a cross-sectional view showing a semiconductor device of a comparative example.
- FIG. 30 is a switching evaluation circuit diagram of the semiconductor device according to the embodiment.
- FIG. 31 is a cross-sectional view showing a main part of a conventional semiconductor device.
- FIG. 32 is a perspective view showing a main part of a conventional semiconductor device.
- FIG. 33 is a cross-sectional view taken along section line AA-AA ′ of FIG.
- FIG. 1 is a perspective view illustrating a main part of the semiconductor device according to the first embodiment.
- a gate trench 7 having a striped planar shape is formed on one main surface (corresponding to the upper surface in the drawing, hereinafter referred to simply as the upper surface) of the substrate to be the n-type drift layer 1.
- a gate oxide film 10 is formed on the inner wall of the gate trench 7, and a conductive gate polysilicon 11 a is formed inside the gate oxide film 10.
- a p-type base layer 4 in contact with the outer side wall of each gate trench 7 is selectively formed. That is, the p-type base layer 4 is in contact with the gate oxide film 10 formed on the inner wall of each gate trench 7.
- the length of the p-type base layer 4 in the longitudinal direction of the gate trench 7 depends on the characteristics of the IGBT and the design design rule, but may be, for example, about 1 ⁇ m or more and 10 ⁇ m or less.
- the distance between adjacent p-type base layers 4 across the same mesa region 18 in the longitudinal direction of the gate trench 7 depends on the characteristics of the IGBT and the design design rules, but is, for example, about 10 ⁇ m to 50 ⁇ m. May be.
- the unit length in the periodic structure of the p-type base layer 4 and the gate trench 7 in the direction perpendicular to the longitudinal direction of the gate trench 7 also depends on the characteristics of the IGBT and the design design rule, but it is 1 ⁇ m or more and 10 ⁇ m, for example. It may be about the following.
- an n-type emitter layer 5 in contact with the gate trench 7 is formed in the same manner as the p-type base layer 4.
- An end portion of the n-type emitter layer 5 along the longitudinal direction of the gate trench 7 is disposed so as to be inside the p-type base layer 4. That is, the length of the n-type emitter layer 5 in the longitudinal direction of the gate trench 7 is shorter than the length of the p-type base layer 4 in the longitudinal direction of the gate trench 7.
- the n-type emitter layers 5 adjacent to each other in the direction perpendicular to the longitudinal direction of the gate trench 7 and in contact with the gate trench 7 are p-type so as to connect each other.
- the base layer 4 may have a planar shape connected to the upper surface side in a ladder shape.
- the n-type emitter layer 5 may have an H-shaped planar shape as shown in FIG.
- An interlayer insulating film (not shown) is provided on the upper surface of the p-type base layer 4.
- an opening (contact opening) 14 for allowing the p-type base layer 4 and the n-type emitter layer 5 to contact an emitter electrode (not shown) is formed inside the p-type base layer 4.
- the contact opening 14 exposes part of the p-type base layer 4 and the n-type emitter layer 5.
- stripe-like dummy trenches 8 are formed in parallel to the longitudinal direction of the gate trenches 7. Yes.
- a gate oxide film 10 is formed on the inner side wall of the dummy trench 8 similarly to the inner side of the gate trench 7, and a conductive dummy polysilicon 11 b is formed on the inner side of the gate oxide film 10.
- the dummy trench 8 and the gate trench 7 are separated from each other. Therefore, the dummy polysilicon 11b formed inside the dummy trench 8 is not connected to the gate polysilicon 11a formed inside the gate trench 7. , Separated.
- the separation means that, for example, the regions are electrically insulated from each other, or the distance between the regions is separated.
- n-type field stop layer 2 is formed adjacent to the other main surface (corresponding to a lower surface on the paper surface, hereinafter simply referred to as a lower surface) of the substrate to be the n-type drift layer 1, and the n-type field stop layer
- a p-type collector layer 3 is formed adjacent to the lower surface of 2.
- a collector electrode (not shown) is formed on the lower surface of the p-type collector layer 3.
- FIG. 2 is a cross-sectional view taken along section line A-A ′ of FIG.
- a cross-sectional view refers to a cross-sectional view taken along a cutting line in a perspective view.
- the emitter electrode 12, not shown in FIG. 1, an interlayer insulating film 9 that insulates the emitter electrode 12 from the gate polysilicon 11a inside the gate trench 7 and a collector electrode 13 are also shown (hereinafter referred to as “the collector electrode 13”).
- the collector electrode 13 the same applies to FIG. 5 for FIG. 4, FIG. 24 for FIG. 23, and FIG. 27 for FIG.
- the dummy polysilicon 11 b formed inside the dummy trench 8 may be connected to the emitter electrode 12.
- the dummy polysilicon 11b may be exposed in the contact opening 14 as shown in FIG. Other connection methods will be described later.
- a feature of the first embodiment is that a dummy trench 8 different from the gate trench 7 is formed in the mesa region 18 sandwiched between the gate trench 7 and the p-type base layer 4.
- a voltage higher than a threshold value is applied to the gate electrode 15 having a general MOS type trench gate structure, an electron inversion layer (channel) is formed on the adjacent surface of the p type base layer 4 in contact with the side wall of the gate trench 7. ) Is formed.
- a dummy trench 8 as a second trench is arranged in the vicinity of the mesa region 18 adjacent to the side wall on the opposite side across the gate trench 7 with respect to the side wall of the gate trench 7 where the channel is formed. Yes.
- the n-type drift layer 1 and the p-type base layer 4 are applied.
- a depletion layer spreads from the pn junction and the sidewall of the gate trench 7.
- FIG. 33 is a cross-sectional view taken along section line AA-AA ′ of FIG.
- the depletion layer end 16 is greatly curved as shown in FIG.
- the collector-gate capacitance Cgc that is, the mirror capacitance (hereinafter referred to as mirror capacitance Cgc) depends on the area of the equipotential surface
- the mirror capacitance Cgc increases by the amount of curvature of the equipotential surface.
- the provision of the dummy trench 8 in the mesa region 18 results in a wider depletion layer than the IGBT shown in FIGS. 32 and 33 (hereinafter referred to as a conventional example).
- the area is running low.
- the depletion layer is pinched off at a voltage lower than that of the conventional example (a combination of depletion layers spreading from different directions). Therefore, the area of the equipotential surface is also reduced, and the mirror capacitance Cgc is reduced. Further, the switching speed or switching loss can be reduced by reducing the mirror capacitance.
- a conductor is embedded inside the gate oxide film 10 formed on the inner side wall of the dummy trench 8.
- a depletion layer spreads in the n-type drift layer 1.
- a conductor here, dummy polysilicon 11 b
- a depletion layer spreads from the side wall of the dummy trench 8 as in the gate trench 7.
- equipotential surfaces are distributed in parallel to the dummy trenches 8. Therefore, the depletion layer extending from the gate trench 7 and the dummy trench 8 is pinched off at a smaller applied voltage, and the area of the equipotential surface is reduced. With the above mechanism, the mirror capacitance Cgc is reduced.
- the conductor (dummy polysilicon 11b) embedded in the dummy trench 8 it is more preferable to connect the conductor (dummy polysilicon 11b) embedded in the dummy trench 8 to the emitter electrode 12.
- the reason is as follows.
- the dummy polysilicon 11b is not connected to the emitter electrode 12, when a voltage is applied to the collector electrode 13, a potential difference is generated between the dummy trench 8 and the emitter electrode 12, and an equipotential surface is formed.
- an interlayer insulating film 9 is formed between the dummy trench 8 and the emitter electrode 12, and in many cases, the interlayer insulating film 9 is made of a silicon oxide film. Since the relative dielectric constant of the silicon oxide film is about 3.9, which is about 1/3 that of silicon (11.9), the equipotential surface is concentrated in the interlayer insulating film 9. Therefore, in the case of the conventional IGBT, the curvature of the equipotential surface is promoted by the interlayer insulating film 9, and the area of the equipotential
- the curvature of the equipotential surface is considerably relieved. Furthermore, it is preferable to connect a conductor (dummy polysilicon 11 b) embedded in the dummy trench 8 to the emitter electrode 12. The reason is that no potential difference occurs in the interlayer insulating film 9 between the dummy trench 8 and the emitter electrode 12, and the equipotential surface hardly enters the interlayer insulating film 9. As a result, as shown in FIG. 2, the depletion layer end 16 is pinched off with a sufficiently small applied voltage, so that the equipotential surface is not curved and is distributed almost planarly at the bottom of the gate trench 7 and the dummy trench 8. become.
- the mirror capacitance Cgc is further reduced. Further, the potential of the dummy polysilicon 11b is always the same as that of the emitter electrode 12, and the potential of the dummy polysilicon 11b is stabilized even when the internal state is changed, such as when it is turned off or turned on. become.
- the contact opening 14 of the interlayer insulating film 9 (FIG. 2) is formed in the longitudinal direction of the dummy trench 8.
- the end of the dummy polysilicon 11b in the longitudinal direction is exposed.
- the dummy polysilicon 11b and the emitter electrode 12 (FIG. 2) are connected at the exposed portion.
- the dummy polysilicon 11b and the emitter electrode 12 (FIG. 2) can be easily set to the same potential without adding a special film (conductive film, insulating film) or a photolithography process (mask). Since it is possible, it is more preferable.
- the distance L gd between the gate trench 7 and the dummy trench 8 is the width of the depletion layer extending from the p-type base layer 4 in a thermal equilibrium state in the direction perpendicular to the main surface of the substrate (hereinafter referred to as “the distance L gd”).
- the width is preferably equal to or less than W bi .
- a depletion layer has already spread in a thermal equilibrium state from the equilibrium condition of carrier drift current and diffusion current. In the case of the IGBT structure of the present invention, this pn junction corresponds to the pn junction 19 in the p-type base layer 4 and the n-type drift layer 1.
- the depletion layer in the thermal equilibrium state is referred to as a built-in depletion layer.
- Most of the built-in depletion layer extends toward the n-type drift layer 1 having a lower impurity concentration than the p-type base layer 4. Therefore, a depletion layer also spreads on the side wall of the gate trench 7 near the p-type base layer 4. Since the depletion layer also extends from the side wall of the gate trench 7 opposite to the side wall adjacent to the p-type base layer 4, between the dummy trenches 8 formed between these gate trenches 7. However, the built-in depletion layer spreads slightly.
- the mirror capacitance can show a small value corresponding to the capacitance of the built-in depletion layer.
- the potential of the mesa region 18 between the dummy trench 8 and the gate trench 7 increases rapidly, and the turn-on di / dt increases sharply. As described above, this phenomenon cannot be controlled by adjusting the gate resistance.
- the mesa region 18 between the dummy trench 8 and the gate trench 7 is connected to the emitter electrode. This reduces the IE effect as a reaction (compensation) for restoring gate controllability.
- the dummy trench 8 has an effect of blocking. Therefore, even if the mesa region 18 between the dummy trench 8 and the gate trench 7 is intentionally connected to the emitter electrode 12 through the p-type base layer 4, holes are rather accumulated in the vicinity of the p-type base layer 4. Therefore, the IE effect is enhanced as compared with the conventional IGBT structure shown in FIG.
- the above effect is that the mesa region 18 between the dummy trench 8 and the gate trench 7 in the mesa region 18 sandwiched between the p-type base layers 4 that are dispersedly arranged is connected to the emitter electrode 12 via the p-type base layer 4. This is an effect obtained for the first time by the configuration connected to Therefore, this effect cannot be expected from any of the conventional IGBT having a structure in which the floating p layer 30 and the dummy trench 8 shown in FIG. 31 are combined and the IGBT having the structure shown in FIG.
- an oxide film is formed by, for example, thermal oxidation, and a resist mask having openings for forming the gate trench 7 and the dummy trench 8 is formed on the upper surface of the substrate to be the n-type drift layer 1 by photolithography.
- the oxide film is etched to form an oxide film mask for trench etching.
- trench etching is performed by anisotropic etching to form a gate trench 7 and a dummy trench 8 on the upper surface of the substrate.
- the oxide film mask is removed by wet etching or the like.
- a gate oxide film 10 is formed inside the gate trench 7 and the dummy trench 8 by thermal oxidation.
- polycrystalline silicon (polysilicon) doped with phosphorus or the like is deposited inside the gate trench 7 and the dummy trench 8 by chemical vapor deposition (CVD) or the like.
- CVD chemical vapor deposition
- a resist mask in which the formation region of the p-type base layer 4 is opened is formed on the upper surface of the substrate by photolithography.
- boron is ion-implanted into the upper surface of the substrate using the resist mask as a mask.
- the p-type base layer 4 is selectively formed on the upper surface of the substrate.
- the resist mask is removed.
- impurities (boron) forming the p-type base layer 4 are diffused by heat treatment.
- the gate trench 7 since the gate trench 7 has already been formed, the diffusion of boron in the direction in which the gate oxide film 10 crosses the gate trench 7 is suppressed. Accordingly, the lateral diffusion of the p-type base layer 4 is performed only in the direction parallel to the gate trench 7 (longitudinal direction).
- the interval between the p-type base layers 4 in the longitudinal direction of the gate trench 7 is made long enough to keep the mesa region 18 in which the dummy trenches 8 are formed in the n-type.
- a resist mask having an opening for forming the n-type emitter layer 5 is formed on the upper surface of the substrate by photolithography.
- the resist mask for example, arsenic or the like is ion-implanted into the upper surface of the substrate and annealed to selectively form the n-type emitter layer 5 on the surface layer of the p-type base layer 4.
- a silicon oxide film to be the interlayer insulating film 9 is deposited by a known CVD method or the like.
- a resist mask is formed on the surface of the interlayer insulating film 9 by photolithography so that the contact opening 14 forming region is opened.
- contact openings 14 are formed in the interlayer insulating film 9 by etching using the resist mask as a mask.
- a metal film such as aluminum is deposited on the upper surface side of the substrate so as to fill the contact opening 14. Thereby, the emitter electrode 12 in contact with the p-type base layer 4 and the n-type emitter layer 5 is formed.
- a protective film such as polyimide is deposited to cover the emitter electrode 12.
- a pad portion is opened in the protective film by photolithography. This pad opening is an opening region for connecting an emitter electrode and an aluminum wire or a lead frame when a chip is packaged in an IGBT module or a mold in a so-called post-process after chip dicing.
- the substrate is thinned by grinding or polishing from the back side of the substrate by back grinding or wet etching.
- ions serving as donors such as phosphorus and protons are implanted into the back surface of the substrate, and then ions serving as acceptors such as boron are implanted from the back surface.
- the acceleration energy of the first donor impurity (proton, phosphorus, etc.) implantation performed on the back surface of the substrate is larger than the acceleration energy of the subsequent acceptor impurity (boron, aluminum, etc.) implantation.
- the order of donor impurities and acceptor impurities when ions are implanted into the back surface of the substrate may be reversed.
- laser annealing for example, well-known YAG2 ⁇
- the n-type field stop layer 2 is formed by the formation of hydrogen-related donors by protons
- the p-type collector layer 3 is formed by the activation of boron.
- Example 1 Next, a specific method for manufacturing a semiconductor device will be described with reference to the following examples.
- a 600V class IGBT is realized (see FIGS. 1 and 2).
- a silicon wafer (substrate) having a specific resistance of, for example, about 20 ⁇ cm to about 35 ⁇ cm is prepared.
- the specific resistance is about 40 ⁇ cm to 60 ⁇ cm in the 1200 V class, about 60 ⁇ cm to 90 ⁇ cm in the 1700 V class, and about 100 ⁇ cm to 250 ⁇ cm in the 3500 V class.
- the higher the breakdown voltage the higher the specific resistance of the wafer, so that the built-in depletion layer becomes wider, and as a result, the effect of reducing the mirror capacitance becomes stronger.
- Vbi When the specific resistance is 50 ⁇ cm, Vbi is 0.69 V and Wbi is 3.2 ⁇ m. When the specific resistance is 75 ⁇ cm, Vbi is 0.68 V and Wbi is 3.8 ⁇ m. When the specific resistance is 175 ⁇ cm, Vbi is 0.66 V and Wbi is 5.8 ⁇ m.
- trench etching with a depth of about 5 ⁇ m is performed on the wafer surface (substrate upper surface) using anisotropic etching to form a trench.
- the gate trench 7 and the dummy trench 8 are laid out using the same mask, they can be formed simultaneously.
- the width in the direction perpendicular to the longitudinal direction of the gate trench 7 and the dummy trench 8 in the layout mask was 1 ⁇ m.
- the distance L gd between the gate trench 7 and the dummy trench 8 was 2 ⁇ m.
- the distance L gd between the gate trench 7 and the dummy trench 8 is smaller than the built-in depletion layer width Wbi. Further, through the subsequent processes, the width in the direction perpendicular to the longitudinal direction of the gate trench 7 and the dummy trench 8 is expanded by about 10% from 1 ⁇ m due to thermal oxidation or the like. As a result, the distance L gd between the gate trench 7 and the dummy trench 8 is also about 20% narrower than 2 ⁇ m.
- a gate oxide film 10 having a thickness of about 100 nm is formed inside the gate trench 7 and the dummy trench 8 by thermal oxidation.
- polycrystalline silicon (polysilicon) doped with phosphorus or the like is deposited by chemical vapor deposition (CVD) or the like.
- CVD chemical vapor deposition
- the gate polysilicon 11a and the dummy polysilicon 11b are filled in the gate trench 7 and the dummy trench 8, respectively.
- the gate polysilicon 11a and the dummy polysilicon 11b are doped with dopants to such an extent that they exhibit conductivity.
- the sheet resistance of the polysilicon is about 1 ⁇ / ⁇ or more and 50 ⁇ / ⁇ (ohm / square) or less. That is, the material embedded in the gate trench 7 and the dummy trench 8 only needs to show conductivity, and may be a high melting point metal such as platinum.
- the above-described conductive polysilicon is preferable.
- boron is ion-implanted into the wafer surface to selectively form the p-type base layer 4 using a photoresist or the like.
- drive-in diffusion is performed for several hours at a high temperature of about 1100 ° C., for example.
- the length of the p-type base layer 4 in the longitudinal direction of the gate trench 7 was 8 ⁇ m.
- the interval between the p-type base layers 4 adjacent to each other with the mesa region 18 in the longitudinal direction of the gate trench 7 is set to 30 ⁇ m.
- the unit length in the periodic structure of the p-type base layer 4 and the gate trench 7 was 5 ⁇ m.
- the n-type emitter layer 5 is formed by removing the photoresist once, ion-implanting arsenic or the like again using a photoresist or the like, and annealing at about 1000 ° C.
- a silicon oxide film having a thickness of about 1 ⁇ m is deposited by a well-known CVD method or the like to form an interlayer insulating film 9.
- a contact opening 14 is formed using a photoresist pattern or the like, and then a metal film such as aluminum is deposited to form the emitter electrode 12.
- a protective film such as polyimide is formed, and a pad portion for connecting the emitter electrode and the aluminum wire or the lead frame is opened using a photoresist pattern or the like.
- the back surface of the silicon wafer is ground and polished by back grinding, wet etching, or the like, so that the total thickness of the silicon wafer is reduced to about 50 ⁇ m to 60 ⁇ m.
- the total thickness of the wafer after grinding varies depending on the pressure resistance class and the like, and is set as appropriate.
- protons are injected from the back surface in the range of acceleration energy of 1 MeV to 8 MeV and dose amount of about 1.0 ⁇ 10 14 / cm 2 to 1.0 ⁇ 10 15 / cm 2 , and then boron is similarly used.
- the acceleration energy is 10 keV or more and 100 keV or less, and the dose amount is 1.0 ⁇ 10 13 / cm 2 or more and 1.0 ⁇ 10 15 / cm 2 or less.
- laser annealing for example, the well-known YAG2 ⁇
- a single or double pulse at an energy density of 1 J / cm 2 on the back surface of the wafer.
- Example 2 The effect of the first embodiment will be verified.
- description will be made while comparing with the conventional IGBT shown in FIG.
- a first example an IGBT in which one dummy trench 8 was provided between adjacent gate trenches 7 was manufactured.
- the manufacturing method and design conditions of the IGBT are the same as in the first embodiment.
- an IGBT was prepared in which no dummy trench 8 was provided between adjacent gate trenches 7 (see the conventional example, FIG. 32).
- the conventional example was formed with the same parameters as in Example 1, and the length of the p-type base layer 4 in the longitudinal direction of the gate trench 7 was 8 ⁇ m, the same as in Example 1.
- the distance between adjacent p-type base layers 4 in the longitudinal direction of the gate trench 7 is the same as that in the first embodiment.
- the unit period in the periodic structure of the p-type base layer 4 and the gate trench 7 in the direction perpendicular to the longitudinal direction of the gate trench 7 is the same as that in the first embodiment.
- FIG. 3 is a characteristic diagram showing the electrical characteristics of the capacitance and the collector-emitter voltage according to the first example.
- FIG. 3 is a graph showing the dependence (CV characteristics) of the input capacitance Cies and the feedback capacitance Cres on the voltage applied between the collector and emitter electrodes in the semiconductor device of Example 1.
- Cge is a gate-emitter capacitance.
- Cce is a collector-emitter capacitance.
- an impedance analyzer HP-4192A, manufactured by Hewlett-Packard Co. was used, and the measurement AC frequency was set to 1 MHz.
- the input capacitance Cies is measured by connecting an external capacitor in parallel between the collector and emitter (hereinafter also referred to as CE) to cancel the CE capacitance Cce.
- the output capacitance Coes is measured by connecting an external capacitor in parallel between the gate and emitter (between GE) to cancel the GE capacitance Cge.
- the electrostatic capacitance Cx is measured by connecting an external capacitor in parallel between the gate and the collector to cancel the GC capacitance Cgc.
- the dummy trench 8 is provided between the adjacent gate trenches 7 (mesa region 18), so that the depletion layer extending from the gate trench 7 -Even when the applied voltage between the emitters is low, the pinch-off occurs, and the area of the equipotential surface decreases.
- a semiconductor device having a small mirror capacitance Cgc can be obtained.
- the switching speed or switching loss can be reduced by reducing the mirror capacitance. Thereby, a semiconductor device with small switching loss can be obtained.
- FIG. 4 is a perspective view illustrating a main part of the semiconductor device according to the second embodiment.
- the difference between the second embodiment and the first embodiment is the number of dummy trenches 8 in the mesa region 18.
- two dummy trenches 8 are provided between adjacent gate trenches 7 in a striped planar layout.
- the longitudinal ends of the two dummy trenches 8 in each mesa region 18 are connected to each other.
- FIG. 5 is a cross-sectional view taken along section line B-B ′ of FIG.
- the dummy polysilicon 11 b formed inside the dummy trench 8 is connected to the emitter electrode 12.
- the end of the dummy polysilicon 11b may be exposed in the contact opening 14 as shown in FIG.
- the distance between the gate trench 7 and the adjacent dummy trench 8 or the distance between the adjacent dummy trenches 8 can be reduced.
- the depletion layer extending from the dummy trench 8 adjacent to the gate trench 7 is pinched off at a lower applied voltage.
- the equipotential surface at the bottom of the gate trench 7 or the dummy trench 8 becomes more planar.
- the area of the equipotential surface becomes particularly small at a low applied voltage.
- the mirror capacitance can be reduced, the electric field strength at the bottom of the trench can be relaxed, and the breakdown voltage can be prevented from lowering.
- the potential of the dummy polysilicon 11b formed in each dummy trench 8 is the same potential.
- the dummy polysilicon 11b is also stable against fluctuations in the potential in the chip that occur when the IGBT is turned on or off. You can follow.
- the dummy trenches 8 are connected to each other at the ends in the longitudinal direction of the dummy trenches 8 as shown in FIG. It is preferable to connect the dummy polysilicon 11b inside the trench 8.
- the radius of curvature of the end of the dummy trench 8 can be increased. Therefore, it is possible to prevent electric field concentration at the end of the dummy trench 8 when a high voltage is applied between the CEs to expand the depletion layer.
- the end portions of the dummy polysilicons 11b are exposed in the contact openings 14. Then, the dummy polysilicon 11b is connected to the metal forming the emitter electrode at this exposed portion. As a result, the potential of the dummy polysilicon 11b can be made the same as that of the emitter electrode without adding a complicated mask layout, extra electrode film formation, or photolithography process.
- the conductor (dummy polysilicon 11b) embedded in the dummy trench 8 to the emitter electrode 12 as in the first embodiment.
- the reason is the same as in the first embodiment.
- the mirror capacity can be reduced as in the first embodiment.
- the equipotential surface is more evenly distributed and the effect of reducing the mirror capacitance can be enhanced.
- the potential of the dummy polysilicon 11b is always the same as that of the emitter electrode 12. As a result, the potential of the dummy polysilicon 11b is stabilized.
- the proportion of the dummy polysilicon 11b having the same potential as the emitter electrode 12 in the mesa region 18 increases.
- the potential of the mesa region 18 can be further stabilized even during switching.
- FIG. 29 is a cross-sectional view showing a semiconductor device of a comparative example.
- the mirror capacitance Cgc increases rather than the conventional example, which is not preferable.
- FIG. 6 is a plan view showing the semiconductor device of FIG.
- the p-type base layer 4 is preferably arranged in a checkered pattern.
- Two dummy trenches 8 are formed between adjacent p-type base layers 4 in the mesa region 18.
- a p-type contact layer 6 having an impurity concentration higher than that of the p-type base layer 4 is formed inside the p-type base layer 4 in FIG. 6 in order to suppress a known collector current latch-up.
- latch-up is a phenomenon in which a parasitic thyristor built in the IGBT is turned on, and control such as turn-off by the gate electrode 15 becomes impossible.
- the formation of the p-type contact layer 6 is a well-known technique, and although the description thereof is omitted in other embodiments of the present invention, the p-type contact layer 6 may be formed as in the second embodiment. Of course.
- FIG. 7 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the third embodiment.
- FIG. 7 is a graph comparing the dependence (CV characteristics) of the collector-emitter voltage V CE on the input capacitance Cies and the feedback capacitance Cres between the IGBT of the second embodiment and the conventional IGBT.
- a second example an IGBT having two dummy trenches 8 provided between adjacent gate trenches 7 was manufactured (hereinafter referred to as a second example).
- Other design conditions of the second embodiment are the same as those of the first embodiment.
- a conventional IGBT was fabricated in the same manner as in Example 2.
- the electrostatic capacitance Cx and the voltage VCE between CE were measured, and the electrical property of IGBT was verified.
- the measurement method and calculation method are the same as in the second embodiment.
- the feedback capacitance Cres (mirror capacitance) is reduced in the third embodiment as well as the second embodiment in comparison with the conventional example.
- the third embodiment having two dummy trenches has a smaller mirror capacity and can be reduced to about 30% of the conventional example at the maximum.
- FIG. 8 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the fourth example.
- FIG. 8 is a diagram comparing current-voltage (IV) characteristics when the IGBTs of the first and second embodiments and the conventional IGBT are on. It should be noted that the circles on the curves are merely shown so that it can be understood which IGBT each curve corresponds to.
- the rated current density is defined as 225 A / cm 2 and is indicated by a solid line parallel to the horizontal axis of FIG.
- Example 2 similarly to Example 2, a first example and a comparative example were produced. Further, as in Example 3, a second example was produced. Then, the collector current I C and the CE voltage V CE were measured for each of the first and second examples and the comparative example, and the electrical characteristics of the IGBT were verified. The measurement method is the same as in Example 2.
- the on-voltage at the rated current density tends to decrease compared to the conventional example.
- the on-state voltage is about 0.1 V at the rated current. Voltage reduction was confirmed.
- the on-voltage is a voltage drop between CEs required when a current having a rated current or a rated current density is passed.
- the reduction of the on-voltage in the second embodiment is due to the enhancement of the IE effect by the dummy trench 8. That is, since the number of dummy trenches 8 is two, the distance from the gate trench 7 in the mesa region 18 or the distance between the adjacent dummy trenches 8 is reduced. As a result, the width of the effective mesa region 18 is narrowed, so that the IE effect is improved.
- FIG. 9 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the fifth example.
- FIG. 9 compares the correlation between the saturation current value when the collector current I C is saturated and the ON voltage shown in FIG. 8 in the ON state of each of the IGBTs of the first and second embodiments and the conventional IGBT. It is a graph.
- the saturation current value means that when the gate voltage V GE is constant and the collector current I C is flown until the ON voltage becomes sufficiently large to be 100 V or more, the collector current I C is obtained due to the current saturation effect in the well-known MOS gate. It is the current value when C is saturated to a certain value.
- Example 2 a first example and a comparative example were produced. Further, as in Example 3, a second example was produced. Then, for each of the first and second examples and the comparative example, the ON voltage and the collector saturation current were measured, and the electrical characteristics of the IGBT were verified.
- the on-state voltage and the saturation current at the rated current density For example, when the channel density per unit area (or the number density in the chip surface of a unit cell having a MOS gate) is increased, the on-voltage is lowered, but the saturation current value is increased. As will be described later, this saturation current value is strongly related to the short circuit tolerance of the IGBT, and the smaller the saturation current value, the higher the short circuit tolerance.
- the on-state voltage can be reduced by about 0.03 V on average compared to the conventional example.
- the on-voltage can be reduced by 0.1 V while maintaining the same saturation current as in the first embodiment or the conventional example.
- the structure of the present invention first and second embodiments
- FIG. 10 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the sixth example.
- FIG. 10 is a diagram comparing turn-off waveforms for the IGBTs of the second embodiment and the conventional example.
- a second example was produced. Similar to Example 2, a comparative example was prepared. Then, for each of the second example and the comparative example, the collector current I C , the CE voltage V CE and the gate voltage V GE were measured using a switching evaluation circuit described later, and the electrical characteristics of the IGBT were verified. Next, the switching evaluation circuit will be described.
- FIG. 30 is a switching evaluation circuit diagram of the semiconductor device according to the embodiment.
- FIG. 30 shows a switching test circuit for turn-off or turn-on described later.
- the circuit configuration shown in FIG. 30 is a single-phase inductive load circuit.
- a capacitor 21 is connected in parallel to the DC power supply 20, and an IGBT 24 and a free-wheeling diode (FWD) 25 connected in series on the high voltage side of the IGBT 24 are connected in parallel to the capacitor 21.
- An inductive load 26 is connected in parallel with the FWD 25.
- the inductive load 26 corresponds to a three-phase AC motor in an actual machine such as an inverter, and is typically about 0.1 mH to 1 mH.
- the IGBT 24 is controlled to be turned on and off by inputting a pulse voltage of ⁇ 15 V to the gate electrode from the gate driving power source 22 through the gate resistor 23.
- the circuit itself has a stray inductance 27 of about 10 nH to 300 nH, but in the circuit diagram, it is shown at the top of the circuit for convenience.
- the collector current for turning off (hereinafter referred to as the turn-off current) is 30 A (rated current density is equivalent to 200 A / cm 2 ), the gate resistance of the turn-off is 75 ⁇ , the gate voltage is ⁇ 15 V, and the measurement temperature is 125 ° C.
- the power supply voltage V CC was set to 300 V, which is a half value of the rated voltage.
- the second example shows a delay time (a constant value after the gate voltage V GE starts decreasing after the gate voltage V GE starts to decrease) in spite of driving with the same gate resistance.
- 10 is a period in which the constant value is shown (the period from about 0.7 ⁇ s to 0.9 ⁇ s in the waveform in FIG. 10) is shortened by about 100 ns, and the CE voltage V CE is It can be seen that the rate of change dV / dt at the time of rising is also high. As a result, the turn-off loss is reduced by about 10%.
- the delay time is shortened because the mirror capacity is reduced. Furthermore, a decrease in surge voltage (maximum value of V CE ) can also be confirmed.
- FIG. 11 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to the seventh embodiment.
- FIG. 11 is a diagram showing the relationship between the turn-off current and the turn-off loss under the same switching conditions as the turn-off waveform shown in FIG. 10 in each of the IGBTs of Embodiments 1 and 2 and the conventional example.
- Example 2 similarly to Example 2, a first example and a comparative example were produced. Further, as in Example 3, a second example was produced. Then, turn-off loss and collector current I C were measured for each of the first and second examples and the comparative example, and the electrical characteristics of the IGBT were verified.
- the turn-off loss occurs during the period from when the OFF signal is input to the gate and the gate voltage V GE starts decreasing until the collector current I C becomes 0 (this is referred to as one pulse).
- CE collector current value obtained by integrating the product (power loss) and I C (energy loss).
- the turn-off loss is approximately linearly proportional to the turn-off current.
- both the first and second embodiments can achieve a smaller turn-off loss than the conventional example, particularly at the rated current or higher current.
- the reason for this effect is that by providing the dummy trench of the present invention, the mirror capacitance Cgc is reduced, and as a result, the delay time at turn-off determined by the mirror capacitance is reduced. That is, as a result of the decrease in the delay time, the turn-off time is shortened and the turn-off loss is reduced.
- FIG. 12 is a characteristic diagram illustrating electrical characteristics of the semiconductor device according to Example 8. As illustrated in FIG. FIG. 12 is a graph showing the relationship between the on-voltage and the turn-off loss in each of the IGBTs of the first and second embodiments and the conventional example.
- Example 2 similarly to Example 2, a first example and a comparative example were produced. Further, as in Example 3, a second example was produced. Then, turn-off loss and on-voltage were measured for each of the first and second examples and the comparative example, and the electrical characteristics of the IGBT were verified.
- on-state voltage there is a trade-off relationship between on-state voltage and turn-off loss. For example, if the total impurity amount in the p-type collector layer is increased to increase the hole injection efficiency, the on-voltage decreases, but the concentration of injected holes increases, resulting in a longer turn-off time, resulting in an increase in turn-off loss. To do.
- the turn-off loss is reduced by 10% or more in the first embodiment (dummy polysilicon is short-circuited with the emitter electrode) compared to the conventional example. It can be seen that the on-voltage is reduced by 0.10 V by converting the reduced turn-off loss into the on-voltage. Furthermore, in the second embodiment (similarly, the dummy polysilicon is short-circuited with the emitter electrode), an on-voltage reduction of 0.18 V was achieved. That is, the present invention has the effect of dramatically improving the trade-off between the on-voltage and the turn-off loss without having to compensate for the increase in saturation current as described above.
- the reason for this effect is that by providing the dummy trench of the present invention, the mirror capacitance Cgc is reduced, and as a result, the delay time at turn-off determined by the mirror capacitance is reduced. As a result, the turn-off time is shortened and the turn-off is reduced. This is because the loss is reduced.
- FIG. 13 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Working Example 9.
- FIG. 13 is a graph showing the relationship between the gate resistance at turn-off and the surge voltage at turn-off in each of the IGBTs of the first and second embodiments and the conventional example.
- a first example and a comparative example were produced.
- a second example was produced.
- the turn-off surge voltage and the gate resistance were measured, and the electrical characteristics of the IGBT were verified.
- Example 9 the turn-off surge voltage in the second example was smaller than that in the conventional example.
- FIG. 13 shows that the effect (the difference in surge voltage between the first or second embodiment and the conventional example) is large when the gate resistance is 50 ⁇ . That is, the maximum value of the surge voltage in the first and second embodiments is shifted to the higher gate resistance side, and the absolute value is also lowered. This is because the provision of the dummy trench 8 reduces the mirror capacitance, and the time constant (Cgc ⁇ Rg, where Rg is a gate resistance) for reducing the gate voltage V GE at turn-off is reduced. This is considered to be equivalent to what has been done.
- FIG. 14 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Working Example 10.
- FIG. 14 is a diagram comparing turn-on waveforms in the IGBTs of the first and second embodiments and the conventional example.
- a first example and a comparative example were produced.
- a second example was produced.
- the collector current I C , the CE voltage V CE and the gate voltage V GE were measured for each of the first and second examples and the comparative example, and the electrical characteristics of the IGBT were verified.
- the measurement method is the same as in Example 6.
- the gate voltage V GE waveform when the gate voltage V GE is increased from -15V, time at 0.8 ⁇ s the conventional example, the gate voltage V GE is increasing rapidly.
- the gate voltage V GE increases smoothly and no rapid change is observed.
- the magnitude (absolute value) of the voltage change rate dV / dt is also higher in the first and second embodiments. It can be seen that it is larger and rapidly decreasing.
- FIG. 15 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Example 11.
- FIG. 15 is a diagram comparing waveforms at the time of a short circuit in each IGBT of the conventional example (FIG. 15A) and the second embodiment (FIG. 15B).
- Example 3 a second example was produced. Similar to Example 2, a comparative example was prepared. For each of the second example and the comparative example, the collector current I C , the CE voltage V CE and the gate voltage V GE were measured, and the electrical characteristics of the IGBT were verified. The measurement method is the same as in Example 6.
- the turn-on di / dt of the second embodiment is smaller than that of the conventional example.
- the maximum value I max of the collector current is lowered although the static saturation current is substantially equal as shown in FIG. This is because the formation of the dummy trench 8 increases the input capacitance Cies, and the mirror capacitance Cres is small, so that an increase in gate voltage (a slight increase) due to the displacement current through this is suppressed. It is thought that.
- the reduction of the mirror capacitance reduces the maximum collector current value I max , which is a favorable effect from the viewpoint of reducing the collector maximum current generated during a short circuit and improving the short-circuit tolerance.
- FIG. 16 is a characteristic diagram showing electrical characteristics of the semiconductor device according to Working Example 12.
- FIG. 16 is a graph comparing the gate resistance at turn-off and the turn-off spike voltage (maximum value of surge voltage between CEs) at the time of short-circuit in each of the first and second embodiments of the present invention and the conventional IGBT. is there.
- Example 2 a first example and a comparative example were produced.
- Example 3 a second example was produced.
- the turn-off spike voltage and the gate resistance at the time of a short circuit were measured, and the electrical characteristics of the IGBT were verified.
- the same effect as that of the first embodiment can be obtained. Further, by providing a plurality of dummy trenches 8, the distance between the dummy trench 8 and the gate trench 7 or the distance between the adjacent dummy trenches 8 is reduced. As a result, the width of the effective mesa region 18 is narrowed, so that the IE effect is improved. Thereby, a semiconductor device with a low on-voltage can be obtained.
- FIG. 17 is a cross-sectional view illustrating a main part of the semiconductor device according to the third embodiment.
- the difference between the third embodiment and the first embodiment is that the width of the dummy trench 8 in the mesa region 18 is wide.
- the contact area between the emitter electrode 12 and the dummy polysilicon 11b is increased, so that the contact resistance between the emitter electrode 12 and the dummy polysilicon 11b can be made sufficiently small. It becomes possible.
- FIG. 18 is a plan view illustrating the main part of the semiconductor device according to the fourth embodiment.
- the difference between the fourth embodiment and the second embodiment is as follows.
- the adjacent two dummy trenches 8 are connected to each other not only at the end portion in the longitudinal direction but also at the intermediate portion 28.
- the dummy polysilicon 11 b is also connected at the intermediate portion 28.
- the dummy polysilicon 11b is polycrystalline silicon doped with a dopant such as phosphorus at a high concentration, it exhibits a sufficiently low resistance as described above, but exhibits a higher resistance value than a metal such as aluminum. Therefore, when the CE voltage changes suddenly during switching (for example, the instantaneous voltage change rate is about 10000 V / ⁇ s), a time difference may occur in the potential change in the dummy polysilicon 11b.
- FIG. 19 is a cross-sectional view illustrating a main part of the semiconductor device according to the fifth embodiment.
- FIG. 20 is a plan view showing a main part of the IGBT of FIG.
- the difference between the fifth embodiment and the second embodiment is that a dummy polysilicon 11b is formed up to the upper surfaces of two adjacent dummy trenches 8 and a bridge portion 29 is provided, so that the dummy poly is sandwiched between the mesa regions 18.
- the silicon 11b is connected to each other in a bridge shape.
- a polysilicon pad 17 (FIG. 20), which is an opening for making contact between the dummy polysilicon 11b and the emitter electrode 12, is provided on the upper surface of the bridge portion 29 of the dummy polysilicon 11b.
- the bridge portion 29 of the dummy polysilicon 11b and the polysilicon pad 17 preferably have the following planar shape.
- the width near the middle of the mesa region 18 in the longitudinal direction of the gate trench 7 is partially expanded, and a bridge portion 29 of dummy polysilicon 11b is provided near the middle.
- the polysilicon pad 17 is provided inside the bridge portion 29.
- FIG. 21 is a perspective view of a relevant part of the semiconductor device according to the sixth embodiment.
- the difference of the sixth embodiment from the first embodiment is that the contact opening 14 provided on the upper surface of the p-type base layer 4 is shortened in the length of the opening along the longitudinal direction of the gate trench 7. That is, the opening 14 does not cover the end of the dummy trench 8 in the longitudinal direction. That is, by preventing the dummy polysilicon 11b from coming into contact with the emitter electrode, the potential of the dummy polysilicon 11b is made floating. When the potential of the dummy polysilicon 11b is floated, the mirror capacitance is reduced to 75% of the conventional example, although not as much as when connected to the emitter electrode.
- the mirror capacity can be reduced to 66% of the conventional example.
- the potential of the dummy polysilicon 11b is floated, it is not necessary to form the contact opening 14 at the end of the dummy trench 8. Therefore, for example, etching damage at the time of contact opening of the interlayer insulating film 9 does not reach the gate oxide film 10 of the dummy polysilicon 11b. Therefore, the finished shape extending from the end in the longitudinal direction of the dummy trench 8 to the end of the contact opening 14 is very good.
- FIG. 22 is a cross-sectional view illustrating a main part of the semiconductor device according to the seventh embodiment.
- the difference between the seventh embodiment and the second embodiment is that the number of dummy trenches 8 in the mesa region 18 is further set to three. That is, the number of dummy trenches 8 in the mesa region 18 is not limited to three, and a plurality of dummy trenches 8 is also preferable.
- a plurality of potentials of the dummy polysilicon 11b may be set. For example, as shown in FIG. 22, the potential of the dummy polysilicon 11b of the middle dummy trench 8 among the three may be the same as that of the gate electrode 15. Alternatively, although not shown, if the dummy polysilicon 11b is connected to the emitter electrode 12 in all the dummy trenches 8, the mirror capacitance can be further reduced.
- FIG. 23 is a perspective view of a relevant part of the semiconductor device according to the eighth embodiment.
- FIG. 24 is a cross-sectional view taken along the section line CC ′ of FIG.
- the difference of the eighth embodiment from the second embodiment is that in the mesa region 18, the gate trench 7 and the dummy trench 8 are adjacent to each other or sufficiently close to each other.
- the dummy polysilicon 11b has the same potential as the emitter electrode.
- making the gate trench 7 and the dummy trench 8 sufficiently close means that the width of the mesa region 18 between the gate trench 7 and the dummy trench 8 is, for example, about the thickness of the gate oxide film 10 (for example, 0.1 ⁇ m). Means close to.
- the gap between the gate trench 7 and the dummy trench 8 may be narrowed by thermal oxidation pile-up and become thinner than the thickness of the thermal oxide film. .
- the pile-up means that when a silicon thermal oxide film having a certain thickness is formed by a known silicon thermal oxidation mechanism, about 44% of silicon is consumed and reduced. If the gate oxide film 10 of the gate trench 7 and the gate oxide film 10 of the dummy trench 8 are attached by pile-up, they are adjacent to each other. At this time, the gate polysilicon 11a and the dummy polysilicon 11b are not short-circuited. Thereby, the mirror capacity is further reduced. In other words, the equipotential surface in the mesa region 18 can pass only a small amount of voltage in the zero bias (thermal equilibrium state) or the CE voltage V CE of about 10V.
- FIG. 25 is a cross-sectional view illustrating a main part of the semiconductor device according to the ninth embodiment.
- the difference between the ninth embodiment and the eighth embodiment is that the two dummy trenches 8 are adjacent or sufficiently close to each other and are separated from the adjacent gate trenches 7. In this way, the risk of short-circuiting between the gate polysilicon 11a and the dummy polysilicon 11b as described above can be avoided, and the mirror capacitance can be reduced.
- the number of dummy trenches 8 is not limited to two and can be variously changed, and may be three or more. Further, it is more preferable to connect the dummy polysilicon 11b to the emitter electrode 12 because the mirror capacitance can be sufficiently reduced as described above.
- FIG. 26 is a perspective view of the main part of the semiconductor device according to the tenth embodiment.
- FIG. 27 is a cross-sectional view taken along a cutting line DD ′ in FIG.
- the features of the tenth embodiment are as follows. In the mesa region 18 sandwiched between the gate trenches 7, dummy trenches 8 are provided all between the p-type base layers 4 adjacent in the longitudinal direction of the gate trench 7. Adjacent gate trenches 7 or dummy trenches 8 are arranged so as to be in contact with each other or sufficiently close to each other. Other configurations are the same as those in the first embodiment.
- the mirror capacity can be made sufficiently small.
- the dummy polysilicon 11b is connected to the emitter electrode 12 and set to the same potential as the emitter electrode 12, the equipotential surface almost no longer exists in the mesa region 18, and the mirror capacitance is extremely small. Cgc IGBT is achieved, which is more preferable.
- FIG. 28 is a plan view of the main part of the semiconductor device according to the eleventh embodiment.
- a feature of the eleventh embodiment is that the arrangement of the p-type base layer 4 is arranged in a line in a direction perpendicular to the longitudinal direction of the gate trench 7 as shown in FIG. Other configurations are the same as those in the first embodiment. Even if the p-type base layer 4 is arranged in this way, it is possible to achieve an effect of reducing the mirror capacitance.
- the p-type base layer 4 when the p-type base layer 4 is distributed in a checkered pattern, two p-type base layers 4 adjacent to one mesa region 18 via the gate trench 7 sandwich the mesa region 18. . Therefore, the pinch-off effect of the depletion layer in the mesa region 18 is further enhanced. Furthermore, the current density distribution on the upper surface of the chip in the on state can be made uniform when the p-type base layer 4 is distributed in a checkered pattern as described above. Therefore, the p-type base layer 4 is preferably distributed in a checkered pattern.
- the present invention is not limited to the above-described embodiment, and the dimensions of various regions constituting the IGBT such as the length in the longitudinal direction of the gate trench and the dummy trench and the length in the direction perpendicular to the longitudinal direction can be appropriately changed. It is.
- the semiconductor device according to the present invention is useful for a power semiconductor device such as an insulated gate semiconductor device (IGBT) used in a power conversion device or the like.
- IGBT insulated gate semiconductor device
Abstract
Description
本発明の実施の形態1にかかる半導体装置について、図1を用いて説明する。図1は、実施の形態1にかかる半導体装置の要部を示す斜視図である。n型ドリフト層1となる基板の一方の主面(紙面では上方の面に相当、以下、単に上面とする)に、ストライプ状の平面形状を有するゲートトレンチ7が形成されている。ゲートトレンチ7の内壁にはゲート酸化膜10が形成され、さらにゲート酸化膜10の内側には導電性のゲートポリシリコン11aが形成されている。
次に、具体的な半導体装置の製造方法について、以下の実施例を例に説明する。実施の形態1に従い、600VクラスのIGBTを実現する(図1,2参照)。まず、比抵抗が例えば20Ωcm以上35Ωcm以下程度のシリコンウェハー(基板)を用意する。実施例1では、30Ωcmとした。ここで本発明の半導体装置は、その他の耐圧クラスでも適用できることは勿論である。例えば比抵抗は、1200Vクラスでは40Ωcm以上60Ωcm以下程度、1700Vクラスでは60Ωcm以上90Ωcm以下程度、3500Vクラスでは100Ωcm以上250Ωcm以下程度、それ以上の耐圧クラスもそれに応じて比抵抗を高くすればよい。特に高耐圧であるほど、ウェハーの比抵抗を高くする必要があるため、ビルトイン空乏層は一層広くなり、その結果ミラー容量低減効果は強くなる。
実施の形態1の効果について検証する。ここでは、図32に示した従来例のIGBTと比較しながら説明をする。まず、実施の形態1に従い、隣り合うゲートトレンチ7の間に1本のダミートレンチ8を設けたIGBTを作製した(以下、第1実施例とする)。IGBTの製造方法および設計条件は、実施例1と同様である。比較として、隣り合うゲートトレンチ7の間にダミートレンチ8を設けていないIGBTを作製した(従来例、図32参照)。従来例については、実施例1と同様のパラメータで形成し、ゲートトレンチ7の長手方向におけるp型ベース層4の長さは実施例1と同じ8μmとした。また、同じくゲートトレンチ7の長手方向において、隣り合うp型ベース層4の間隔についても、実施例1と同じとした。さらに、ゲートトレンチ7の長手方向に垂直な向きの、p型ベース層4とゲートトレンチ7の周期構造における単位周期も、実施例1と同様である。そして、第1実施例および比較例のそれぞれについて、静電容量Cxおよびコレクタ-エミッタ間電圧VCEを測定し、IGBTの電気的特性について検証した。
実施の形態2にかかる半導体装置について、図4を用いて説明する。図4は、実施の形態2にかかる半導体装置の要部を示す斜視図である。実施の形態2における実施の形態1との相違点は、メサ領域18におけるダミートレンチ8の本数である。実施の形態2では、隣り合うゲートトレンチ7の間に、例えば2本のダミートレンチ8をストライプ状の平面レイアウトで設けている。それぞれのメサ領域18における2本のダミートレンチ8の長手方向の端部は、互いに接続されている。
実施の形態2の効果について検証する。図7は、実施例3にかかる半導体装置の電気的特性を示す特性図である。図7は、実施の形態2のIGBTと、従来例のIGBTとの入力容量Ciesおよび帰還容量Cresにおけるコレクタ-エミッタ間電圧VCEの依存性(C-V特性)を比較したグラフである。まず、実施の形態2に従い、隣り合うゲートトレンチ7の間に2本のダミートレンチ8を設けたIGBTを作製した(以下、第2実施例とする)。第2実施例のその他の設計条件は、第1実施例と同様である。比較として、実施例2と同様に、従来例のIGBTを作製した。そして、第2実施例および比較例のそれぞれについて、静電容量CxおよびCE間電圧VCEを測定し、IGBTの電気的特性について検証した。測定方法および算出方法は、実施例2と同様である。
図8は、実施例4にかかる半導体装置の電気的特性を示す特性図である。図8は、実施の形態1,2のIGBT、および従来例のIGBTのオン時における電流-電圧(I-V)特性を比較した図である。なお、曲線上の丸印は、各曲線がどのIGBTに対応しているかが分かるように示したものに過ぎない。定格電流密度を225A/cm2と定義し、図8横軸に平行な実線にて示す。まず、実施例2と同様に、第1実施例および比較例を作製した。また、実施例3と同様に、第2実施例を作製した。そして、第1,2実施例および比較例のそれぞれについて、コレクタ電流ICおよびCE間電圧VCEを測定し、IGBTの電気的特性について検証した。測定方法は、実施例2と同様である。
図9は、実施例5にかかる半導体装置の電気的特性を示す特性図である。図9は、実施の形態1,2のIGBT、および従来例のIGBTそれぞれのオン状態において、コレクタ電流ICが飽和したときの飽和電流値と、図8に示したオン電圧の相関を比較したグラフである。ここで、飽和電流値とは、ゲート電圧VGEを一定とし、オン電圧が100V以上に十分大きくなるまでコレクタ電流ICを流すと、周知のMOSゲートにおける電流飽和の効果のためにコレクタ電流ICが一定値に飽和したときの、電流値のことである。
図10は、実施例6にかかる半導体装置の電気的特性を示す特性図である。図10は、実施の形態2と従来例のIGBTそれぞれについてのターンオフ波形を比較した図である。まず、実施例3と同様に、第2実施例を作製した。実施例2と同様に、比較例を作製した。そして、第2実施例および比較例のそれぞれについて、後述するスイッチング評価回路を用いて、コレクタ電流IC、CE間電圧VCEおよびゲート電圧VGEを測定し、IGBTの電気的特性について検証した。次に、スイッチング評価回路について説明する。
図11は、実施例7にかかる半導体装置の電気的特性を示す特性図である。図11は、実施の形態1,2および従来例のそれぞれのIGBTにおいて、図10で示したターンオフ波形と同じスイッチング条件における、ターンオフ電流とターンオフ損失の関係を示した図である。まず、実施例2と同様に、第1実施例および比較例を作製した。また、実施例3と同様に、第2実施例を作製した。そして、第1,2実施例および比較例のそれぞれについて、ターンオフ損失およびコレクタ電流ICを測定し、IGBTの電気的特性について検証した。
図12は、実施例8にかかる半導体装置の電気的特性を示す特性図である。図12は、実施の形態1,2と、従来例の各々のIGBTにおいて、オン電圧とターンオフ損失の関係を示したグラフである。まず、実施例2と同様に、第1実施例および比較例を作製した。また、実施例3と同様に、第2実施例を作製した。そして、第1,2実施例および比較例のそれぞれについて、ターンオフ損失およびオン電圧を測定し、IGBTの電気的特性について検証した。
図13は、実施例9にかかる半導体装置の電気的特性を示す特性図である。図13は、実施の形態1,2と、従来例の各々のIGBTにおいて、ターンオフ時のゲート抵抗と同じくターンオフ時のサージ電圧との関係を示したグラフである。まず、実施例2と同様に、第1実施例および比較例を作製した。また、実施例3と同様に、第2実施例を作製した。そして、第1,2実施例および比較例のそれぞれについて、ターンオフサージ電圧およびゲート抵抗を測定し、IGBTの電気的特性について検証した。
図14は、実施例10にかかる半導体装置の電気的特性を示す特性図である。図14は、実施の形態1,2と、従来例の各々のIGBTにおいて、ターンオン波形を比較した図である。まず、実施例2と同様に、第1実施例および比較例を作製した。また、実施例3と同様に、第2実施例を作製した。そして、第1,2実施例および比較例のそれぞれについて、コレクタ電流IC、CE間電圧VCEおよびゲート電圧VGEを測定し、IGBTの電気的特性について検証した。測定方法は、実施例6と同様である。
図15は、実施例11にかかる半導体装置の電気的特性を示す特性図である。図15は、従来例(図15(a))と実施の形態2(図15(b))の各々のIGBTにおいて、短絡時の波形を比較した図である。まず、実施例3と同様に、第2実施例を作製した。実施例2と同様に、比較例を作製した。そして、第2実施例および比較例のそれぞれについて、コレクタ電流IC、CE間電圧VCEおよびゲート電圧VGEを測定し、IGBTの電気的特性について検証した。測定方法は、実施例6と同様である。
図16は、実施例12にかかる半導体装置の電気的特性を示す特性図である。図16は、本発明の実施の形態1,2と従来例の各々のIGBTにおいて、ターンオフ時のゲート抵抗と短絡時のターンオフスパイク電圧(CE間のサージ電圧の最大値)波形を比較したグラフである。まず、実施例2と同様に、第1実施例および比較例を作製した。また、実施例3と同様に、第2実施例を作製した。そして、第1,2実施例および比較例のそれぞれについて、短絡時におけるターンオフスパイク電圧およびゲート抵抗を測定し、IGBTの電気的特性について検証した。
本発明の実施の形態3にかかる半導体装置について、図17を用いて説明する。図17は、実施の形態3にかかる半導体装置の要部を示す断面図である。実施の形態3における実施の形態1との相違点は、メサ領域18におけるダミートレンチ8の幅が広いことである。実施の形態3では、ダミートレンチ8の本数を1本に減らしつつ、ダミートレンチ8が2本のときと同様のミラー容量低減効果を得ることが可能である。さらにエミッタ電極12とコンタクトをとって同電位とする場合、エミッタ電極12とダミーポリシリコン11bが接触する面積が広くなるので、エミッタ電極12とダミーポリシリコン11b間の接触抵抗を十分小さくすることが可能となる。
本発明の実施の形態4にかかる半導体装置について、図18を用いて説明する。図18は、実施の形態4にかかる半導体装置の要部を示す平面図である。実施の形態4における実施の形態2との相違点は、以下の通りである。メサ領域18の内部に形成された2本のダミートレンチ8について、隣接する2本のダミートレンチ8をその長手方向における端部だけでなく中間部分28でも相互に接続している。その結果、ダミーポリシリコン11bも中間部分28においてつながっている。
本発明の実施の形態5にかかる半導体装置について、図19,20を用いて説明する。図19は、実施の形態5にかかる半導体装置の要部を示す断面図である。また、図20は、図19のIGBTの要部を示す平面図である。実施の形態5における実施の形態2との相違点は、隣り合う2本のダミートレンチ8の上面までダミーポリシリコン11bを形成してブリッジ部分29を設けることで、メサ領域18を挟んでダミーポリシリコン11bを相互にブリッジ状に接続させることである。そして、ダミーポリシリコン11bのブリッジ部分29上面に、ダミーポリシリコン11bとエミッタ電極12とのコンタクトをとるための開口部であるポリシリコンパッド17(図20)を設けている。
本発明の実施の形態6にかかる半導体装置について、図21を用いて説明する。図21は、実施の形態6にかかる半導体装置の要部を示す斜視図である。実施の形態6における実施の形態1との相違点は、p型ベース層4の上面に設けたコンタクト開口部14について、ゲートトレンチ7の長手方向に沿った開口部の長さを短くし、コンタクト開口部14がダミートレンチ8の長手方向端部にかからないようにしたことである。つまり、ダミーポリシリコン11bがエミッタ電極と接触しないようにすることで、ダミーポリシリコン11bの電位を浮遊(フローティング)としている。ダミーポリシリコン11bの電位を浮遊とした場合、エミッタ電極と接続した場合ほどではないものの、従来例に比べて、その75%の値までミラー容量は低減された。
本発明の実施の形態7にかかる半導体装置について、図22を用いて説明する。図22は、実施の形態7にかかる半導体装置の要部を示す断面図である。実施の形態7における実施の形態2との相違点は、メサ領域18におけるダミートレンチ8の本数を、さらに3本としたことである。つまり、メサ領域18におけるダミートレンチ8の本数は、3本に限らず複数本あっても好ましい。
本発明の実施の形態8にかかる半導体装置について、図23を用いて説明する。図23は、実施の形態8にかかる半導体装置の要部を示す斜視図である。また、図24は、図23の切断線C-C’における断面図である。実施の形態8における実施の形態2との相違点は、メサ領域18において、ゲートトレンチ7とダミートレンチ8を隣接させる、または十分近接させたことである。図24のように、ダミーポリシリコン11bをエミッタ電極と同電位とすることがなお好ましい。ここで、ゲートトレンチ7とダミートレンチ8を十分近接させるとは、ゲートトレンチ7とダミートレンチ8との間のメサ領域18の幅が、例えばゲート酸化膜10の厚さ(例えば0.1μm)程度にまで近いことを意味している。あるいは、ゲート酸化膜10を熱酸化にて形成する場合において、ゲートトレンチ7とダミートレンチ8の間が、熱酸化のパイルアップにより狭まり、熱酸化膜の厚さよりも薄くなる程度であってもよい。
本発明の実施の形態9にかかる半導体装置について、図25を用いて説明する。図25は、実施の形態9にかかる半導体装置の要部を示す断面図である。実施の形態9における実施の形態8との相違点は、2本のダミートレンチ8が隣接または十分近接していて、隣り合うゲートトレンチ7とは離間していることである。このようにすれば、前述のようにゲートポリシリコン11aとダミーポリシリコン11bがショートする危険性を避けることができ、かつミラー容量を低減することが可能となる。ここで、ダミートレンチ8の本数は、2本に限らず種々変更可能であり、3本あるいはそれ以上でもよい。また、ダミーポリシリコン11bをエミッタ電極12に接続することで、前述のようにミラー容量が十分低減できるので、なお好ましい。
本発明の実施の形態10にかかる半導体装置について、図26,27を用いて説明する。図26は、実施の形態10にかかる半導体装置の要部を示す斜視図である。また図27は、図26の切断線D-D’における断面図である。実施の形態10の特徴は、以下の通りである。ゲートトレンチ7に挟まれるメサ領域18において、ゲートトレンチ7の長手方向にて隣り合うp型ベース層4の間の全てにダミートレンチ8を設けている。そして、隣り合うゲートトレンチ7またはダミートレンチ8は、互いに接するかまたは十分近接するように配置している。それ以外の構成は、実施の形態1と同様である。
本発明の実施の形態11にかかる半導体装置について、図28を用いて説明する。図28は、実施の形態11にかかる半導体装置の要部を示す平面図である。実施の形態11の特徴は、p型ベース層4の配置を、これまでの市松模様ではなく、図28のようにゲートトレンチ7の長手方向に直行する方向に一列に並べたことである。それ以外の構成は、実施の形態1と同様である。このようにp型ベース層4を配置しても、ミラー容量の低減効果を奏することは可能である。
2 n型フィールドストップ層
3 p型コレクタ層
4 p型ベース層
5 n型エミッタ層
6 p型コンタクト層
7 ゲートトレンチ
8 ダミートレンチ
9 層間絶縁膜
10 ゲート酸化膜
11a ゲートポリシリコン
11b ダミーポリシリコン
12 エミッタ電極
13 コレクタ電極
14 コンタクト開口部
15 ゲート電極
16 空乏層端
17 ポリシリコンパッド
18 メサ領域
19 pn接合
20 直流電源
21 コンデンサ
22 ゲート駆動用電源
23 ゲート抵抗
24 IGBT
25 FWD
26 誘導負荷
27 浮遊インダクタンス
28 中間部分
29 ブリッジ部分
30 浮遊p層
Claims (11)
- 第1導電型の第1の半導体層と、
前記第1の半導体層の上に設けられた第2導電型の第2の半導体層と、
前記第2の半導体層の表面に複数形成されたストライプ状の第1の溝と、
前記第1の溝内に絶縁膜を介して形成されたゲート電極と、
前記第1の溝間の長手方向に選択的に形成された複数の第1導電型の第3の半導体層と、
前記第3の半導体層の表面に選択的に形成された第2導電型の第4の半導体層と、
前記第3の半導体層と前記第4の半導体層に接するエミッタ電極と、
前記第1の半導体層に接するコレクタ電極と、を有する絶縁ゲート型半導体装置において、
隣り合う前記第1の溝の間に当該第1の溝と平行に設けられ、かつ2つの前記第3の半導体層の間に挟まれた第2の溝が1つ以上形成されていることを特徴とする半導体装置。 - 前記第2の溝内には絶縁膜を介して第1の導電体が埋め込まれており、
前記第1の導電体は前記ゲート電極とは離間していることを特徴とする請求項1に記載の半導体装置。 - 前記第1の導電体は前記エミッタ電極と接続していることを特徴とする請求項2に記載の半導体装置。
- 前記第1の導電体は、前記第2の溝の長手方向の端部にて前記エミッタ電極と接続していることを特徴とする請求項3に記載の半導体装置。
- 隣り合う前記第1の溝の間に形成された前記第2の溝が2つ以上形成されていることを特徴とする請求項2に記載の半導体装置。
- 1つ以上形成された前記第2の溝の内部に形成されている前記第1の導電体は、互いに同一の電位となるように電気的に接続されていることを特徴とする請求項5に記載の半導体装置。
- 互いに隣り合う前記第2の溝は、当該第2の溝の長手方向の端部にて相互に接続され、
前記第2の溝の内部に形成された前記第1の導電体は、前記端部にて相互に接続されていることを特徴とする請求項6に記載の半導体装置。 - 隣り合う前記第2の溝の上面には、前記隣り合う第2の溝の内部に形成された前記第1の導電体を互いに接続するように前記第1の導電体に接する第2の導電体が形成されており、
前記第2の導電体は、当該第2の導電体の一部にて前記エミッタ電極と接続していることを特徴とする請求項6に記載の半導体装置。 - 前記第1の導電体が浮遊の電位となるように、前記エミッタ電極およびコレクタ電極および前記ゲート電極と前記第1の導電体は離間していることを特徴とする請求項2に記載の半導体装置。
- 前記第1の溝と前記第2の溝とが、前記第1の溝の長手方向の側壁または第2の溝の長手方向の側壁にて互いに隣接していることを特徴とする請求項1に記載の半導体装置。
- 前記第1の溝と前記第2の溝との間隔は、熱平衡状態において前記第2の半導体層と前記第3の半導体層とからなるpn接合から前記第2の半導体層に広がるビルトイン空乏層幅よりも小さいことを特徴とする請求項1~10のいずれか一つに記載の半導体装置。
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WO2015162811A1 (ja) * | 2014-04-21 | 2015-10-29 | 三菱電機株式会社 | 電力用半導体装置 |
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JP7211516B2 (ja) | 2019-07-12 | 2023-01-24 | 富士電機株式会社 | 半導体装置 |
WO2022014623A1 (ja) * | 2020-07-15 | 2022-01-20 | 富士電機株式会社 | 半導体装置 |
JP7405261B2 (ja) | 2020-07-15 | 2023-12-26 | 富士電機株式会社 | 半導体装置 |
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CN102792448A (zh) | 2012-11-21 |
EP2546882A1 (en) | 2013-01-16 |
JPWO2011111500A1 (ja) | 2013-06-27 |
US20150318386A1 (en) | 2015-11-05 |
EP2546882B1 (en) | 2018-04-18 |
US9099522B2 (en) | 2015-08-04 |
CN102792448B (zh) | 2015-09-09 |
US9634130B2 (en) | 2017-04-25 |
EP2546882A4 (en) | 2014-12-31 |
US20130037853A1 (en) | 2013-02-14 |
JP5488691B2 (ja) | 2014-05-14 |
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