JP6187697B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6187697B2 JP6187697B2 JP2016532503A JP2016532503A JP6187697B2 JP 6187697 B2 JP6187697 B2 JP 6187697B2 JP 2016532503 A JP2016532503 A JP 2016532503A JP 2016532503 A JP2016532503 A JP 2016532503A JP 6187697 B2 JP6187697 B2 JP 6187697B2
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- 239000004065 semiconductor Substances 0.000 title claims description 82
- 239000003990 capacitor Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 230000015556 catabolic process Effects 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 64
- 238000010586 diagram Methods 0.000 description 15
- 230000003071 parasitic effect Effects 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 6
- 239000002344 surface layer Substances 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Description
図1〜図3は、この発明に係る実施の形態1の半導体装置の構成図である。図1Aは、半導体装置全体の平面図である。図1Bは、図1Aのa部拡大図である。図2Aは、図1BのIIA−IIAで切断した要部の構造を示す断面図である。図2Bは、図1BのIIB−IIB線で切断した要部の構造を示す断面図である。図3は図1BのIII−III線で切断した要部の構造を示す断面図である。
図6は、この発明に係る実施の形態2の半導体装置200の全体の平面図である。実施の形態1に示した、図1〜図3の半導体装置100との違いは、活性領域32に形成される同一の長さのストライプのトレンチ33を配置した点である。また、2つの第1IGBTセル群34を第1ゲートランナー36で取り囲み、2つの第2IGBTセル群35を第2ゲートランナー37で取り囲む構成にした点である。
図7は、この発明に係る実施の形態3の半導体装置300の要部の構造を示す断面図である。この断面図は、実施の形態1における図3に相当する断面図である。実施の形態1の半導体装置100との違いは、コンデンサ18を半導体基板23上に層間絶縁膜22を介して配置した点である。すなわち、図7に示すように、第1ゲートランナー14と第2ゲートランナー15で誘電体21を挟んでコンデンサ18を形成した点である。それ以外の構成については、実施の形態1または実施の形態2と同じである。
図8は、この発明に係る実施の形態4の半導体装置400の要部の構造を示す断面図である。この断面図は、実施の形態1における図3に相当する断面図である。実施の形態1の半導体装置100との違いは、コンデンサ18上に抵抗38を配置し互いに並列接続してdi/dt緩和素子を構成した点である。
図9および図10は、この発明に係る実施の形態5の半導体装置500の構成図である。図9Aは全体の平面図である。図9Bは図9Aのa部拡大図である。図10は図9BのX−Xで切断した要部の構造を示す断面図である。図11は、図9および図10に示す半導体装置500の等価回路図である。
2 nバッファ層
3 nドリフト層
4 pウェル層
5、6、16、33 トレンチ
7 ゲート絶縁膜
8 第1ゲート電極
9 第2ゲート電極
10 第1nエミッタ層
11 第2nエミッタ層
12、34 第1IGBTセル群
13、35 第2IGBTセル群
14、36 第1ゲートランナー
15、37 第2ゲートランナー
17 絶縁膜
18 コンデンサ
19 第1電極
20 第2電極
21 誘電体
22 層間絶縁膜
23 半導体基板
24 コレクタ電極
25 エミッタ電極
26、32 活性領域
27 トレンチ群
28 ゲート端子
29 コレクタ端子
30 エミッタ端子
31 寄生ゲート・エミッタ容量
31a 合計の寄生ゲート・エミッタ容量
38 抵抗
39 ダイオード
Claims (5)
- 半導体基板と、前記半導体基板に設けられたMOS型スイッチング素子を有する活性領域と、前記活性領域を囲むように設けられた耐圧構造領域と、前記活性領域と前記耐圧構造領域との間あるいは前記活性領域間に設けられるゲートランナーと、を備えた半導体装置であって、
前記活性領域は、前記MOS型スイッチング素子のゲート電極が前記ゲートランナーに直接接続する第1セル群と、di/dt緩和素子を介して前記ゲートランナーに接続する第2セル群とを有しており、
前記di/dt緩和素子が、コンデンサ、または、コンデンサと並列接続される抵抗であり、
前記コンデンサが、前記半導体基板に配置されるトレンチと、前記トレンチの内壁を被覆する絶縁膜と、前記トレンチ内に絶縁膜を介して両側に配置されるポリシリコンで形成された電極と、前記電極に挟まれて配置される誘電体と、を具備することを特徴とする半導体装置。 - 半導体基板と、前記半導体基板に設けられたMOS型スイッチング素子を有する活性領域と、前記活性領域を囲むように設けられた耐圧構造領域と、前記活性領域と前記耐圧構造領域との間あるいは前記活性領域間に設けられるゲートランナーと、を備えた半導体装置であって、
前記活性領域は、前記MOS型スイッチング素子のゲート電極が前記ゲートランナーに直接接続する第1セル群と、di/dt緩和素子を介して前記ゲートランナーに接続する第2セル群とを有しており、
前記di/dt緩和素子が、コンデンサ、または、コンデンサと並列接続される抵抗であり、
前記コンデンサが、前記第1セル群のゲート配線および前記第2セル群のゲート配線を電極とし、両者の間に挟まれた誘電体で構成されることを特徴とする半導体装置。 - 半導体基板と、前記半導体基板に設けられたMOS型スイッチング素子を有する活性領域と、前記活性領域を囲むように設けられた耐圧構造領域と、前記活性領域と前記耐圧構造領域との間あるいは前記活性領域間に設けられるゲートランナーと、を備えた半導体装置であって、
前記活性領域は、前記MOS型スイッチング素子のゲート電極が前記ゲートランナーに直接接続する第1セル群と、di/dt緩和素子を介して前記ゲートランナーに接続する第2セル群とを有しており、
前記di/dt緩和素子が、逆並列接続されたダイオードであることを特徴とする半導体装置。 - 前記ダイオードが、ポリシリコンで形成されることを特徴とする請求項6に記載の半導体装置。
- 前記MOS型スイッチング素子が、絶縁ゲート型バイポーラトランジスタであることを特徴とする請求項4から7のいずれか一つに記載の半導体装置。
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