CN105874602B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN105874602B
CN105874602B CN201580003528.7A CN201580003528A CN105874602B CN 105874602 B CN105874602 B CN 105874602B CN 201580003528 A CN201580003528 A CN 201580003528A CN 105874602 B CN105874602 B CN 105874602B
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semiconductor device
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CN105874602A (zh
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佐藤茂树
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Fuji Electric Co Ltd
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Abstract

通过在与第一IGBT单元组(12)的第一栅极(8)连接的第一栅极流道(14)和与第二IGBT单元组(13)的第二栅极(9)连接的第二栅极流道(15)之间连接电容器(18)，能够使半导体装置(100)的导通、关断时的di/dt平缓。如此，能够提供减小栅极驱动电力，从而能够抑制导通、关断时的电流、电压的波动的半导体装置。

Description

半导体装置
技术领域
本发明涉及一种半导体装置。
背景技术
以往，在对旋转马达、伺服马达的控制中不可或缺的变换器-逆变器等电力变换装置中，搭载有功率二极管、绝缘栅双极型晶体管(IGBT)等半导体装置。
图12是以往的形成为沟槽结构的半导体装置600的整体俯视图。另外，图13是表示沿图12的XIII-XIII线切断的主要部分的结构的剖视图。对于该半导体装置600，例举出了IGBT。
在图12和图13中，在配置于半导体基板83的p集电层61上配置有n缓冲层62，并在n缓冲层62上配置有n漂移层63。在n漂移层63的表面层配置有p阱层64。配置有贯通该p阱层64而到达n漂移层63的沟槽65。在沟槽65的内壁隔着栅极绝缘膜67填充有多晶硅并配置有栅极68。在由沟槽65夹住的p阱层64的表面层选择性地配置有n发射层70。
IGBT单元72a由p集电层61、n缓冲层62、n漂移层63、p阱层64、n发射层70以及配置在沟槽65内的栅极68构成。p集电层61连接到集电极84，n发射层70连接到发射极85。发射极85和栅极68利用层间绝缘膜82电绝缘。作为IGBT单元72a的集合体的IGBT单元组72被栅极流道(gate runner)74分割成四部分，并配置于活性区86。栅极流道74连接到栅极端子88。
图14是图12所示的半导体装置600的内部的等效电路图。多个IGBT单元72a并联，栅极流道74连接到栅极端子88，IGBT单元组72的集电极84连接到集电极端子89，IGBT单元组72的发射极85连接到发射极端子90。
若向栅极端子88输入导通信号，则各IGBT单元72a同时导通。通过微细化使单元间隔变窄，并内置有多个单元的高性能的IGBT(半导体装置600)使电子的注入效率变大，能够以相同的芯片尺寸(半导体基板83的尺寸)流通较大的集电极电流。因此，导通时和关断时的di/dt变大。
若该di/dt变大，则IGBT的导通时和关断时的电流、电压产生波动。该电流电压的波动产生辐射噪声，除了导致IGBT自身的误动作之外，还产生使邻接的栅极驱动电路、电子设备误动作的不良情况。
为了防止其波动，而具有设置多个独立的栅极端子，并在栅极驱动电路具有移位寄存器，将栅极输出信号依次延迟地输入到栅极端子的方法(例如，下述专利文献1)。由此，IGBT单元组依次延迟地进行导通或者关断，di/dt变得平缓。
现有技术文献
专利文献
专利文献1：日本特开平8-32064号公报
发明内容
技术问题
然而，在上述的专利文献1中记载的方法中，存在需要移位寄存器电路、驱动电路变得复杂的问题。
为了消除上述现有技术的问题，因而本发明的目的在于提供一种利用简单的方法使导通时和关断时的di/dt平缓，并减少栅极驱动电力，从而能够抑制导通、关断时的电流、电压的波动的半导体装置。
技术方案
为了解决上述的课题，实现本发明的目的，因而本发明的半导体装置具备：半导体基板、设置于上述半导体基板的具有MOS型开关元件的活性区、以包围上述活性区的方式设置的耐压结构区、以及设置在上述活性区与上述耐压结构区之间或上述活性区之间的栅极流道，上述活性区具有上述MOS型开关元件的栅极直接连接到上述栅极流道的第一单元组和上述MOS型开关元件的栅极经由di/dt缓和元件连接到上述栅极流道的第二单元组。
另外，本发明的半导体装置优选为，在上述的发明中，上述di/dt缓和元件为电容器、电容器和与上述电容器并联的电阻、反向并联的二极管中的任一种。
另外，本发明的半导体装置优选为，在上述的发明中，上述MOS型开关元件为绝缘栅双极型晶体管(IGBT)。
另外，本发明的半导体装置是如下的构成，在上述的发明中，上述电容器具备：配置于上述半导体基板的沟槽、被覆上述沟槽的内壁的绝缘膜、由在上述沟槽内隔着绝缘膜配置在两侧的多晶硅形成的电极、以及被上述电极所夹而配置的电介质。
另外，本发明的半导体装置优选为，在上述的发明中，上述电容器以上述第一单元组的栅极布线和上述第二单元组的栅极布线为电极，并且由夹在两者之间的电介质构成。
另外，本发明的半导体装置优选为，在上述的发明中，上述二极管由多晶硅形成。
发明效果
根据本发明，使导通时和关断时的di/dt平缓，从而能够抑制导通、关断时的电流、电压的波动，另外，能够减少栅极驱动电力。
附图说明
图1A是本发明的实施方式1的半导体装置100的整体俯视图。
图1B是图1A的a部的放大俯视图。
图2A是表示沿图1B的IIA-IIA切断的主要部分的结构的剖视图。
图2B是表示沿图1B的IIB-IIB切断的主要部分的结构的剖视图。
图3是表示沿图1B的III-III切断的主要部分的结构的剖视图。
图4是半导体装置100的等效电路图。
图5A是栅极电压波形图。
图5B是栅极端子28、电容器18以及寄生栅极-发射极电容31的连接图。
图5C是表示第一IGBT单元组12、第二IGBT单元组13以及IGBT(半导体装置100)的导通时的di/dt的说明图。
图6是本发明的实施方式2的半导体装置200的整体俯视图。
图7是表示本发明的实施方式3的半导体装置300的主要部分的结构的剖视图。
图8是表示本发明的实施方式4的半导体装置400的主要部分的结构的剖视图。
图9A是本发明的实施方式5的半导体装置500的整体俯视图。
图9B是图9A的a部的放大俯视图。
图10是表示沿图9B的X-X切断的主要部分的结构的剖视图。
图11是半导体装置500的等效电路图。
图12是以往的形成为沟槽结构的半导体装置600的整体俯视图。
图13是表示沿图12的XIII-XIII线切断的主要部分的结构的剖视图。图14是半导体装置600的内部的等效电路图。
符号说明
1：p集电层
2：n缓冲层
3：n漂移层
4：p阱层
5、6、16、33：沟槽
7：栅极绝缘膜
8：第一栅极
9：第二栅极
10：第一n发射层
11：第二n发射层
12、34：第一IGBT单元组
13、35：第二IGBT单元组
14、36：第一栅极流道
15、37：第二栅极流道
17：绝缘膜
18：电容器
19：第一电极
20：第二电极
21：电介质
22：层间绝缘膜
23：半导体基板
24：集电极
25：发射极
26、32：活性区
27：沟槽组
28：栅极端子
29：集电极端子
30：发射极端子
31：寄生栅极-发射极电容
31a：总计的寄生栅极-发射极电容
38：电阻
39：二极管
具体实施方式
以下，对于本发明的半导体装置的优选实施方式，参照本说明书和附图进行详细的说明。在本说明书和附图中，在前缀有n或p的层和区域中，分别表示电子或者空穴为多数载流子。应予说明，在以下的实施方式的说明和附图中，对相同的构成标记相同的符号，并省略重复的说明。另外，在实施方式中说明的附图为了易于观察或易于理解，而没有以正确的尺寸、比例进行绘制。并且，本发明只要不超出其主旨，就不限于以下说明的实施方式的记载。
(实施方式1)
图1～图3是本发明的实施方式1的半导体装置的构成图。图1A是半导体装置的整体俯视图。图1B是图1A的a部放大图。图2A是表示沿图1B的IIA-IIA切断的主要部分的结构的剖视图。图2B是表示沿图1B的IIB-IIB切断的主要部分的结构的剖视图。图3是表示沿图1B的III-III切断的主要部分的结构的剖视图。
在图1A和图1B中，在半导体基板23的外周设置有未图示的耐压结构区，在其内侧配置有第一栅极流道14。活性区26被第一栅极流道14分割为例如四个部分而配置。在被分割而成的各活性区26配置有具有长条纹状的四根第一沟槽5的第一IGBT单元组12和具有短条纹状的四根第二沟槽6的第二IGBT单元组13。在实施方式1中，第一沟槽5、第二沟槽6的根数为四根，但不限于此。
如图1B所示，第一IGBT单元组12的第一栅极8连接到第一栅极流道14，第二IGBT单元组13的第二栅极9连接到第二栅极流道15。第一栅极流道14、第二栅极流道15分别连接到作为di/dt缓和元件的电容器18的作为多晶硅电极的第一电极19、第二电极20。第一栅极流道14和第二栅极流道15为栅极布线，例如由铝等金属形成。
第一沟槽5、第二沟槽6分别集合而形成沟槽组27。沟槽组27被配置在四个位置，各个沟槽组27被第一栅极流道14包围。第一栅极流道14连接到第一IGBT单元组12的第一栅极8，并且连接到一个栅极端子28。第二栅极流道15连接到第二IGBT单元组13的第二栅极9。
如后所述，由配置于一个沟槽5的栅极8、配置在该沟槽的两侧的n发射层10、以及配置在它们的正下方的n漂移层3、n缓冲层2和p集电层1构成一个IGBT单元。这样的一个IGBT单元集合而成为第一IGBT单元组12。同样地，由配置于一个沟槽6的栅极9、配置于该沟槽的两侧的n发射层11、以及配置在它们的正下方的n漂移层3、n缓冲层2和p集电层1构成一个IGBT单元。这样的一个IGBT单元集合而成为第二IGBT单元组13。
通过在第一栅极流道14与第二栅极流道15之间连接电容器18，从而输入到栅极端子28的栅极输入电压Vin作为降低的栅极电压而传递到第二IGBT单元组13的第二栅极9。因此，第二IGBT单元组13的di/dt变小，其结果，IGBT(半导体装置100)的导通、关断时的di/dt变得平缓。通过使di/dt变得平缓，能够防止在IGBT的集电极-发射极电压和集电极电流上产生的波动。
图2A中，在p集电层1上配置有n缓冲层2，在n缓冲层2上配置有n漂移层3。在n漂移层3的表面层配置有p阱层4。配置有贯通该p阱层4而到达n漂移层3的长的第一沟槽5和短的第二沟槽6。在第一沟槽5、第二沟槽6的内壁隔着栅极绝缘膜7填充有多晶硅且配置有第一栅极8、第二栅极9。在由第一沟槽5或者第二沟槽6夹住的p阱层4的表面层配置有第一n发射层10或第二n发射层11。
第一IGBT单元组12由p集电层1、n缓冲层2、n漂移层3、p阱层4、第一n发射层10以及配置于第一沟槽5的第一栅极8构成。另外，第二IGBT单元组13由p集电层1、n缓冲层2、n漂移层3、p阱层4、第二n发射层11以及配置在第二沟槽6内的第二栅极9构成。这些第一IGBT单元组12和第二IGBT单元组13配置于被第一栅极流道14包围的活性区26。
p集电层1连接到集电极24，第一发射层10、第二发射层11连接到发射极25。发射极25和第一栅极8、第二栅极9利用层间绝缘膜22电绝缘。
图2B中，在第一沟槽5的两侧配置有第一n发射层10，在第二沟槽6的两侧没有配置第二n发射层11。另外，在连接到第一栅极8的第一栅极流道14的内侧配置有连接到第二栅极9的第二栅极流道15。第一栅极流道14和第二栅极流道15通过层间绝缘膜22与p阱层4电绝缘。
另外，第一栅极流道14和第一栅极8、以及第二栅极流道15和第二栅极9通过设置于层间绝缘膜22的接触孔而电连接。
图3中，配置有贯通p阱层4而到达n漂移层3的第三沟槽16，所述p阱层4配置在包含第一栅极流道14和第二栅极流道15的端部附近且被第一栅极流道14和第二栅极流道15的端部夹住的位置的下方，并且在该第三沟槽16的内壁配置有绝缘膜17。这里，使第三沟槽16的深度与第一沟槽5、第二沟槽6的深度相同，但也可以在p阱层4内形成浅的第三沟槽16。
在该第三沟槽16内隔着绝缘膜17配置电容器18。电容器18由第一电极19、第二电极20以及夹于第一电极19、第二电极20之间的电介质21构成。作为电介质21，例如有树脂、绝缘体等。在图1A中在一个第二IGBT单元组13中配置有两个该电容器18。在第二栅极流道15不被分割为两部分而连接成一个时，该电容器18可以为一个。
第一电极19电连接到第一栅极流道14的端部，第二电极20电连接到第二栅极流道15的端部。该第一电极19、第二电极20例如由与第一栅极8、第二栅极9相同的多晶硅形成。另外，绝缘膜17例如由与栅极绝缘膜7相同的氧化膜形成。通过如此的构成，能够将电容器18形成在半导体基板23内。
图4是图1～图3所示的半导体装置100的等效电路图。图4中，电容器18为一个。另外，在构成第一IGBT单元组12的IGBT单元的第一栅极8和第一n发射层10之间形成的寄生栅极-发射极电容31、在构成第二IGBT单元组13的IGBT单元的第一栅极9和第一n发射层10之间形成的寄生栅极-发射极电容31是相同的，均以虚线表示。
栅极端子28连接到第一栅极流道14，第一栅极流道14连接到第一IGBT单元组12的第一栅极8。第二栅极流道15连接到第二IGBT单元组13的第二栅极9。在第一栅极流道14与第二栅极流道15之间连接有电容器18。集电极24电连接到集电极端子29。发射极25连接到发射极端子30。
图5A～图5C是对半导体装置100的动作进行说明的图。图5A是栅极电压波形图。图5B是栅极端子28、电容器18以及寄生栅极-发射极电容31的连接图。图5C是表示第一IGBT单元组12、第二IGBT单元组13以及IGBT(半导体装置100)的导通时的di/dt的说明图。
从栅极端子28输入的栅极输入电压Vin经由第一栅极流道14而作为第一栅极电压Vg1输入到第一IGBT单元组12的第一栅极8。该栅极输入电压Vin在电容器18与第二IGBT单元组13的寄生栅极-发射极电容31(图5B中以总计的寄生栅极-发射极电容31a表示)之间被分压，并经由第二栅极流道15而作为第二栅极电压Vg2输入到第二栅极9。栅极输入电压Vin上升快但第一栅极电压Vg1、第二栅极电压Vg2稍微变得平缓是因为布线电阻32。
通过使该被分压的低的第二栅极电压Vg2输入到第二IGBT单元组13的第二栅极9，从而使第二IGBT单元组13的导通、关断时的di/dt与第一IGBT单元组12的di/dt相比变得平缓。其结果，能够使将第一IGBT单元组12和第二IGBT单元组13合在一起的IGBT(半导体装置100)的导通时的di/dt平缓。
但是，会产生第二栅极电压Vg2的到达电压Vg2o变得比第一栅极电压Vg1的到达电压Vg1o低，第二IGBT单元组13的驱动困难的情况。为了防止该情况，优选使电容器18比第二IGBT单元组13的寄生栅极-发射极电容31大，并使第二IGBT单元组13的第二栅极电压Vg2的到达电压Vg2o比输入到第一IGBT单元组12的第一栅极电压Vg1的到达电压Vg1o的一半大。
越将电容器18的电容增大，输入到第二IGBT单元组13的第二栅极电压Vg2的到达电压Vg2o变得越高。然而，由于导通、关断时的di/dt变陡，所以优选第二栅极电压Vg2的到达电压Vg2o为第一栅极电压Vg1的到达电压Vg1o的90％以下。若使第二IGBT单元组13的总计的寄生栅极-发射极电容31a为nF数量级，则作为电容器18的电容，可以为数10nF～数100nF的程度。
为了使IGBT单元依次延迟地进行导通、关断从而使di/dt平缓，具有如下的方法，即在IGBT单元组的栅极多晶硅布线串联地插入栅极电阻Rg，以与存在于IGBT单元组的栅极-发射极之间的各寄生栅极-发射极电容Cg组合，调整各栅极电阻Rg，从而依次增大CR时间常数，但在该方法中，由于需要针对各IGBT单元组设置栅极电阻，所以构成变得复杂，进一步地存在在栅极电阻上产生损耗，栅极驱动电力变大的问题。
这样，根据实施方式1，与这样的依次增大CR时间常数的方法或使用上述的移位寄存器的方法相比，能够以更简单的构成使IGBT(半导体装置100)的di/dt平缓。并且，由于不产生因该电容器18所导致的消耗电力，所以与依次增大CR时间常数的方法相比，能够减少栅极驱动电力。
应予说明，作为上述的半导体装置100而例举了IGBT，但也可以是MOSFET(MOS栅型场效应晶体管)等。另外，作为半导体装置100的材料，除了硅之外，也可以是例如宽禁带材料，例如SiC(碳化硅)、GaN(氮化镓)等。
另外，在实施方式1中，以第一IGBT单元组12、第二IGBT单元组13的两级的IGBT单元组进行了说明，但也可以进一步增加级数。
另外，在实施方式1中，对于IGBT单元以沟槽栅型进行了说明，但也可以是平面栅型。
(实施方式2)
图6是本发明的实施方式2的半导体装置200的整体俯视图。与实施方式1所示的图1～图3的半导体装置100的不同点在于，配置了形成于活性区32的相同长度的条纹的沟槽33。另外，不同点为设置成了以第一栅极流道36包围两个第一IGBT单元组34，以第二栅极流道37包围两个第二IGBT单元组35的构成。
在第一栅极流道36与第二栅极流道37之间连接图1中设置的作为di/dt缓和元件的电容器18。除此以外的构成与实施方式1相同。
根据实施方式2，与实施方式1所示的半导体装置100同样地，能够以更简单的构成使IGBT(半导体装置200)的di/dt平缓。
(实施方式3)
图7是表示本发明的实施方式3的半导体装置300的主要部分的结构的剖视图。该剖视图是相当于实施方式1中的图3的剖视图。与实施方式1的半导体装置100的不同点在于，将电容器18隔着层间绝缘膜22配置在半导体基板23上。即，如图7所示，不同点在于利用第一栅极流道14与第二栅极流道15夹着电介质21而形成电容器18。除此以外的构成与实施方式1或实施方式2相同。
这样，根据实施方式3，与实施方式1所示的半导体装置100同样地，能够以更简单的构成使IGBT(半导体装置300)的di/dt平缓。
当然，也可以以图7的构成来形成图6的构成中的电容器。即，在实施方式2的半导体装置200中，也可应用实施方式3中的电容器18的构成。
(实施方式4)
图8是表示本发明的实施方式4的半导体装置400的主要部分的结构的剖视图。该剖视图是相当于实施方式1中的图3的剖视图。与实施方式1的半导体装置100的不同点在于，在电容器18上配置电阻38且彼此并联而构成di/dt缓和元件。
在仅插入电容器18的方法中第二栅极电压Vg2的到达电压Vg2o变得比第一栅极电压Vg1的到达电压Vg1o低。因此，通过连接电阻38，能够使第二栅极电压Vg2的到达电压Vg2o与第一栅极电压Vg1的到达电压Vg1o相同。除此以外的构成与实施方式1相同。
由此，所有IGBT单元组的动作进一步稳定化，能够确保IGBT(半导体装置400)的进一步的稳定动作。作为电阻38的值，若设定为例如数kΩ～数100Ω的程度，则能够延迟第二栅极电压Vg2成为到达电压Vg2o的时间，从而使di/dt平缓。
可以如下设定电阻38的值Ro，即，使由该电阻38的值Ro和第二IGBT单元组13的寄生栅极-发射极电容31的合计值Co构成的时间常数τ＝Ro×Co处于成为IGBT的集电极电流的上升或者下降的di/dt的时间区域中。
这样，根据实施方式4，与实施方式1所示的半导体装置100同样地，能够以更简单的构成使IGBT(半导体装置400)的di/dt平缓。
当然，也可以以图8的构成来形成图6的构成中的电容器。即，在实施方式2的半导体装置200中，也可以应用实施方式4中的电容器18和电阻38的构成。
(实施方式5)
图9和图10是本发明的实施方式5的半导体装置500的构成图。图9A是整体俯视图。图9B是图9A的a部放大图。图10是表示沿图9B的X-X切断的主要部分的结构的剖视图。图11是图9和图10所示的半导体装置500的等效电路图。
与实施方式1中的图1～图3的半导体装置100的不同点在于，代替电容器18而连接有反向并联的二极管39。该反向并联的二极管39成为di/dt缓和元件。通过在第一栅极流道14与第二栅极流道15之间连接反向并联的二极管39，能够使栅极输入电压Vin延迟地传递到第二栅极流道15，使第二IGBT单元组15的导通开始时间延迟数ns～数十ns的程度。
其结果，能够使IGBT(半导体装置500)的di/dt平缓。将二极管39反向并联是为了使导通时的di/dt和关断时的di/dt同时平缓。该二极管39可以通过在例如多晶硅中扩散p型杂质和n型杂质来制作。
另外，通过串联地连接多个该二极管39能够进一步增大延迟时间。换句话说，能够通过二极管39的串联数量来进行延迟时间的调整。
通常，为了使二极管39变成导通状态，需要在pn结蓄积一定量的载流子，其蓄积时间成为延迟时间。因此，延迟时间能够通过二极管39的pn结的面积进行控制。在该实施方式5中，利用二极管39的正向的结电容，使第二IGBT单元组13的栅极电压Vg2的上升时间延迟。
这样，根据实施方式5，与实施方式1所示的半导体装置100同样地，能够以更简单的构成使IGBT(半导体装置500)的di/dt平缓。
根据本发明，能够提供一种以更简单的方法使导通时和关断时的di/dt平缓，并减少栅极驱动电力从而能够抑制导通、关断时的电流、电压的波动的半导体装置。
以上，在本发明中，以IGBT为例进行了说明，但并不限于此，也可以应用于二极管等。
产业上的可利用性
以上，本发明的半导体装置对变换器、逆变器等电力变换装置等中使用的功率半导体装置有用。

Claims (7)

1.一种半导体装置，其特征在于，所述半导体装置具备：半导体基板、设置于所述半导体基板的具有MOS型开关元件的活性区、以包围所述活性区的方式设置的耐压结构区、以及设置在所述活性区与所述耐压结构区之间或所述活性区之间的栅极流道，
所述活性区具有所述MOS型开关元件的栅极直接连接到所述栅极流道的第一单元组和所述MOS型开关元件的栅极经由di/dt缓和元件连接到所述栅极流道的第二单元组，
所述di/dt缓和元件为电容器、或电容器和与所述电容器并联的电阻，
所述电容器具备：配置于所述半导体基板的沟槽、被覆所述沟槽的内壁的绝缘膜、在所述沟槽内隔着绝缘膜配置在两侧的由多晶硅形成的电极、以及以夹在所述电极之间的方式配置的电介质。
2.根据权利要求1所述的半导体装置，其特征在于，
所述MOS型开关元件为绝缘栅双极型晶体管。
3.一种半导体装置，其特征在于，所述半导体装置具备：半导体基板、设置于所述半导体基板的具有MOS型开关元件的活性区、以包围所述活性区的方式设置的耐压结构区、以及设置在所述活性区与所述耐压结构区之间或所述活性区之间的栅极流道，
所述活性区具有所述MOS型开关元件的栅极直接连接到所述栅极流道的第一单元组和所述MOS型开关元件的栅极经由di/dt缓和元件连接到所述栅极流道的第二单元组，
所述di/dt缓和元件为电容器，
所述电容器由作为电极的所述第一单元组的栅极布线和所述第二单元组的栅极布线和夹在两者之间的电介质构成。
4.根据权利要求3所述的半导体装置，其特征在于，
所述MOS型开关元件为绝缘栅双极型晶体管。
5.一种半导体装置，其特征在于，所述半导体装置具备：半导体基板、设置于所述半导体基板的具有MOS型开关元件的活性区、以包围所述活性区的方式设置的耐压结构区、以及设置在所述活性区与所述耐压结构区之间或所述活性区之间的栅极流道，
所述活性区具有所述MOS型开关元件的栅极直接连接到所述栅极流道的第一单元组和所述MOS型开关元件的栅极经由di/dt缓和元件连接到所述栅极流道的第二单元组，
所述di/dt缓和元件为反向并联的二极管。
6.根据权利要求5所述的半导体装置，其特征在于，
所述二极管由多晶硅形成。
7.根据权利要求5或6所述的半导体装置，其特征在于，
所述MOS型开关元件为绝缘栅双极型晶体管。
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